SU1022160A1 - Number-pulse function generator - Google Patents

Abstract

NUMBER-PULSE FUNCTIONAL ADVERTISER, containing an imputable adder, a double multiplier, and a first counter, the output of which is connected to an upstream chip input of the binary multiplier, the dual input of which is connected to the first multiplier of the binary multiplier, the first outlet, and a numeric byte and 104; The second input of which is connected to the input of the transform | of the body, characterized in that, in order to increase the range of performance without deteriorating the dynamic characteristics of the converter, it is not second and third counters and a controlled frequency divider, the pulse input of which is connected to the output of a pulse adder, output, one overflow of the first counter is connected to the input of the second and third counters, the third output is connected to a control of the input of a controlled frequency divider, the output of which is connected to in the first counter.

Description

The invention of ognosigs to iamerygelnaya and computing technology and can. to find application in devices for processing information presented in the form of a number-pulse code, frequency, or, time intervals.

It is known to construct a square root of the number of pulses, containing a VI-bit binary counter, a group of AND elements AND, and two OR elements. The device is a binary multiplier covered by a positive OFAT bond, with the control functions of the counter and the counter and the counter divider of the binary multiplier combined in one counter T Ij.

A disadvantage of this device is the narrow interval of the argument.

The closest in technical essence to the proposed device is a device containing a binary multiplier, an adder and a counter, with the input of the device connected to the first pulse input; an adder, the second input of which is connected to the output of an i-bit digital multiplier, the last input is connected to the output of a pulse adder and the input of a output counter of the result corresponding to the bit outputs of the C 3 binary multiplier

A disadvantage of the known device is the narrow interval of variation of the argument, given as the number of impulses, for which it can. be calculated. square root value The measurement range of the argument lies within O - 2, where AND is the bit size of the result counter and the binary multiplier. In practice, there are often cases when it is required to calculate the square root value from the number of pulses, which is much larger. To do this, you can simply increase the bit width of the device, but then there is a sharp drop in the arrival frequency of the input pulses of the argument. This is due to the fact that the input pulses, having passed through the summation circuit, fall on the input of the binary multiplier and the appearance of feedback pulses. Thus, for example, the first peak pulse at a device width of AND 5 causes the appearance of 7 and feedback pulses. The next input pulse of the argument can arrive when this cycle of 7 pulses ends.

At and 5, the known device calculates the square root value of the argument value lying within 0-16. If required, for example,

TO calculate the square root of, 2 then the required value of the number of bits of the device AND 11. In this case, the first input pulse already triggers 63 feedback pulses. This entails a reduction in the frequency of the input pulses of the argument. The phenomena described above observe not only at V, 1, but also at other values of X.

The goal of isophenenia is to increase the conversion range without degrading the dynamic characteristics of the preophazazole. The goal is achieved by the fact that the number-pulse functional converter containing a pulse adder, a binary multiplier and a first counter, the bit output of which is connected to the control input of a binary multiplier, the pulse input of which is connected to the input of the first counter, the output of the binary multiplier is connected to the first input of the impedance adder, the second input of which is connected to the input of the converter, is additionally introduced the second and third counters and a controlled frequency divider, the pulse input of which connected to the output of pulse adder vkod overflow of the first counter is connected to the input of the second and third counters, the third counter output is connected to the sound control & l yuschim entrance controllable frequency divider whose output is connected to the input of the first counter.

The drawing shows a block diagram of the device.

The device contains a pulse adder 1, a counter 2, a controlled divider 3 frequencies, a binary multiplier 4 and counters 5 and 6. Before starting work, counters 5 and 6, divider 3 and binary multiplier 4 are in the zero state, and in counter 2 is written unit

The device receives impulses of frequency y. The average frequency d at the output of binary multiplier 4 is determined by the frequency $ in the output from divider 3, and by the additional code of the number Wr entering counter 5, and is equal to

V-i.

(f ×

Frequency / | at the output of the impedance adder 1 is equal to

 (2-)

The pulses of this frequency are fed to the input of a controlled divider of the 3rd part, which in the general case implements the function

, | vi, z. Cr)

where Mn is the number recorded in counter 2. Since in this case N2.

therefore, from (1),

that

(2) and (3) dl.

(four)

but

The frequency pulses t are integrated by the counter 5, the code in which varies in time according to the law with regard to (4)

.u,

Solving this equation; is

.

Where

r X - tyt, i

With X, counter 5 overflows and is counted one by one in counters 2 and 6. Here, M 1 becomes 2, and the numbers stored in counters 5 and 6 are counted as one number.

rezuptrga M ,. counters 5 and 6 it is logical to consider the error counter as the result 5–6. Counter 5 stores the lowest binary bits of the result code, and counter 6 stores the oldest ones.

Thus, starting from the moment of time%;

I t meni t-,, number in the counter 5-G

varies according to the law given (1), (2) and (3)

h.b- 1 "|; y-, h,

Considering that .r.

this equation is

.N56-- 2L

U)

where y-f yt For any number η repetitive 1 counter 5 we obtain that N2-i - «- iC | N5-6 i-2 -« - N5V taking into account that formula (7) is valid for any K f x i

Thus, the proposed device allows calculating the value of the square root of frequency, time, or number-impulse signals for any argument value (the range of changes is limited only by the number of counters 6 and 2 and the width of divider 3} without degrading the dynamic characteristics of the device over the entire interval change the argument.

Claims (1)

NUMEROUS-PULSE FUNCTIONAL CONVERTER, comprising a pulse adder, a binary multiplier, and a first counter, the bit output of which is connected to a control input of the binary multiplier, the pulse input of which is connected to the input of the first counter, the output of the binary multiplier is connected to the first input of the pulse adder, the second input of which is connected to the input of the transform (a theory, characterized in that, in order to increase the conversion range without impairing the dynamic characteristics of the converter, a second the first and third counters and a controlled frequency divider, the pulse input of which is connected to the output of the pulse adder, the output overflow of the first counter is connected to the input of the second and third counters, the output of the third counter is connected to the control input of the controlled frequency divider, the output of which is connected to the input of the first counter .