SU1478368A1 - Multifrequency signal receiver - Google Patents

Abstract

The invention relates to radio and can be used in discrete information transmission systems. The purpose of the invention is to improve noise immunity. The device contains an energy spectrum analyzer 1, a switch 2, a drive 5, a logic unit 6, a control unit 10, and r-11 clock pulses. The goal is achieved by introducing a decisive block 3, two compensators 4.9, a data selection block 7, a synchronization error calculating block 8, a control signal generator 12, a switch 13 and a demodulator 14. The compensator 4 is designed to suppress narrowband interference. Unit 7 of all formed estimates of differences chooses the one, the value of which is proportional to the signal delay. According to the calculated value of the synchronization error in block 8, the compensator 9 delays the pulses of Mr. 11 arriving at the compensator 9 through the driver 12, which compensates for the error in the delay. 11 hp f-ly, 12 ill.

Description

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The invention relates to radio and can be used in discrete information transmission systems.

The purpose of the invention is to improve noise immunity.

Fig. 1 shows a structural electrical circuit of the proposed receiver; Fig. 2 is a structural electrical circuit diagram of the energy spectrum analyzer; FIG. 3 is a structural electrical circuit of the control unit; 4 shows the structural electrical circuit of the first compensator; FIG. 3 shows a structural electrical circuit of the second compensator in FIG. 6, a structural electrical circuit of the storage device; Figure 7 is a structural electrical circuit of a logic unit; Fig. 8 shows a structural electrical circuit of the demodulator; Fig. 9 is a structural electrical circuit of a decision block; Fig. 10 is a structural electrical circuit of a data selection block; Fig. 11 illustrates the structural electrical circuit of the driver of the control signal; FIG. 12 is a structural electrical circuit of a synchronization error calculation unit.

The multi-frequency receiver contains analyzer 1 of the energy spectrum, first switch 2, decisive block 3, first compensator 4, accumulator 5, logic block 6, data selection block 7, block 8 for calculating the synchronization error, second compensator 9, block 10 of control, clock generator 11 pulses, a control signal generator 12, a second switch 13, a demodulator 14, and a decoder 15.

The energy spectrum analyzer 1 contains the first 16 and second 17 frequency converters, the first 18 and second 19 band-pass filters, the reference signal generator 20, the first 21 and second 22 analog-to-digital converters, the first 23 and second 24 registers, the weight unit 25, the first the sixth adders 26-31, the third 32 and the fourth 33 register the first - the fourth multipliers 34-37, the first 38 and the second 39 storage units and the first 40 and second 41 quadrants.

The control unit 10 contains the first 42 and second 43 frequency dividers,

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counter 44, switch 45 and register 46.

The first compensator 4 contains the first 47 and second 48 elements And, the first - the fourth registers 49-52, the frequency divider 53 and the adder 54.

The second compensator 9 contains a counter 55, a comparison block 56, an inverter 57, the first is the third element AND 58-60, and the element OR 61.

Drive 5 contains the first - fourth elements AND 62-65, inverter 66, element OR 67, the first - fourth registers 68-71, the first 72 and second 73 adders, the multiplier 74, the permanent storage unit 75, the counter 76 and the frequency divider 77.

Logic block 6 contains the first-fifth registers 78-82, the comparison node 83, the first - the tenth elements AND 84-93, the frequency divider 94, the arithmetic node 95, the inverter 96, the first 97 and the second 98 elements OR, and the counter 99.

Demodulator 14 contains the first to fourth elements of AND 100-103, the first 104f and the second 105 delay blocks, the first 106 and second 107 adders, the first 108 and second 109 full-wave rectifiers and the comparison unit 110.

Solving unit 3 contains the first - fourth elements And 111-114, the first 115 and second 116 elements OR, the first 117 and second 118 inverters, the adder 119 and the node 120 of the delay.

Block 7 data selection contains the register 121, the element OR 122; the first is the third nodes 123-125 of comparison, the first-third inverters are 126-128, the first are the ninth elements of AND 129-137, the first are the sixth adders 138-143, the first is the sixth full-wave rectifiers 144-149 and the counter 150.

The driver 12 of the control signal contains an inverter 151, a register 152, a trigger 153, a first 154 and a second 155 elements I.

The synchronization error calculation block 8 comprises a comparison node 156, an inverter 157, a persistent storage node 158, an AND 159 element, an adder 160, an OR 161 element, a counter 162, the first 163 and the second 164 I.

The receiver works as follows.

An additive mixture of signal, white noise and narrowband is fed to the input of the multi-frequency receiver.

omeh. The spectrum of the signal, which is a digital message transmitted in the form of frequency telegraphy (THT), is extended by pseudo-random frequency hopping (PN), and the frequency of the switching frequency is equal to the transmission rate of the message. The energy spectrum analyzer 1 divides the working frequency range into individual channels according to the number of working frequencies (K) and generates signals proportional to the powers of the additive mixtures of the signal, white noise and interference in each channel. Functionally, it is equivalent to a set of K bandpass filters with quadratic detectors. The central frequencies of the filters vary discretely in accordance with the law of frequency switching in the signal with the speed specified by the clock frequency according to the commands generated in the control unit 10.

Suppose that a signal in the initial time interval, the magnitude of which is determined by the transmission rate of the message, is transmitted at the i-th frequency corresponding to the i-th filter. In the next interval, the signal appears at the (1 + 1) -th frequency, and due to reassignment of the center frequencies (1 + 1) - the frequency again corresponds to the i-th filter, thus the frequency elements of the signal appear at the output of the same 1st filter. Suppose that in one of the channels, for example, in the jth, there is a narrowband interference. Due to the redistribution of center frequencies

the interference is split across the spectrum while the signal at the output of the same 1st filter collapses across the spectrum. Thus, at the output of the analyzer 1 of the energy spectrum, a signal convolution and interference split along the spectrum are formed.

When transmitting information in the form of a frequency band, the working frequency range is divided into pairs of frequency channels for transmitting in each time interval either a single or zero character of the message. Therefore, the reorganization of the filters according to the described algorithm is carried out in pairs.

The first switch 2 will lift the signal from the control unit 10 in pairs and connects the outputs of the energy spectrum analyzer 1 to input 0

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I will give a decision block 3, which is designed to select a single or zero frequency channel in the i-th pair, depending on the transmitted message symbol. Information about the transmitted symbol in the steady state comes from demodulator 14. In the transient mode (before information is extracted), the input of the first compensator receives the sum signal of the i-th channel channels. Thus, in the steady state noise band is narrowed by 2 times. The first compensator 4 is designed to suppress low-noise interference. At its output, differences are formed between the values of the sum signals at the ith and (i + +1) steps of polling the energy spectrum analyzer at each frequency pair, as a result of which narrowband interference is compensated. The cleared signal is fed to the accumulator 5, where the accumulation is carried out with averaging the differences formed by the first compensator 4. Averaging is performed by the recursive algorithm

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where ui + 1 are the differences formed at the output of the first compensator 4 at the (1 + 2) -th polling step of the analyzer of the 1 energy spectrum; average differences at the output of accumulator 5, respectively, in the (i + 1) -m and (1 + 2) -th steps of the survey of the analyzer 1 of the energy spectrum. The number of differences at each polling step is determined by the number of channel pairs (channel pairs). At the exit . The accumulator 5 generates statistical estimates of the magnitudes of the differences. The accuracy of the estimate is directly proportional to the averaging interval.

From the output of accumulator 5, the difference estimate goes to logic block 6, which determines the output numbers of the analyzer 1 of the energy spectrum containing the transmitted message, and data selection block 7, which selects the estimate from the generated difference estimates proportional to the signal delay. This estimate is fed to the input of the synchronization error calculation block 8.

51

Based on the calculated value of the synchronization error, the second compensator 9 delays the pulses of the oscillator 11 clocks arriving at the second compensator 9 through the driver 12 of the control signal, which compensates for the delay error. The delayed clock pulses directly and through the control unit 10 are fed to the energy spectrum analyzer 1 and the first switch 2. The control unit 10 sets the switching order of the first switch 2 and the frequency selection in the energy spectrum analyzer 1. The driver 12 of the control signal is designed to switch the receiver to the accurate synchronization mode when a command is received from logic block 6.

The outputs of the energy spectrum analyzer 1 are also connected to the inputs of the second switch 13, which, by commands from logic unit 6, connects to the inputs of demodulator 14 a group of channels containing the transmitted message. From the output of the demodulator 14, the symbols of the transmitted message arrive at the decoder 15 and the decisive block 3.

Claims (12)

1. Multi-frequency signal receiver containing an energy spectrum analyzer, the outputs of which are connected to the corresponding signal inputs of the first switch, the control input of which is connected to the second outputs of the control unit, a clock generator, a decoder, a drive, the first outputs of which are connected to the first inputs of the logic unit, the first input of the energy spectrum analyzer is the receiver input, the output of which is the decoder output, characterized in that, in order to increase the interference stability, two compensators, a data selection block, a synchronization error calculation block, a second switch, a decision block, a control signal generator and a demodulator, the output of which is connected to the first input of the decision block and the first input of the decoder, the second input of which is connected to the generator output like83686 output pulses and to the third input of the control signal generator, the first and second inputs of which are connected respectively to the third and fourth outputs of the logic unit, the first and second outputs of which are connected respectively to the first and second control inputs 0 of the second switch, the outputs of which are connected to the corresponding signal inputs of the demodulator, the control input of which is connected to the first input of the second compensator and to the control input of the decision unit, the outputs of which are connected to the signal inputs of the first compensator, the control input of which is connected to the third output control unit 0 the first outputs of which are connected to the third inputs of the energy spectrum analyzer, the second input of which is connected to the input of the control unit and to the second output of the second compensator, the first and second inputs of which are connected respectively to the first and second outputs of the synchronization error calculation block, the signal inputs of which are connected to About the outputs of the data selection block, the first and second inputs of which are connected respectively to the fifth and sixth outputs of the logic unit, the second input of which is connected to the second input of the accumulator and c, the third input of the data selection block, the fourth inputs of which are connected to the third output of the storage device, the first and The second inputs of which are connected respectively to the first and second outputs of the first compensator, while the output of the control signal generator is connected to the control input of the first compensator and to the control input of the calculator techniques, are synchronization errors, the energy spectrum analyzer outputs connected to respective signal inputs of the second switch, and the first and second outputs of the first switch are connected correspondingly with the second and third casting block inputs. 2. The receiver according to claim 1, characterized in that the energy spectrum analyzer contains two frequency converters, two band-pass filters, four registers, two analog-digital converters, a block of weighting coefficients, six adders, five 0 five 0 five four multipliers, two storage blocks, two quadrants and a reference signal generator, the first and second outputs of which are connected to the second inputs of the first and second frequency converters, respectively, the outputs of which are connected to the inputs of the first and second bandpass filters, respectively, whose outputs are connected to the first inputs of the first, respectively and second analog-to-digital converters, the outputs of which are connected to the inputs of the first and second registers, respectively, the outputs of which are connected to the first inputs from respectively, the first and second adders, the outputs of which are connected to the first inputs of the third and fourth multipliers, respectively, the outputs of which are connected respectively to the first and second inputs of the third adder, the outputs of which are connected to the inputs of the first storage unit, the outputs of which are connected to the second inputs of the first adder, to the first the inputs of the first multiplier and the inputs of the first quad, the outputs of which are connected to the first inputs of the fourth adder, the second inputs of which are connected to the outputs The second quadrant, the inputs of which are connected to the first inputs of the second multiplier, to the second inputs of the second adder and to the outputs of the second storage unit, whose inputs are connected to the outputs of the fifth adder, the first and second inputs of which are connected to the outputs of the first and second multipliers, the second inputs which are connected to the second inputs of the fourth and third multipliers, respectively, the outputs of the fourth adder are connected to the first inputs of the sixth adder, the outputs of which are connected to the inputs of tert its register, the first outputs of which are connected to the second inputs of the sixth adder, the first and second outputs of the weight factor block are connected to the second inputs of the first and second multipliers, the second outputs of the third register are connected to the inputs of the fourth register, the outputs of which are the analyzer of the energy spectrum, the first the input of which is the combined first inputs of the first and second frequency converters, the second combined inputs of the first and second known-digital converters The drivers are the second input of the energy spectrum analyzer, the third inputs of which are the inputs of the weighting unit. 3. Receiver pop. 1, different from Q o and in that the control unit contains two frequency dividers, a counter, a switch and a register, the parallel outputs of which are connected to the corresponding inputs of the commutator 5, the control input of which is connected to the input of the first splitter. frequency, the output of which is connected to the input of the counter and to the input of the second frequency divider, the output of which under Q keys to the second input of the register, the first inputs of which are connected to the serial outputs of the register, while the input of the first frequency divider is the input of the control unit alenie The 5 first, second, and third outputs of which are, respectively, the switch outputs, the counter outputs, and the output of the first frequency divider. 4. Receiver pop. 1, distinguished by the fact that the drive contains four elements AND, an inverter, an element OR, four registers, two adders, a multiplier, a permanent storage unit, a counter and a frequency divider, the outputs of which The storage unit is connected. with the second inputs of the multiplier, the first inputs of which are connected to the outputs of the first adder, the first inputs of which are connected to the outputs of the first register, the first input of which is connected to the second input of the second register, to the input of the third register and to the input of the fourth register, the parallel outputs of which are connected to the inputs of the first element And, the output of which is connected to the second input of the second element-And to the input of the inverter, the output of which is connected to the second input of the third element And, the outputs of which are connected to the first inputs of the elec OR, whose outputs are connected to the second inputs of the second register, the outputs of which are connected to the second inputs of the fourth 5th AND element and to the second inputs of the second adder, the first inputs of which are connected to the multiplier outputs, the third register output0 five 0 five 0 pen with the input of the frequency divider and with the first input of the fourth element I, the outputs of which are connected to the second inputs of the first adder, the output of the frequency divider is connected to the counter, the outputs of the second sum are connected to the second inputs of the OR element, the second inputs of the first register connected to the outputs of the second element And, the first inputs of which are connected to the first inputs of the third element And and are the inputs of the accumulator, the control input of which is the first input of the first register, the outputs of the second adder are the first outputs The dam of the storage device, the second output of which is the output of the fourth register. 5. The receiver according to claim 1, characterized in that the logic block contains five registers, a comparison node, ten AND elements, a frequency divider, an arithmetic node, an inverter, two OR elements and a counter whose outputs are connected to the second inputs The first element And, the output of which through the first register is connected to the second, the inputs of the second element And, the outputs of which are connected to the inputs of the second register, the parallel outputs of which are connected to the inputs of the third element And, the output of which is connected to the second input of the fourth element-And, the first input The house of the fifth element And with the first input of the sixth element And, the second input of which is connected to the input of the counter and the input of the frequency divider, the output of which is connected to the first input of the second element And and to the control input of the second register, the serial outputs of which are connected to the second inputs of the element And, the outputs of which are connected to the inputs of the arithmetic node, the first outputs of which are connected to the second inputs of the seventh element And and the first inputs of the third register, the second inputs of which are connected to the second outputs of the arithmetic the second inputs of the eighth element AND, and the second inputs of the ninth AND element, the outputs of which are connected to the second inputs of the first OR element, the first inputs of which are connected to the outputs of the tenth And element, the second inputs of which are connected to the third inputs of the third register and the third exits ten 15 20 25 78368Y an arithmetic node, the fourth and fifth outputs of which are connected respectively to the fourth and fifth inputs of the third register, the control input of which is connected to the output of the sixth And element, the outputs of the fourth register are connected to the corresponding inputs of the fifth register and the second inputs of the comparison node, the first inputs which is connected to the first outputs of the fifth register, the second output of which is connected to the first input of the fourth element And, the output of which is connected to the input of the inverter, to the first input of the tenth element And, and to the first the input of the eighth element And, the outputs of which are connected to the first inputs of the second element OR, the second inputs of which are connected to the outputs of the seventh element And, the first input of which is connected to the first input of the ninth And element and to the output of the inverter, the first input of the first element And connected 0 five five 0 five 0 with the output of the comparison node, with the control input of the fifth register and with the control input of the fourth register whose inputs are the first inputs of the logic unit, the second input of which is the counter input, first, second, third, fourth, fifth and sixth outputs the logical unit are respectively the outputs of the second element OR, the outputs of the first element OR, the output of the third element AND, the output of the frequency divider, the output of the fourth element AND, and the outputs of the third register. 6. Receiver pop. 1, characterized in that the demodulator contains four AND elements, two delay units, two adders, two two-wave rectifiers and a comparison unit, the first and second inputs of which are connected to the outputs of the first and second full-wave rectifiers, respectively The inputs of which are connected to the outputs of the first and second adders, respectively, the first inputs of which are connected to the outputs of the first and second delay blocks, respectively, whose inputs are connected to the outputs of the first and second elements, respectively, the first inputs of which are combined and connected to the first inputs of the third and fourth elements And, the outputs of which are connected. yens with the second inputs of the first and second adders, respectively the stroke of the comparison unit is the output of the demodulator, the first, second, third and fourth inputs of which are respectively the second inputs of the first element AND, the second inputs of the second element AND, the second inputs of the third element And and the second inputs of the fourth element AND, the first input of which demodulator control input. 7. The receiver according to claim 1, characterized in that the decision block contains four AND elements, two OR elements, two inverters, an adder and a delay node, the first and second outputs of which are connected to the first inputs of the first and second elements And, the second inputs of which are connected to the outputs of the first and second elements OR, respectively, the first inputs of which are connected to the output of the first inverter, whose input is connected to the second inputs of the third and the fourth And elements, the outputs of which are connected to the second inputs of the second and first OR elements respectively, the first input of the third element AND connected to the input of the second inverter, the output of which is connected to the first input of the fourth And the outputs of the first and second elements of And are connected respectively to the first and second inputs of the adder, the outputs of which are the outputs of the decision block, the first, second and third inputs of which are respectively the input of the second inverter, the second and third inputs of the delay node controlling the inputs of the decision block is the input of the first inverter. 8. Receiver pop. 1, characterized in that the first compensator contains four registers, two AND elements, an adder and a frequency divider, the output of which is connected to the second control input of the first register, the parallel outputs of which are connected to the corresponding inputs of the second register, the outputs of which are connected with the first inputs of the adder, the second inputs of which are connected to the outputs of the first element I, the first inputs of which are connected to the outputs of the third register and to the inputs of the first register, the second control input of which is connected to y control input of the third register, with the control input of the fourth register and 12 five 0 five The input of the frequency divider, the parallel outputs of the fourth register are connected to the inputs of the second And element, the output of which is connected to the second input of the first And element, the serial output of the fourth register is connected to the control input of the second register, the outputs of the adder and the serial output of the fourth register are respectively the first and the second outputs of the first compensator, the frequency divider input is the control input of the first compensator. 9v Receiver pop. 1, which differs from the fact that the second compensator contains three AND elements, an OR element, an inverter, a comparison unit and a counter, the input of which is connected to the output of the first AND element and to the first input of the second And element, output which is connected to the first input of the OR element, the second input of which is connected to the output of the third element And, the first input of which is connected to the first input of the first element And, the second input of which is connected to the input of the inverter, the output of which is connected to the second input of the third element And, the counter outputs connection with the first inputs of the comparison unit, the output of which is connected to the second input of the second element AND, and is the first output of the second compensator, the second output of which is the output of the OR element, the first input of the first element AND, is the control input of the second compensator, the first and second inputs which are respectively the input of the inverter and the second inputs of the comparison unit. 10. The receiver according to any one of the following: the synchronization error computing unit contains three AND elements, an OR element, a comparison node, an inverter, a permanent storage node, an adder and a counter, the outputs of which are connected to the second inputs of the first AND element and adder, the outputs of which are connected to the second inputs of the second element AND, the outputs of which are connected to the second inputs of the OR element, the first inputs of which are connected to the outputs of the first element AND, the first input of which is connected to the output of the inverter, whose input is connected to the input of the second element I. 0 0 five 131 The third input of the third element And with the output of the comparison node, the second inputs of which are connected to the first inputs of the third And element and the outputs of the permanent storage node whose inputs are connected to the outputs of the OR element, while the output of the comparison node is the first output of the synchronization error calculation block The second outputs of which are the outputs of the third AND element, the input of the counter is the control input of the synchronization error calculation unit, whose inputs are the first inputs of the comparison node. 11. Receiver pop.1, about tl and h So that the data selection block contains a register, an OR element, three comparison nodes, three inverters, nine AND elements, six adders, six full-wave rectifiers and a counter, the outputs of which are connected to the second inputs of the first comparison node, the output of which is connected to the control input of the register and the first input of the first element I, the outputs of which are connected to the inputs of the register, the first outputs of which are connected through the first full-wave rectifier to the first inputs of the first adder, the outputs of which are connected to the first the second inputs of the second comparison node, the second inputs of which are connected to the outputs of the second full-wave one rectifier, whose inputs are connected to the first inputs of the second element I, the second inputs of the sixth adder and the fourth outputs of the register, the second outputs of which are connected to the first inputs of the third adder and with the inputs of the third two-half-period rectifier, the outputs of which are connected to the first inputs of the fourth adder, the outputs of which are connected to the second inputs of the third comparison node, the first inputs of which are Connected to the outputs of the fifth adder, the first inputs of which are connected to the outputs of the fourth two-half-period rectifier, whose inputs are connected to the first inputs of the third And element and to the fifth outputs of the register, the third outputs of which are connected to the first inputs of the fourth And element, with the second inputs the third adder and with the first inputs of the sixth adder, the outputs of which are connected to the inputs of the fifth half-14 Q five a period rectifier whose outputs are connected to the second inputs of the fourth and fifth adders, the outputs of the third adder are connected to the inputs of the sixth full-wave rectifier whose outputs are connected to the second inputs of the first and second adders, the output of the second comparison node is connected to the first input of the fifth element And The second input of which is connected to the output of the first inverter, whose input is connected to the second input of the sixth element And whose output is connected to the input of the second inverter and to the first input of the seventh element a And, the second input of which is connected to the second input of the eighth element And and with the output of the third foreign inverter, whose input is connected to the output of the fifth element And and to the second input of the ninth element And, the first input of which is connected to the first input of the eighth element And way out 5 of the second inverter, the output of the third comparison node is connected to the first input of the sixth element AND, the output of the seventh element AND is connected to the second input of the third element AND, the outputs of which are connected to the first inputs of the OR element, the second inputs of which are connected to the outputs of the second element AND, the second input which is connected to the output of the eighth element AND, the output of the ninth element AND is connected to the second input of the fourth element AND, the outputs of which are connected to the third inputs of the OR element, the outputs of which are the outputs of the data selector, the first, second, third and fourth inputs of which are respectively the input of the first inverter, the first inputs of the first comparison node, the counter input and the second inputs of the first element I. 12. The receiver according to p. Distinguished by the fact that the control signal generator contains two elements AND, a trigger, a register and an inverter, the output of which is connected to the second input of the register, the outputs of which are connected to the inputs of the first 5 of the And element, the output of which through a trigger is connected to the first input of the second element And, the output of which is the output of the control signal shaper, the first, second five five 4J FIG. 2 44 : 45 i ft-If If 46 . Fig.Z f f t 59 60 5 b QftfZVt $ / 54 FIG. eleven