SU1027799A1 - Phase discriminator - Google Patents

Abstract

A PHASE DISCRIMINATOR containing a differentiating circuit, the input of which is the information input of the phase discriminator, and the output is connected via a rectifier to the first inputs of two AND elements, the second inputs of which directly and through an inverter are connected to the clock input of the phase discriminator differing from that. that, in order to increase the accuracy and speed of the formation of a corrective action, it introduced two delay lines with taps, two switches and a frequency meter, the control outputs of which are connected to the combined control inputs of the switches, the outputs of which are the outputs of the device, and the switchable inputs switches are connected to the outputs of the delay lines, the inputs of which are connected to the outputs of the corresponding elements And, the first inputs of which are connected to the information input of the frequency meter, clock the output of the latter is connected to the combined clock inputs of the switches, and the clock (L input is connected to the clock input of the phase discriminator.

Description

i / y. / The invention relates to radio engineering and can be used, in particular, in the receiving part of the information transmission system. The known phase discriminator d for a corrective device with discrete control, containing two modulo two adders, a recording unit, two delay lines, logic elements and a pulse counter. The disadvantages of this device are high complexity and the absence of interruptions in the communication channel and structures of received messages, which reduces the speed and accuracy of the formation of corrective action. -. The closest to the present invention is a phase discriminator containing a differentiating circuit, the input of which is the information input of the phase discriminator, and the output of the differentiating circuit is connected via rectifier to the first inputs of two And elements, the outputs of which are phase discriminator, and the inputs of And elements directly and through an inverter connected to the clock input of the phase discriminator 2. This device is designed to analyze the mutual location of clock pulses and elements message and generates correction pulses of addition or subtraction (one for each edge of the message element). However, the known device both bakes a low response rate of the corrective action, since it does not react to the change in the message structure and to the mode of operation of the receiving part of the transmission system that precedes the analysis moment. The use of this phase dis criminator in the acceptance of a synchronization system leads to a decrease in speed. The purpose of the invention is to improve the speed of the formation of the corrective action. The goal is achieved by the fact that a phase discriminator containing a differentiating circuit, whose input is the information input of the device, and the output of the differentiating circuit, via a rectifier, is connected to the first inputs of two And elements, the second inputs of which are directly and via an inverter connected to the clock input of the phase discriminator # introduced two delay lines with taps, two switches and a frequency meter that controls the outputs of which connect. Yen with the combined control inputs of the switches, the outputs of which are the device outputs, the switching inputs of the switches are connected to the outputs of the delay lines whose inputs are connected by the t outputs of the corresponding AND elements, the first inputs of which are connected to the information input of the frequency meter switches, and the clock input is connected to the clock input device. FIG. 1 shows an electrical block diagram of the device of the invention. FIG. 2 - temporary, diagram of his work,. where a - the pulses at the information input device; b - pulses at the output of the differentiating circuit; c - pulses at the output of the miter, g - pulses at the clock input of the device, g - pulses at the output of the inverter, e, f - pulses at the outputs of the second and first elements HV, respectively, - pulses at the outputs of the second b of the delay element, k - pulses on the clock output frequency meter; l, m - pulses at the outputs, respectively, of the second and first switch-. tori. The device contains the first and second elements Hi and 2, the first and second lines 3 and 4 Delays, the first and second switches 5 and b, the differentiating circuit 7, the rectifier 8, the inverter $, the frequency meter 10, consisting of the first and second counters 11 and 12. The clock input of the device is connected to the input of the inverter 9, the second input of element 2 and the clock input of the meter 10, the information input of which is connected to the first inputs of the elements 1 and 2 and the output of the rectifier 8, the input of which is connected to the output of the differential circuit 7 whose input is information nym input device. The first output of the device is the output of the switch 5, the switching inputs of which through line 3 are connected to. the output of the element 1 is the second input of which is connected to the output of the inverter 9, the second output of the device is the output of the switch 6, the switching inputs of which line 4 are connected to the output of the element of the 2nd. meters 10, the clock output of which is connected to the combined clock inputs of the switches 5 and 6. The implementation of the component parts of the device is not difficult.

I Lines 3 and 4 delays - typical delay lines with taps. The number of taps, K, determines the maximum signal multiplication factor that is selected, based on the desired response time, to the frequency step of the clock synchronization device. The maximum signal delay time should not exceed the duration of a single message element.

Switches 5 and 6 can be implemented on the basis of input triggers of memory and AND elements. At the moment a pulse arrives at a clock input of the switch, the code of the number on its control inputs is rewritten into input memory trigger / output voltages of which by means of the elements connect the signals of the switch with a certain number of its switched inputs. The greater the number code at the control inputs of the switch, the smaller the number of its switched inputs is connected to the output.

Frequency meter 10 is designed to determine the average frequency of the pulse following a certain period of time. In the simplest case of FIG. 1) can be implemented by a counter 11, the input of which is the clock input of the meter 10, the clock output of which is the output of the counter 11 and connected to the fault input of the counter 12, the outputs of the bits of which are the control outputs of the meter 10, whose information input is The clock input of the counter 12. The capacitance of the counter 11 and the frequency of its input pulses determine the time interval during which the measurement is made. The capacity of the counter 12 must be sufficient so that during the time between the two pulses, arriving at its fault input, it does not overflow with the pulses, –path and time with the information input of the meter -10. The higher the average frequency of these pulses, the greater is the number of times the number at the outputs of counter 12 at the moment of time preceding its reset.

The device works as follows.

Generated by the clock synchronization device, which includes the proposed phase discriminator, the clock pulses (clock frequencyr) with a frequency close to the speed of wiring (transmission) of the received message elements are sent to the clock input of the device. The second input element And 2 clock pulses come directly (Fig. 2d), and the second input element And 1 through the inverter (Fig. 2e),

preparing them for work- (permitting work for the corresponding half-period).

Received message elements arrive at the information input.

the device (Fig. 2a), the differentiating circuit 7 carries out the separation of their fronts (Fig. 2b), which are rectified (Fig. 2c) by the rectifier 8 / s.

the inputs of the And 1 and 2 elements. If the phase of the clock pulses lags behind the phase of the received message elements (Fig. 2a, d), then a pulse is formed at the output of the And 2 element (Fig. 2e),

if it is ahead, then at the output of the element I 1.

The timing diagram (Fig. 2) is shown for the case of upholding the phase of the clock pulses when using the delay line with four taps (). .

In the case of a lag phase of the clock pulses, the pulse from the output of the element II 2 (Fig. 2e) is fed to the input of the delay line 4, where

its reproduction, i.e. At each of the outputs (taps) of the delay line 4, one (respectively, delayed relative to each other) pulse is generated (FIG. 2i),

which arrive at the switched. switch input 6.

In addition, the 8 edges of the received message elements allocated by the rectifier arrive at the information INPUT of the frequency meter 10 (recorded in the counter 12). At the moment of forming the impulse (Fig. 2k), at the clock output of the frequency meter 10 (when the counter 11 is filled / the number code from the control outputs of the meter 10 (counter 12 readings) is copied to the switch 5 and b, which determine the multiplication factor for this code; corrective impulses. Thereafter, a reset to zero is performed.

state of the counter 12. The more often the single and zero elements in the message or their groups alternate; the more often the phase-in clock pulses are compared with the phase of received message elements, the higher the frequency meter readings 10 and the lower the signal multiplication factors are set by switches 5 and 6. Similarly, in the case of interruptions in the communication channel (when adjusting the frequency and phase of the clock pulses, Formed by the device of clock synchronization, the number code on the

The output of the frequency meter 10 is minimal, and the multiplication factor of the signals is set to the maximum and is reflected in the timing diagram (Fig. 2) where the formation of the pulse

nz clock output meter 10

(1fig, 2k) leads to a total change in the number of add-on correction pulses, generated during each analysis of the ratio of the phases of the clock pulses to the received message elements, from two to four. The device operates in the same way in the case of the phase advance of the clock pulses, however, corrective pulses are generated at the output of the switch 5.

The proposed device provides an increase in the speed of forming a corrective action, due to the automatic

changes in the magnitude of the corrective action (the multiplication factor of the corrective pulses) depending on the type of received feedback, i.e. from the average unchanged over a fairly long intervals of message structure. In the result of this, a more accurate and faster response to a change in the phase mismatch between the clock pulses and the received message elements occurs, i.e. faster synchronization of received message elements. A similar result is achieved when there are interruptions in the communication channel.

Claims (1)

A PHASE DISCRIMINATOR containing a differentiating circuit, the input of which is the information input of the phase discriminator, and the output through the rectifier is connected to the first inputs of two AND elements, the second inputs of which are direct, which, in order to increase the accuracy and speed of corrective action formation, two lines are introduced into it delays with taps, two switches and a frequency meter, the control outputs of which are connected to the combined control inputs of the switches, the outputs of which are the outputs of the device -keeping, and switches the switched inputs connected to outputs of the delay lines, the inputs of which are connected to the outputs of the respective AND gates, the first inputs of which are connected to the data input of frequency meter, a clock output of the latter is connected with the combined clock SU ... 1027799>