SU1020836A1 - Device for histogram determination - Google Patents

Abstract

1. APPARATUS FOR DETERMINING A HISTOGRAM containing a decoder, a counter, a delay line, a comparator, the first input of which is the device input, and the second input of the connector and the information output of the sweep generators, the output of the comparator is connected to the first input of the I element, the second input of which is connected with the information output of the pulse generator, so that, in order to simplify the device, it contains indicator registers and a generator of high-frequency pulses, synchronizing the input of which is combined with By synchronizing the inputs of the sweep generator and the pulse generator and connected to the bus. Starting the device, the information output of the high-frequency pulse generator is connected to the input of the I element, the output of which is connected to the summing input of the counter, the installation input of which is connected to the output of the delay element, which input is combined with the control § the input of the decoder, the first input of the AND element and is connected to the output of the com parator, the bit outputs of the counter through the decoder are connected to the inputs of the corresponding indicators molecular retis ters.

Description

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2. The device according to claim 1, characterized in that the indicator register contains in each bit an RS flip-flop integrating an RC-chain, an indicator and an AND element, whose information input is connected to the output of the integrating RC-chain of its bit, and the output element And the previous bit is connected to a single input-trigger followed

bit, the control inputs of the AND elements and the single input of the first RS trigger are combined and are the corresponding register input, while the zero inputs of the R5 flip-flops are combined and connected to the register bus, and the output R5 of the trigger each time is connected to the indicator and , except for the last bit, to the input of the integrating RS-chain of its bit

   one . The invention relates to a specialist (Zoned computer devices and may find use in processing statistical information. A device for determining a histogram is known, comprising a switch, registers, analog storage elements, a digital-analog device, triggers 1. However, this device does not allow : It does not produce a histogram in natural time and, moreover, is rather complicated. The closest to the one proposed is a device containing a driver, counters (ring and interval), a threshold device, two decoders / element And, a pulse generator and a delay element, the first input of the threshold device is the input of this device, and the second input is connected to the information output of the generator, the output of the threshold device is connected to the first the input of the element And, the second input of which is connected to the information output of the pulse generator G2. The disadvantages of the known device are its use only for analyzing emissions of random processes, the use of a ring counter and a second decoder, which generally makes it difficult to change the number of histogram intervals. In addition, to visualize the histogram, it is necessary to ensure consistency with various indicators. . The purpose of the invention is to simplify and ensure the construction of a histogram with the formation of sampling elements of the process under investigation, represented by a pulse number code. This goal is achieved in that the device for determining the histogram, which contains the decoder, the counter, the delay line, the comparator whose first input is the device input, and the second input is connected to the information output of the sweep generator, the comparator output is connected to the first input of the And element, the second input which is connected to the information output of the pulse generator, introduced indicator registers and a generator of high-frequency pulses whose sync input is combined with the sync inputs of the generator A sweep and pulse generator is connected to the device Start bus, the information output of the high-frequency pulse generator is connected to the third input of the element I, the output of which is connected to the summing input of the counter, the setup input of which is connected to the output of the delay element whose input is combined with the control input of the decoder, The first input of the element is AND and is connected to the output of the comparator. The discharge outputs of the counter are connected via the decoder to the inputs of the corresponding indicator indicator registers. The indicator register contains in each bit an RS-trigger that integrates the RC-chain, an indicator and an AND element, the information input of which is. is connected to the V-axis of the integrating RC-chain and its bit, and the output of the AND the preceding bit is connected to the single input of the RS trigger of the subsequent bit, the control inputs of the AND elements and the single input of the first RS flip-flop are combined and are sorted by the register input, In this case, the zero inputs of the RS-flip-flops are combined and connected to the register register bus, and the output of the NS-flip-flop is connected to the indicator in each bit and, besides the last bit, to the input of the integrating HC-chain of its bit, Ja FIG. 1 shows a diagram of the device; not figs. 2 - diagram of the indicator register. The device contains a number-pulse analog-to-digital converter / consisting of a comparator

1, one input of which is the input of the entire device, and the other connected to the sweep generator 2 of a linearly varying sweep voltage, which reversely produces clock pulses for clocking other generators (the signal at the output of the comparator 1 is equal to O at Ug Up, where Ug and Up-, respectively, the input and sweep voltage, and is equal to j jipH U tzu Upj, generator of 3 high-frequency pulses and (three-input) element I 4, generator of 5 pulses, whose frequency is less than the frequency of the pulses of the generator 3 times. Where m is the number intervals histogram, b counter, decoder 7 (on the m outputs), a delay element 8 and the indicator registers in m n states corresponding to the number of levels of the histogram interval. /

The device works as follows.

After switching on the device and setting counter B and registers 9 into О (installation circuits are not shown), the Start-up signal starts the generator 2 and the 3-t 5 generator is synchronized, i.e.; at the time of synchronization, the pulses at the outputs of the generators 3 and 5 in the vehicle simultaneously. At the output of the element 4, there is a pulse that will change the state of the counter 6 by one, since at the output of the comparator 1 the signal is still O. Over a time interval corresponding to the maximum ordinate of the current element of the sample, each wth generator pulse 3 will coincide with them, the pulses of the gene of ator 5. It should be noted that for reliable operation of the device, the duration of the pulses t of the generator 5 is determined by the condition tt T, where t у, and T are the corresponding duration and period of the pulse of the generator 3. v

At the moment of equality Ug Up, the output of the comparator 1 is on a Vits signal, which locks the element I 4 and unlocks the decoder 7, which will result in the conversion of the code {Counter b to a change in the state of one of the decoder outputs. This change leads to the transition to the next state, L, corresponding to indicator indicator register 9. After the time t, the determined time constant of delay element 8, counter 6 is reset to zero by the signal from the output of delay element 8. At the time of the correspondence Up p Dctx about the Ratny course of the linearly varying voltage of the generator 2, a sync pulse is generated, which again synchronizes the pulse sequences of the generators 3 and 5 and starts the generator 2. The next cycle of the device operation will begin.

After the formation of all the elements of the sample in the indicator registers will be recorded the number of elements of this sample with ordinates corresponding to the intervals r, istogram, i.e. a change in the state of the 1st indicator register can be made only by those sampling elements, the number of pulses N in which corresponds to the condition. For example, when and in the interval of the histogram, only those elements of the sample fall into which the number of pulses corresponds to the condition 77 N 87.

The operation of the indicator register circuit is as follows.

The change in the output state of the decoder 7 is a pulse of duration C, since it is limited by the time of the delay element 8, therefore, either by the front or by the decay of this pulse, the trigger 10 is switched to one state. Since the RC time constant is Cnf. , the capacitor C does not have time to charge during the time f before the voltage level of the logical unit required to open the element And 13. At the moment of arrival of the second pulse to this register at the information input of the element And 13v | there will be a signal and the next trigger will go into one state. A change in the state of the triggers 10 is highlighted by indicators or otherwise, justified for this particular case, by means of.

Thus, each subsequent impulse received on this register will highlight the level corresponding to its number, and the one from the bottom

The operation of the device is carried out in parallel with the formation of the ordinate of the investigated process, which is the number-pulse code. The device is designed for the analysis of samples, in units, expressed by the number of pulses satisfying condition 4, where y is the current value of the element; k is the number of bits of the binary number, expressing the number of pulses, which corresponds to one period of the linearly rising voltage of the generator 2,

The most effective use of the device is to perform it as an additional card to the number of pulsed ADC. However, it should be borne in mind that the number of histogram intervals with decreasing dispersion will decrease. Therefore, in order to use the device more efficiently on the basis of preliminary data, it is necessary to choose the oscillator frequency 5 or / and to limit it from the bottom of the input signal. In addition, if the value of the smallest element of the sample is greater than zero, then there will be some flattening of the histogram, which can be eliminated using the methods described above.

fig 2

The efficiency of the device was tested on a model made on integrated circuits of various series and discrete. Elements. The test results confirm the positive effect of the device.

The device provides a histogram in real time.

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Claims (1)

1. DEVICE FOR DETERMINING A HISTOGRAM, containing a decoder, counter, delay line, a comparator, the first input of which is the input of the device, and the second input is connected to the information output of the scan generators, the output of the comparator is connected to the first input of the element And, the second input of which is connected with the information output of the pulse generator, which is why, in order to simplify the device, it contains indicator registers and a high-frequency pulse generator, the synchronizing input of which is combined with the clock using the input inputs of the sweep generator and the pulse generator and is connected to the device's Start bus, the information output of the high-frequency pulse generator is connected to the input of the And element, the output of which is connected to the summing input of the counter, the installation input of which is connected to the output of the delay element, whose input is combined with the control input of the decoder, the first input! element And and is connected to the output of the comparator, the bit outputs of the counter through a decoder are connected to the inputs of the corresponding indicator registers. a SU ”1020836> - 2. The device according to π. 1, characterized in that the indicator register. Contains in each category an RS trigger that integrates the RC chain, an indicator and an I element, the information input of which is connected to the output of the integrating RC chain of its discharge, and the output of the And element of the previous discharge is connected to a single input RS-flip-flops of the subsequent discharge, control inputs of elements · And and a single input of the first RS-flip-flop are combined and are the corresponding input of the register, while the zero inputs of the RS-flip-flops are combined and connected to the installation bus of the register, and the output is RS-t iggera in each stage is connected to the indicator and, except for the last digit, to the entrance of the integrating RS-chain his discharge. 12