SU1559398A1 - Time-pulse comparator - Google Patents

Abstract

The invention relates to a pulse technique and can be used in instrumentation systems. The purpose of the invention is to increase the reliability of the results. To do this, a comparator containing a pulse former 1, a clock generator 3, synchronization blocks 4.5, elements AND 6-8, element OR 9, trigger 10, a counter 11 pulses, digital comparators 12.13, a shift register 15, a digital comparator is entered 14 and new functional relationships. The duration of each input pulse with the help of a pulse counter 11 and a digital comparator 14 is compared with a predetermined threshold. The result of the comparison is entered in the shift register 15. The results of the latest comparisons form in the shift register 15 an N-bit number, the high bits of which correspond to the later results. This number is compared with predetermined thresholds using digital comparators 12,13. 1 il.

Description

The invention relates to a pulse technique and can be used as part of noise-resistant automatic control systems and instrumentation systems. '

The purpose of the invention is to increase the reliability of the comparison results.

The drawing shows a structural diagram of the device.

The time-pulse comparator contains a pulse shaper 1, an input bus 2, a clock 3, the first and second synchronization blocks 4 and 5, the first, second and third elements 6-8, the OR element 9, trigger 10, the pulse counter 11, the first, second and third digital comparators 12-14, shift register 15, first and second output buses 16 and 17.

The first and second outputs of the pulse shaper 1 are connected to the information inputs of the first and second blocks 4 and 5, connected by clock inputs to the first and second outputs of the clock generator 3. The output of the first block 4 is connected to the first input of trigger 10 (unit input to unit) connected directly output to the first inputs of the first and second elements And 6 and 7, The second input of the first element And 6 is connected to the first output of the clock generator 3, and the output to the counting input of the counter

11. The second input of the second AND element 7 is connected to the output of the second block 5, and the output is connected to the first input of the OR element 9, connected by the second input to the output of the third AND element 8, and the output to the second input of trigger 10 (zero input), to the zero input of the counter 11 and to the clock input of the shift register 15. The first input of the third element And 8 is connected to the second output of the clock generator 3, and the second input is combined with the information input of the shift register 15, connected by the outputs to the inputs of the first and second digital comparators 12 and 13 and with connected to the output of the third digital comparator 14, connected by inputs to the outputs of the counter 11. The outputs of the first and second digital comparators 12 and 13 are connected to the first and second output buses 16 and T7. The pulse shaper 1 generates short pulses at the first and second outputs - along the front and along. section of each input pulse, respectively.

The clock generator 3 generates at the outputs short pulses of a high stable frequency F with a period T, and the pulses at its various outputs are shifted by the time T / 2.

The first and second synchronization blocks 4 and 5 are the same; the pulse received at the information input of the block is stored in it and extends to the output of the block synchronously with the next pulse from the second output of the clock generator.

The first, second, and third digital comparators 12-14 support a single output signal when conditions are met

S> S *. (1)

S S *, (2)

N = N _o , (3) where N and S are the contents of the counter 11 · pulses and register 15, respectively; S *, S *, N _o - numbers that are set before starting the device on the second inputs of the comparators 12-14,

The comparator operates as follows.

Are input direct? · Angular pulses with a duration, on which random interference is superimposed. The duration of each input pulse is compared (in digital form) with a reference duration of £ ₀ , namely, the condition 'with _x C _{o is} checked. (4)

The result of the comparison r (r = 1 if condition (4) is satisfied and r = 0 otherwise) is fed to the information input of the shift register 15, the contents of which are shifted by one digit to the right (towards the lower digits) after each comparison _? Niya. Thus, in the shift register 15 a moving sample of the results η of the latest comparisons is formed. The contents of the register are interpreted as an η-bit binary number, the i-ro value of which is the result of the i-ro comparison, i.e., the result r _{h of the} last comparison is given weight 2 to the result of the previous, η-l-th comparison - weight 2 ^{n 4} etc., the result of the oldest comparison taken into account is weight 1

(5) (g 'is the result of an i-ro comparison).

Thus, the device carries out exponential weighting of the sliding sample, composed of the results of η recent comparisons (checks of condition (4)).

Based on the obtained value of S, the device generates output

Cx, with for buses 16, 17, logical signals C *

L.

⁰ X / K ⁶ X

L.

as follows

l

<s _o _ l l °>%

The device operates as follows:

C _f = O s ₍ = O

C, = 1 rule:

C, = 11 s, = o V with ₂ = o] (6) at a time.

Before starting work on the second inputs of the digital comparators 12-14 set, respectively, the numbers S *, S *, N ₀ = F · D _o ? 0 ,.

In the initial state of the device, the trigger 10 and the counter 11 are set to zero, while the clock pulses do not pass through the elements And 6 and 8,

At the moment of receipt of the pulse on the input bus 2, the driver 1 generates a short pulse at its first output, which arrives at the information input of the first block 4, and then at the first input of the trigger 10, setting it to a single state.

As a result, the elements And 6 and 7 are opened at the second inputs and the clock pulses from the first output of the clock generator 3 begin to fill the counter 11.

After a time with _x - at the end of the input pulse of the device - a short pulse is formed at the second output of the former 1. We denote by N * the number of clock pulses transmitted through the element And 6 'over time (obviously, N _x = F ·).

If y ί 'ί'θ, that is, N _x with N _o , then the pulse from the second output of the driver 1 arrives - simultaneously with the pulse from the second output of the clock generator 3 - to the output of the second block 5, This pulse passes through the open now element AND 7 and element OR 9 and shifts the contents of register 15 by one bit to the right, writing to its senior digit (left) zero - the signal present at that time at the output of the third digital comparator 14, connected to the information input of register 15, and representing the result velo checks - $ .viya (4). In addition, the pulse from the output of the OR element 9 returns the trigger 10 and the pulse counter 11 to the zero state, thereby closing the sleep of ~ 10 VA elements And 6-8.

If £ _x > £ ₀ , i.e., Ny> M _o , then when equality (3) is reached, a single signal arises at the output of the third digital comparator 14, and the next pulse from the second output of the clock 3 passes through the second the input element And 8 and through the element OR 9, performing the same functions as in the previous case, with the difference that now in the left bit of the shift register 15 one will be written (signal from the output of the comparator 14, i.e., the result comparisons (4).

When O _x y 'sd, the pulse generated at the second output of the pulse former 1 at the moment of the end of Su will not pass through the And 7 element, since by that time the trigger 10 will already be set to zero by the pulse from the output of the And 8 element. At = C _o clock pulses on. the inputs of the OR element 9 will arrive simultaneously (with Ν * = Ν _0, the AND element 8 is open at the second input). Thus, in any case, each comparison of the values of C _x and% gives rise to a single pulse at the output of the OR element 9, which returns the device to its original state, and each time the contents of register 15 are shifted one bit to the right, and the result of the last condition check is recorded in its left bit (4).

After η checks in register 15, all digits will be filled: the left one is the result of the last check, the next one is the previous one, etc. Digital comparators 12 and 13 are connected by high-order bits to the left bit of register 50 of register 15, i.e., their contents are perceived by them as a binary number defined by formula (5).

The signals C c and C ₂ at the outputs of the comparators 12 and 13 encode in this case, 55 according to rule (6), the generated solution.

Each subsequent check of condition (4) leads to a shift of the contents of the shift register 15 by one time in 1559398 row to the right and fixing the result of the check in its left category. Moreover, due to a shift towards the lower digits, the weight of each of η-l of the previous test results is halved, and the oldest of them is forgotten (the contents of the rightmost digit of the shift register 15 are lost). The highest weight is always the result of the last check, in full accordance with formula (5).

From the moment the device is turned on and until the first informed decision is made, η checks must be carried out.

The use of exponential smoothing allows you to increase the reliability of decisions made when the value changes over time, since the last samples are taken into account with more weight than earlier ones.

Claims (1)

Claim A time-pulse comparator containing a pulse shaper, the input of which is connected to the input bus, the first, second and third AND elements, the OR element, the trigger, the pulse counter, the first and second digital comparators, the outputs of which are connected to the first and second output buses, respectively, the shift register, the first and second synchronization blocks, the information inputs of which are connected respectively to the first and second outputs of the pulse shaper, and the clock inputs are connected to the corresponding outputs of the clock 5 of the generator, the output of the first synchronization block connected to the first input of the trigger connected by the output to the first inputs of the first and second to 10th AND elements, the second inputs of which are connected respectively to the first output of the clock generator and the output of the second synchronization block, the output of the second element And connect to the first input of the OR element, the output of which is connected to the second input of the trigger, different from the fact that, in order to increase the reliability of the 2Q comparison results, a third digital comparator is introduced into it, the inputs to which are bitwise connected to the outputs of the pulse counter, the counting input of which is connected to the output of the first element And, and 25 the input of the installation in O with the clock input of the shift register and is connected to the output of the OR element, the second input of which is connected to the output of the third element And, the first input of which is 30 to the second output of the clock generator, and the second input to the output of the third digital comparator and with the information input of the shift register, the outputs of which are connected bitwise to the inputs of the first and second digital comparators.