SK284547B6 - Method and device for measuring the rate of flow of a flowing fluid - Google Patents

Abstract

A method of measuring the rate of flow of a fluid from two ultrasonic signals consecutively transmitted in mutually opposite directions between two transducers. This method consists in: forming n clock signals CKi, i = 1 to n, mutually dephased by 2 pi /n; locating and memorising the first clock signal, called CLS, that is produced immediately after the occurrence of a characteristic part of the first ultrasonic signal received SIG1; determining the time t1 corresponding to the sum over a whole number m of consecutive periods of each of the time lapses between the occurrence of the characteristic part of each of the m periods and the occurrence of the CLS signal which follows, similarly, for the signal received from the opposite direction SIG2 determining the time t2 corresponding to the sum over m consecutive periods of each of the time lapses between the occurrence of the characteristic part of each period and the occurrence of the CLS signal which follows; forming the difference t2-t1 and deducing therefrom the fluid floe rate Q which is proportional to t2-t1.

Description

Technical field

BACKGROUND OF THE INVENTION The present invention relates to a method for measuring the flow of a flowing fluid, comprising successively transmitting two ultrasonic signals between two ultrasonic transducers (sensors, transducers) spaced apart from one another in the direction of fluid flow. in opposite directions to each other, each transducer receiving a corresponding one of these ultrasonic signals. The invention also relates to an apparatus for measuring the flow of a flowing fluid.

BACKGROUND OF THE INVENTION

For many years, the flow rate of a fluid such as warm water flowing in a pipeline has been measured in such a way that the propagation time of the respective ultrasonic signals transmitted in opposite directions to each other downstream and upstream between two ultrasonic transducers located at two points lying spaced from one another in the direction of fluid flow.

In the field of hot water flow measurement, a method is known according to WO 86/02722 comprising simultaneously transmitting an ultrasonic signal from each transducer to a second transducer, the two signals thus propagating in mutually opposite directions. With respect to the flow, the propagation time 12 of the signal transmitted in the direction opposite to the flow direction is higher than the propagation time T1 of the signal transmitted in the flow direction.

The measurement of the two propagation times T1, T2 makes it possible to derive from these times the flow rate of hot water according to the formula Q = K (T2 - T1) / C, where K is a coefficient taking into account computer geometry and C is a correction coefficient. However, this method has a considerable disadvantage. Indeed, when one of the converters has been energized, it continues to transmit a signal while receiving a signal from the other converter. As the water temperature changes, instability (drifts) and additional parasitic phase shifts were observed in the received ultrasonic signals. In order to overcome this problem, it is necessary to perform a temperature measurement and to correct the flow measurement according to temperature variations, which complicates the measurement method.

In addition, other methods of measurement, such as those described in EP 0 426 309, are known in which acoustic signals are sent successively in the flowing fluid in opposite directions. The propagation time of each of these signals is measured by detecting, at each of the received acoustic signals, the moment corresponding to the phase change with respect to the time reference signal that is coupled to the respective broadcast signal. The detection of this moment is done by a phase detector, but this detection is not accurate.

For each of the acoustic signals, this measurement will be associated with a measurement of the acoustic phase shift induced in the acoustic signal under consideration due to the propagation of this signal in the current. The acoustic phase shift measurement is performed by sampling the received signal in eight capacitors by digitizing the sampled signal and performing synchronized detection of the digitized signal.

However, this measurement method introduces additional noise into the sampled values of the signal, and thus into the measurement itself, as a result of sampling. In addition, this method is complicated since it requires measuring the propagation time and measuring the acoustic phase shift for each signal transmission in a given propagation direction.

As a result, it is important to find a measurement method that does not introduce additional noise into the measurement and that can be performed more easily than in the prior art.

SUMMARY OF THE INVENTION

The present invention provides a method for measuring the flow rate of a flowing fluid in which two ultrasonic transducers spaced apart from one another in a fluid flow direction are successively emitted by two ultrasonic signals that propagate in opposite directions, each transducer receiving one respective ultrasonic signal. SIGj, SIG ₂ , which consists in producing n clock signals CK _{f and} where i = 1 to nan> 4, containing transitions, phase shifted by 2π / η, in a fixed phase relation with respect to the driving signal of converters and the same a frequency such as this signal, selecting a characteristic portion of the period of the first received SIGi signal in one propagation direction, selecting a first clock signal transition that occurs immediately after said characteristic portion appears, this CLS clock signal is stored in memory (memorized), no and those corresponding to the sum of the periods in m consecutive periods, elapsed in m periods between the time when the characteristic portion of the SIG _b signal period and the first subsequent clock signal CLS transition, where m is an integer, the same characteristic portion is identified in m consecutive periods of the second SG ₂ signal received in the opposite propagation direction, the time t ₂ corresponding to the sum of times in m consecutive periods elapsed between the time at which the characteristic portion of the SIG ₂ signal period appears and the moment at which the first subsequent transition of the CLS signal occurs , the difference | t ₂ -ti | is created and a flow rate Q of a fluid that is proportional to t ₂ - ie.

Generating n intermediate CK clock signals _; it is possible to provide a time reference signal that is " variable " as opposed to reference signals used in known methods of ultrasonic measurement of the flow rate of the flowing fluid, since once the desired time measurement resolution is obtained, another more appropriate time reference signal is sought. Since this reference signal is based on clock signals, no noise is introduced, as is the case with the prior art methods. In addition, the method is simple since neither the sampling nor the synchronous detection step takes place and can thus be used with simple analog means, as opposed to the prior art methods. In addition, an electronic circuit without an analog-to-digital converter can be easily integrated into an application-specific integrated circuit (ASIC).

The use of this "variable" time reference makes it possible to achieve the desired resolution with greater accuracy and faster. Indeed, with the n signals CK, shifted by 2π / η, the resolution will be T / n (T is the resolution obtained using a clock signal on the basis of which n signals can be generated) and thus it will be possible to measure the time elapsed between when a characteristic portion of each change of the periods of said signal and the first pass of the selected clock signal has appeared, with better resolution than in the prior art.

SK 284547 Β6

Since the resolution capability increases as the number of measurements increases (by the relation 1 / N, where N is the number of measurements), it is obvious that the introduction of that "variable" time reference makes it possible to directly increase the resolution, so fewer measurements are required to achieve the required resolution.

Advantageously, this method makes it possible to reduce the energy consumption to obtain an ultrasonic measurement of fluid flow with the same resolution as in the prior art methods.

Furthermore, it should be noted that when sound frequencies of about 1 MHz are used, for example for fluids such as water, the prior art methods (such as described in EP 0 426 309) are very energy intensive due to the the need for an analog-to-digital converter which is capable of sampling a 1 MHz frequency signal and the method is thus very expensive, as opposed to the solution of the invention.

The integer number of m periods can be equal to 1 or have other values. When the number m is different from 1, the period in which the characteristic portion is selected may correspond to or precede the first of m consecutive periods.

The received signals SIG 1 and SIG ₂ according to the invention can be processed in the form of rectangular pulses and in this case the characteristic part of the periods of the received signals corresponds to the upward or downward face of each rectangular pulse.

According to the invention, the clock signals may be in the form of rectangular pulses, and in this case the first pass of the selected clock signal is an ascending or descending face.

In the method according to the invention, corresponding differences SIG 1 - CLS and SIG ₂ - CLS are generated between the signals in order to obtain the corresponding signals IEX 1 and IEX ₂ , which allow to determine the corresponding times ie at ₂ . The signals IEXj and IEX ₂ may be in the form of rectangular pulses, and the method of the invention consists in expanding the cumulative duration of all rectangular pulses to determine the corresponding times, ie at ₂ .

For example, the clock signal CK _{t is} in phase with the drive driver signal. According to the first embodiment, four clock signals are generated. According to the second embodiment, eight clock signals are generated. Preferably, based on each received signal, a phase shifted SIGS signal is generated relative to the clock signals, in order to avoid the presently mentioned signals. For example, the SIGS signal is phase shifted by π / η.

The invention further relates to a fluid flow measuring device comprising at least two ultrasonic transducers spaced apart from one another in the direction of fluid flow, means for generating an excitation signal of these transducers, means for receiving two ultrasonic signals SIG 1 and SIG ₂ transmitted correspondingly from said. converters in opposite directions and sequentially, the principle being that the device further comprises means for generating n clock signals CK "where i = 1 to nan> 4, which contain transitions, are phase shifted by 2π / η between them are in a fixed phase relationship with respect to the excitation signal and have the same frequency as that signal, furthermore, the identification means of a characteristic part of one period of the first received signal SIG _b selecting means of the first clock clock CK passage that occurs immediately after it said characteristic portion, means for storing the clock signal as a signal

CLS, means for determining the time t] corresponding to the sum in m consecutive periods of the signal SIG _b the last between the time when it appears a characteristic part of each change of signal periods SIGj and the moment when appears the first following transition of signal CLS, wherein m is an integer, means for identifying the same characteristic part in m consecutive periods of the second received signal SIG ₂ , means for determining the time t ₂ corresponding to the sum of the individual sub-periods in the individual periods elapsed between the time at which the characteristic part of the signal period SIG ₂ and which shows the first subsequent passage of the CLS signal and means for generating a difference | t ₂ - ie and deriving a flow rate Q of the fluid which is proportional to t ₂ - t _v

The device can be implemented with simple analog means, such as mainly D or RS flip-flops, thus allowing no analog-to-digital converter or multiple capacitors to store different sampled values.

Means for generating CK clock signals; they may include a crystal-controlled oscillator, followed by n / 2 D-type flip-flops, forming a divider, thereby enabling CK signals to be phase-shifted by 2π / η between them.

The first clock signal selection means may comprise n type D flip-flops, called selectors, each input D of which is connected to a received common SIGi or SIG ₂ signal, each clock input CK receiving a different clock CK signal, different from one flip-flop to the other, and which can be activated by one RAZ input such that when the RAZ input of the flip-flops is 1 and the common signal is 1, said flip-flops are sensitive to CK signals.

The first clock signal selection means may also comprise n logic gates receiving each at one input a common received signal SIGi or SIG ₂ and monostable circuits receiving each different input of the clock signal CK; and whose output is transmitted each to one from other inputs n logic gates.

The means for storing the CLS clock signal may comprise both n-type D flip-flops, called memory, receiving each as clock input CK an output signal from the output of the select flip-flop, and a NAND logic with n inputs connected to each Q output of each memory flip the input D of these memory flip-flops is permanently at 1 and the first signal received at the clock input CK of one of the flip-flops activates the memory function of the flip-flop by flipping the output Q of that flip-flop to 1 and output Q to 0 to activate the blocking circuit of the received common signal SIG _b SIG ₂ .

In a device according to the invention, n logical NANDs receive on each of their inputs a clock signal CK; and an output signal from the output Q of the corresponding memory flip-flop, the output of each of the logic members being coupled to one of the inputs of the NAND logic member with n inputs, one of the n logic members releasing the associated clock signal CK when the memory function of the corresponding flip-flop is activated.

BRIEF DESCRIPTION OF THE DRAWINGS

BRIEF DESCRIPTION OF THE DRAWINGS The invention is explained in more detail in the following description by way of non-limiting examples, with reference to the accompanying drawings, in which: FIG. 1 shows an arrangement of ultrasonic transducers with respect to a fluid flow according to an embodiment of the invention, FIG. 2 shows another arrangement of ultrasonic transducers with respect to fluid flow, FIG. 3 is a simplified schematic view of a sequential unit used in the apparatus of the invention; FIG. Fig. 4 is a schematic view of one part of the device according to the invention comprising ultrasonic signal transmitting blocks, a converter switching block and a received ultrasonic signal processing block; 5 SIGj signal (SIG ₂₎ formed on the basis of the received ultrasonic signal, FIG. 5b shows the phase of transmitting and receiving ultrasonic signals, FIG. Fig. 6 is a schematic view of a portion of a device according to the invention comprising a clock block CK, (i = 1 to 4), as well as blocks for selecting and storing a clock signal CLS; 7 shows the course of four clock signals CKi in relation to each other, FIG. 8a shows a variant of part of the apparatus of FIG. 6, which selects the CLS clock signal; FIG. 8b shows an alternative part of the device of FIG. 6, which selects and stores the CLS clock signal; FIG. 8c shows the course of the main signals used as a function of time, FIG. Fig. 9 is a schematic view of part of a device according to the invention comprising a simplified block for generating IEX and IEX ₂ signals (SIG ₁ -CLS and SIG ₂ -CLS); 10 is a diagram showing the step of generating IEX signals! aIEX ₂ , FIG. 11 shows the sequence of the signals SIG _b CLS and IEX _b fig. 12a is a schematic view showing the principle of time expansion; FIG. 12b is a simplified diagram of a time expander; FIG. 13 is a schematic diagram of a portion of a device according to the invention comprising a time expander, FIG. 14 shows the course of the various signals SIG _b SIG ₂ , IEX] and IEX ₂ , FIG. 15 is a diagram of part of the apparatus shown in FIG. 6 according to a second embodiment of the invention, FIG. 16 shows the course of eight clock signals CK in relation to each other, and FIG. 17 waveforms CK _b CK ₃ , C4M, SIG _b SIG1S and IEX ,.

DETAILED DESCRIPTION OF THE INVENTION

A device for measuring the flow of a fluid such as hot water is shown in FIG. 1, 2, 4, 7 and 11 and is generally referred to as device 10. As shown in FIG. 1, the device according to the invention comprises two ultrasonic transducers (sensors, sensors) T _b T ₂ , arranged in a flow and spaced apart from one another in the direction of the fluid flow, so that they can read the fluid velocity information. In FIG. 1, the transducers T _b T _{2 are} located opposite each other at opposite ends of the measuring tube 12 in which the fluid flows in the direction of the arrow F.

Another example of an arrangement of transducers T _b T ₂ is shown in FIG. 2, wherein the transducers are housed in the foot of the storage pockets 14 and 16, perpendicular to the direction of fluid flow indicated by the arrow F. The fluid flows in a measuring tube 18 housing two mirrors 20 and 22 intended to reflect ultrasonic signals as indicated. FIG. 2. The ultrasonic transducers T _b T ₂ are driven by an excitation signal that passes from a sequential unit (controller) 24, shown in simplified form in FIG. 3. The sequential unit comprises a 16-bit computer 26, a decoder 28 connected to the computer, and a block 30 made up of multiple logic elements (gates).

The computer 26 and the block 30 are powered by a 1 MHz clock signal CK ₂ originating from a 4 MHz clock signal, which block also receives the TE signal originating from the decoder 28 and allowing the transmission of an ultrasonic signal. Block 30 outputs an excitation signal SE, which has the role of a pilot signal. The computer 26 is activated when a RAZ signal is emitted by a standby clock (not shown).

As shown in FIG. 4, a SE signal, designated as a SE ₂ signal (intended to drive the T ₂ converter), is transmitted to two respective inputs of two NANDs 32 and 34 mounted in parallel to reduce the internal impedance of this circuit. The second input of each NAND logic is connected to a L-value logic. These logic circuits can be replaced by inverters. The output of the two logic gates 32 and 34 is connected to the capacitor C _p connected in series with resistor R, the resistor _R2 is connected to the resistor _R2 which is connected to the two terminals of the transmitter T _b terminal of the converter T _b which is connected to the resistor R ₂ and R ₂ is also connected to a resistor R ₃ to which a current coming from the collector of the switching transistor 36 is supplied.

PNP transistor 36 is supplied to its emitter voltage V _dd. Serial mounting of resistors R ₂ and R ₃ makes it possible to obtain a stable voltage for the polarization of converters equal to V _dd / 2. Capacitor C, isolates the voltage V _dd from the input (on the SE signal side) in order to cancel the potential of the splitter circuit with resistors R ₂ and R ₃ when mainly the SE signal is at a quiet level. This also makes it possible to avoid excessive consumption.

The resistor Rj isolates the transducer T from the input signal to ensure that the rectangular pulse SE ₂ signal is compatible with the high capacitance transducer and allows better control of the emission impedance.

The transmitter _T2 is formed symmetrical wiring, the signal SW _2, the NAND logic elements 38 and 40, resistors R 4, R ₅ and R _fc capacitor _C2 and a transistor 42nd

Since the two symmetrical wiring branches are not connected to each other, a good isolation between the two transistors is thus ensured.

When transistor T | it sends an ultrasonic signal based on the excitation signal at a frequency equal to 1 MHz, the switch 44 of the switching block is open and the switch 46 connected to the converter T ₂ is closed. The ultrasonic transmission signal E shown in FIG. 5, has a duration of, for example, equal to 40 ps. Approximately 80 ms after the start of the broadcast signal, an ultrasonic signal is received by the converter T ₂ (Fig. 5b). The received signal, indicated by the signal R in FIG. 5a and 5b, is processed by an inverter 48 (FIG. 4), for example an HCO4 type CMOS inverter comprising three cascaded inverters that output an SIG signal in the form of a rectangular pulse shown in FIG. 5 a.

Alternatively, the processing may be performed using a differential comparator whose one input receives a signal output from the switching block and the other input receives a reference signal output from a specialized divider or from an RC network defining the mean value of the signal.

As shown in FIG. 6, the device 10 comprises means 50 for generating four clock signals CKj, where i = 1 to 4. These means comprise a 4 MHz crystal controlled oscillator 52. This oscillator emits a clock signal applied to the clock inputs CK of the two D-type flip-flops 54, 56 that form the divider. The waveform of the 4 MHz clock signal is shown in FIG. 7th

The flip-flop output 56 is connected to the flip-flop input 54 and the flip-flop output 54 is connected to the flip flop input 56. As shown in FIG. 7, as the 4 MHz uplink of the signal comes up, the clock signal CK, outputted by the output Q of flip-flop 54 passes to 1 and the input D of flip-flop 56 also has a value of 1.

Thus, the clock signal CK ₃ output of flip-flop 54 goes to 0. At the next ascending face of the 4 MHz clock signal, the clock signal CK ₂ output of flip-flop 56 goes to 1. Clock signal CK4 output from output Q thus, the flip-flop 56 goes to 0, and the flip-flop 54 input also has a value of 0. At the next ascending clock face of the 4 MHz clock signal, the CK clock decreases again to 0, while the CK ₃ signal goes to 1 and at the inlet D of the flip-flop 56 also goes to 0.

When the following ascending face arrives the edge of the 4 MHz clock signal, the clock signal CK ₂ emitted by the output Q of flip-flop 56 goes to 0 and the signal CK4 thus goes to 1, leading to the signal at input D of flip-flop 54 to 1. . In the course of the head ascending clock of 4 MHz clock signal CK goes to 1, _2, the clock signal CK ₃ thus goes to 0, and the D input of flip-flop 56 goes to 1.

The following ascending face of the 4 MHz clock signal causes the clock signal CK ₂ to pass to 1, and thus the clock signal CK4 and the input D of flip-flop 54 to 0. In FIG. 7th

This creates four clock signals CK _b CK ₂ , CK ₃ and CK1 shown in FIG. These signals have the same frequency as the excitation signals SE, and SE of ₂ converters (1 MHz), which are based on the clock signal CK. The signals are phase shifted by π / 2 to each other and are in a fixed phase relationship with respect to the energizing signals of the converters. In addition, these signals have transitions between logic 0 and logic 1.

An alternative to circuit 50 is to produce a 1K clock signal CK based on a 2 MHz clock signal generated by an oscillator and through a D-type flip-flop. The CK ₂ signal is therefore generated based on the CK signal when creating an artificial the delays, for example, through a monostable circuit (or delay circuit) and the CK ₃ and CK4 signals are readily obtained based on the CK, and CK ₂ signals by inverting them.

As shown in FIG. 3, an ERS synchronization signal is generated by the decoder 28 of the sequential unit 26, its course being shown in FIG. 5 and 5a. Its logic value is 0 and after a time period of 95 ms its value passes to 1 when the received signal is in its middle part, which is less disturbed than the beginning or end of the received signal. This signal triggers the start of the phase in which the clock signal CK is selected.

As shown in FIG. 6, the ERS signal is transmitted to the D input of the D-type flip-flop 58. This flip-flop allows to output at its output Q an ERSS signal corresponding to an ERS signal synchronized to the clock signal CK, which is transmitted to the clock input CK of the flip-flop 58. CK, was chosen arbitrarily.

An ERE signal is generated by the decoder 28 of the sequential unit 26 (FIG. 3) and its course is shown in FIG. 5b. Its logic value is 0 and 2 ms after the ERS signal goes to 1, its value goes to 1. This signal triggers the start of the measurement phase.

As shown in FIG. 6, the ERE signal is transmitted to the D input of the D-type flip-flop 60 whose reset input C (clear) to reset to zero is connected to the R signal, which reinitializes it at the start of the measurement. The output Q of flip-flop 60 is connected to one of the inputs of NOR logic member 62, the other input of which receives an ERSS signal. The output of this logic member 62 is connected to an inverter 64, the output of which is connected to one of the inputs of a NOR logic member 66, the other input of which receives a 4 MHz clock signal. At the output of this logic member 66, a C4M frequency signal equal to 4 MHz is output. The C4M signal is re-injected at the clock input CK of flip-flop 60. The C4M signal is triggered by transitioning the ERSS signal to zero and is blocked when an ERE signal synchronized with the same C4M signal occurs. It should be noted that this logic connection limits the presence of the C4M signal mainly at the CK inputs of flip-flops 60 and 70, minimizing circuit consumption (Fig. 8c).

The output Q of flip-flop 60 provides an ERES signal corresponding to the ERE signal synchronized with the C4M signal, the course of which is shown in FIG. 8c. This signal serves to activate the measuring block, which will be described later. The synchronized ERSS signal is sent to reset input C (clear) to type D flip-flop 68. The SIG signal (S1G1 or SIG2) is transmitted to clock input C of that flip-flop whose input D is 1 .

The flip-flop 68 output Q is connected to the D-type flip-flop 70 input D. The C4M signal is sent to the clock input C of that flip-flop 70 and the reset input C (clear to zero) is connected to the RG signal of the function is to initialize this flip-flop at the beginning of a complete measurement cycle, which is formed by transmitting an ultrasonic signal in the direction of fluid flow, called "downstream transmission" and transmitting a signal in the opposite direction, referred to as "countercurrent transmission."

When the ERSS signal at the output Q of flip-flop 58 goes to 1, the first ascending face of the adjusted signal SIGi (or SIG ₂ ) allows the signal at the output Q of flip-flop 68 to pass to 1, thereby enabling the output signal at the output Q of flip-flop 70. to 1 at the first ascending C4M signal front. The SIG1S signal thus generated corresponds to a SIGi signal synchronized with the C4M signal.

In order to obtain a phase shifted signal SIG1S relative to the signal SIG _b , the flip-flop 70 can be replaced by four logic inverters connected in series at the output Q of flip-flop 68. The ERSS signal is also transmitted to input D of flip-flop 72. The reset circuit 72 receives a previous RG signal. Clock input CK of flip-flop 72 is connected to SIG1S signal.

The common SIG1S signal is also transmitted to one of the inputs of the NAND logic element 74 whose output is we

286 routed to an inverter 75 that sends a SIG1S signal to input D of the four D-type flip-flops 76, 78, 80, 82 The reset input of each flip-flop (clear to zero reset) is connected to output Q flip-flop 72.

When the ERSS signal is set to 1, the first ascending face of the SIG1S signal triggers the flip-flop 72 and sets its output Q to 1. The first ascending face of the SIG1S signal, appearing after the ERSS signal has passed to 1, clears input C (clear) to zero) four flip-flops 76,78,80, 82.

The signals from the outputs Q of the flip-flops 76, 78, 80, 82 are received by the clock inputs CK of four other type D flip-flops 84, 86, 88, 90, respectively. The input D of these flip-flops 84, 86, 88, 90 is permanently set to 1 and the reset input C ("clear") of these circuits is connected to the common initialization signal RG.

The outputs Q of flip-flops 84 to 90 are each connected to a corresponding one input of four NAND logic elements 92, 94, 96, 98, while the second input of these NAND logic elements receives clock signals CK _b CK ₂ , CK ₃ , CK4. The outputs of logic elements 92 to 98 are connected to four inputs of logic element 100 NAND. _

The outputs Q of logic members 84-90 are coupled to four inputs of NAND logic member 102 whose output signal is inverted by logic inverter 104 and is then re-injected into the second input of logic member 74. From the moment the uplink face of the SIG1S signal is identified forming a second characteristic signal) four trigger circuit 76, 78, 80, 82, the latches are enabled and receive, each at its input CK of the clock signal corresponding to the clock signal CK i, CK _2, CK _3, CK '.

The common RG signal is 1 (start of measurement start), the flip-flops 84 to 90 are activated and are therefore sensitive to output signals from the outputs Q of flip-flops 76, 78, 80, 82.

The first transition or the ascending face of the first clock signal, which comes immediately after the ascending face of the SIG1S signal has appeared, triggers the output Q of the flip-flop receiving the respective clock signal.

The flip-flops 76, 78, 80, 82 allow identification of the uplink face of the SIG1S signal and the selection of the first clock signal CK1 passage _; that occurs immediately after this ascending forehead appeared. For example, if CK _{3 is} selected as the clock signal because it is closest to SIG1 S at the moment, selecting that signal by flip-flop 80 causes the output Q of flip-flop to 1, which also causes output Q of corresponding flip-flop 88 to 1. The outputs Q of the other flip-flops 76, 78 and 82 are still at 0.

Thus, the output Q of the flip-flop 88 is at 0, causing the output of the logic member 102 to pass 1. The inverted signal arriving at the second input of the logic member 74 is at 0, blocking the logic member and causing the common signal output thus, the flip-flops 76 to 82 become insensitive to the clock signals CK, and the outputs Q of these flip-flops remain at 0.

This makes it possible to prevent other clock signals from being selected and the selected clock signal CK ₃ is thus stored.

When the output Q of the flip-flop 88 is at 1, the signal CK _{3 is} released by the logic member 96 and is fed to one of the four inputs of the logic member 100. The other inputs of this logic member 100 are at 1, 84, 86, and 90, and the output of logic member 100 thus outputs a CK ₃ signal, hereinafter referred to as CLS signal. The CLS signal corresponds to the clock signal selected by the circuit just described. Since the SIG signal has been synchronized with the C4M signal, this makes it possible to prevent the faces of the SIGi and CLS signals from appearing simultaneously.

In the alternative embodiment shown in FIG. 8a, the functions of identifying the uplink face of the SIG1S signal period and selecting the first transition (uplink face) of the clock signal CK, which occurs immediately after the uplink face of the SIG1S signal period occurs, may also be implemented in the following manner. The common SIG1S signal is transmitted to each of the two inputs of the four AND 101, 103, 105, 107 logical elements, and the CKj signals are routed to the corresponding input of the monostable circuit 106, 108, 109, 111 whose output is connected to the other of the four inputs. AND outputs 101, 103, 105, 107. The outputs of the four logical AND members are provided to the corresponding CK clock inputs of the four memory flip-flops 84, 86, 88 and 90.

Fig. 8b shows a variant of the embodiment of FIG. 6, according to which the degree of flip-flops type D 84 to 90 is omitted. In this figure, only the elements shown in FIG. 6 changed. A common SIG1S or SIG2S signal outputting from the output Q of flip-flop 70 is transmitted to input D of four D flip-flops 300, 302, 304, 306 and clock input CK of another flip-flop 308 of type D whose output Q is connected to the reset input C ("clear", to reset to zero) of the flip-flops 300 to 306.

The D-type flip-flop 310 receives, at its clock input, an ERSS signal whose input D is permanently at 1 and whose output signal from output Q is transmitted to one of the two inputs of each of the four logical members AND 312, 314, 316, 318, which the other of these logic members receives corresponding clock signals CKi CK ₂ , CK ₃ and CK ₄

When the ERSS signal goes to 1, the output Q of flip-flop 310 then goes to 1, releasing the clock signals CK ;. Halfway through the C4M signal period later, the ascending SIG1S signal front appears on the D inputs of flip-flops 300 to 306 while simultaneously activating the reset inputs C (clear to zero) of these flip-flops via flip-flop 308. First ascending clock face CK, for example CK ₃ , which immediately follows the ascending face of the SIG1S signal, activates the corresponding D-type flip-flop 304, whose output Q passes to 1.

Because each output Q of the Type D flip-flop 300 to 306 is transmitted to the input of the corresponding NAND logic member 320, 322, 324, 326 and the second input of each logic member receives a corresponding different CK signal, where i = 1 to 4 to 304, the CK ₃ signal of logic member 324 is routed to one of the four inputs of NAND 328. Three other inputs of logic member 328 are coupled to the outputs of logic members 320, 322, and 326 so that the CK ₃ signal released logic member 324 is again at the output of logic member 328.

The outputs of flip-flops 300 - 306 are connected to four inputs of the NAND 330 logic element, whose output signal is sent to a logic inverter 332, which is connected to the set input S ("set") of flip-flop RS 334. directed to flip-flop reset C (reset) C and flip-flop reset 33 (334) receives a re-initialization signal RG that occurs every two measurements (after "upstream" and "downstream").

Thus, when the output Q of flip-flop 304 goes to 1, the output Q goes to 0, the output of logic member 330 goes to 1, and the input S of flip-flop 334 is 0, forcing the output Q of flip-flop 334 to 1 and output Q. Thus, the flip-flop 310 is switched to 0 and the Q flip-flop is 0, blocking the logic elements 312 to 318. Thus, the flip-flop RS 334 provides the choice of clock signals and clock signal CK ₃ (CLS), selected by flip-flop 304, is thus stored in flip-flop 304. This variant makes it possible to reduce the power consumption of the device because CK signals are not addressed directly to the CK clock inputs of flip-flops 300-306.

The following description, with reference to FIG. 9 and 10 show the generation of a signal SIG, CLS, denoted by IEX _b, which is formed from a number of m (where m is an integer) of consecutive signal periods S1G ,. The signal IEXj is in the form of m of rectangular pulses, wherein the width of each rectangular pulse corresponds to the time elapsed between the moment when the characteristic portion of the signal period SIG appears. for example, its ascending face and the moment when the first subsequent transition of the CLS signal occurs, ie, ascending face of this signal (Fig. 10). For example, the number m is equal to 16, in order to reduce the noise accompanying the measurement and its function is averaging.

When the output Q of flip-flop 60 (FIG. 1) goes to 1, the ERES signal allows the D flip-flop 110 (FIG. 9) to activate the selected CLS clock signal on the clock input CK of flip-flop 110. Reset input C (clear) ", For resetting to zero) of this flip-flop 110 is connected to a reset signal R for resetting to zero, which is activated at the beginning of each measurement.

At the ascending CLS signal (FIG. 10), the output Q of flip-flop 110 goes to 1, indicating the output Q of this flip-flop to 0, releasing the reset input "Reset" to counter 112 16 bits, for example, the HC4040, which starts a 16 right-angled countdown. The output Q5 of the counter 112 passes to the value of 1 at the beginning of the sixteenth rectangular pulse and the inverted value of this signal is transmitted to the reset input C (to reset to zero) of the D-type flip-flop 114.

The output Q of the flip-flop 110 is coupled to the CK input of the flip-flop 114 clock signal, whose input D is permanently at 1 and the transition of the output Q of flip-flop 110 forces the output Q of flip-flop 114 to zero. The output Q of this flip-flop 114 is transmitted to a NAND 116 logic member whose second input is permanently at 1 and whose output is connected to input D of the D-flip-flop 118.

When output Q of flip-flop 114 goes to state 0, input D of flip-flop 118 goes to state 1 (FIG. 10). The first ascending face of the SIG signal _b which reaches the clock input CK of the flip-flop 118 after the output

D went to state 1, causing the flip-flop output Q to go to state 1 (Fig. 10).

The output Q of flip-flop 118 is connected both to input D of the D-type flip-flop 120 and to the reset input C (clear to zero) of this flip-flop and to one of the inputs of the NAND 122 logic connected to the clock input C of the counter 112. The flip-flop output Q is coupled to the reset input C (clear to zero) of flip-flop 118. When the flip-flop output Q of the flip-flop 118 is 0, the logic member 122 receives one of its inputs, the logic signal of value 0 and the output of this logic element is therefore at value 1. When the output Q of flip-flop 118 goes to state 1, the output of logic element 122 goes to state 0 and the downward face thus formed triggers the first rectangular pulse reading. At the same time, the output Q of the flip-flop 118, which was in state 1, goes to state 0 and forcibly converts the output of logic member 12 4th

As soon as the first ascending face of the selected CLS clock signal appears (FIG. 10) at the clock input CK of the flip-flop 120, the output Q of the flip-flop goes to state 0, forcibly converting the output of flip-flop 118 to state 0. from the output Q of the flip-flop 118 goes to state 1 and the first rectangular pulse of the IEXj signal is formed (FIG. 10). By analogy, sixteen consecutive rectangular pulses are generated.

The arrival of the 16th uplink face of the SIG signal causes the signal at the output of the logic element 122 to go to 0 in the same manner, thereby activating counting of the last rectangular pulse by the counter 112. The face to clock input CK of counter 112 causes the counter Q5 to go to state 1 and thus inverted output to state 0, thereby blocking the NAND 122 logic element.

Thus, the signal at the output of logic member 122 goes to state 1 (FIG. 10), which stops reading. The reset input C of the flip-flop J14 goes to 0, forcibly bringing the output Q of flip-flop 114 to state 1, and thus the input D of flip-flop 118 to state 0, which blocks this flip-flop .

When the following ascending face of the selected clock signal appears at the clock input CK of the flip-flop 120, its output Q goes to state 0, forcibly bringing the output Q of the flip-flop 118 to state 1 and producing a sixteenth rectangular pulse of the 1EX signal. .

The next step consists in determining the time t1, which corresponds to the sum of the times in these sixteen rectangular pulses elapsed in each period of the SIG signal, between the moment at which the ascending head of said signal appears and the moment at which the first immediately following ascending head of the CLS signal appears. . This step thus consists in determining the sum of the widths of the sixteen formed rectangular pulses (FIG. 11), of which in FIG. 11 only three.

Fig. 12b is a simplified diagram of a time expander. The time expander is suitable due to the small "width" of the rectangular pulses of the IEX _b signal, which cannot be determined by conventional means, such as pulse reading, which would require a clock and a very high frequency counter. For example, the "width" of each of the rectangular pulses of the IEX _b signals obtained with four clock signals may represent a unit time of the order of 130 to 375 ns.

As shown in this figure, the signal IEX _b represented by the voltage V _e , can take logic values of 0 or 1, is sent to the current generator G _1s providing the current Ij. This generator is connected by one of its terminals to point A. A capacitor C with a capacity of, for example, 22 nF is connected by one of its boards to point A, the voltage U _s at the capacitor terminals is applied to the inverting input of the operational amplifier AO used as a comparator. The non-inverting input of this comparator AO is supplied with a reference voltage V _R (eg +1.5 V). The comparator is supplied with a voltage of V _dd (for example 3.3 V). The output of comparator AA is connected to the trigger logic inverter IL whose output is transmitted to a second current generator G _2, which issues a current _second This second generator is powered by V _dd and is connected to one of the terminals by one of the terminals.

When the voltage V _e is 0 (Fig. 12a), the current L is zero, the voltage U _c at the capacitor terminals remains higher than the reference voltage V _R , the comparator VAO output is zero, the inverter output IL is 1 and the current I ₂ is zero. For example, when the voltage V _{e is} 1 (Fig. 12a), the current I ₂ is 3 mA and the capacitor C discharges up to a certain value U _c lower than V _R , for which the voltage V _{e is} again zeroed. Output voltage VAO goes back to a maximum value (e.g. equal to 2.8 V), a voltage inverter logic passes to the value 0, which allows the gradual re-charge the capacitor current I ₂ to the value equal to about 3 μΑ to a value greater than is the voltage Vr, whereupon the value of the VAO voltage drops again to zero (Fig. 12a) and the voltage IL restores to the value 1 and I ₂ returns to the value zero.

Since Ιμ _ε = I ₂ T _S = CU _c = constant, the ratio It / I ₂ , for example equal to 1000, is derived at I ₂ = 3 mA and I ₂ = 3 μΑ. Thus, the ratio T _s / t _e is equal to 1000.

As a result, for each "width" or duration t _{e of the} rectangular pulse, an expanded time T _s at the output of the comparator is obtained, which can be determined by the classical method to derive a width t _e = T ₅ / 1,000 therefrom. For example, T _s is determined by the value of resistor Rm in the circuit in FIG. 13th

The wiring in FIG. 13 is an example of a wiring performing the function of the described time expander. The circuit contains a resistor R _7, through which the signal IEXj (FIGS. 9 and 10), connected to the point B to which are also connected, first diode Dl, on the one hand connected in series with a resistor R _s and with the base of the NPN transistor 130. The emitter of the the NPN transistor is connected to ground through a resistor R ₉ , while the collector is connected to point C.

Logic level 1 on IEX ₂ defines in network R ₇ , Dj, R _with potential B to which the base of transistor 130 is exposed. The current is thus defined essentially by the formula i = (V _B Vbc) / R9, where ν _Λ denotes the base voltage the emitter of transistor 130, which is approximately 0.65 V.

The point C is connected by its capacitor plate C3, which is in turn connected to the inverting input of comparator 132, voltage supply V _dd, the inverting input of the comparator is connected to the reference voltage V _R. The output signal is transmitted, first, the timing measurements, associated with the microprocessor, not shown, and, second, the resistor R _lo. Resistor R _lo is connected to point D, to which diode D ₂ is also connected, connected in series with resistor R _u and on the other hand base of transistor 136. Transistor emitter PNP 136 is connected to resistor R ₁₂ , while collector is connected to said point C. The connection is supplied with voltage V _dd .

The wiring operates in the manner described with reference to FIG. 12a and 12b. The generators G, iGjZ of FIG. 12b are replaced by transistors 130 and 136, while a diode and a resistor are connected in series to each of the transistors to compensate for the drift of the emitter / base diodes of the transistor. After expanding the time corresponding to the sum of the widths of the sixteen rectangular pulses of the signal IEX _b , the time t _b that is characteristic of the propagation of the ultrasonic signal transmitted by the transducer Tj towards the downstream transducer T _b is thus obtained (Fig. 1).

Approximately 40 ms after the start of transmission of the signal from the converter _Tt , a reset signal R (for resetting to zero) is generated to re-initialize the logic blocks to process the IEX signals. Transmitter T ₂ then emits an ultrasonic signal toward transducer T _b by waking the SE ₂ excitation signal at a frequency equal to 1 MHz generated by the sequential unit 24. The switching block controlled by the microprocessor is switched so that switch 44 is open and switch 46 is closed. The transducer T ₂ receives an ultrasonic signal that propagates from the downstream side to the upstream side approximately 90 ms after the start of transmission, and this signal is processed by the inverter 48 to obtain a signal SIG ₂ having the waveform shown in FIG. 5a.

The block described with respect to FIG. 6, it remains activated in the state it was in when the CLS clock signal was selected, and this block thus outputs the CLS signal. The SIG ₂ signal is synchronized with the C4M signal to generate a SIG2S signal. The SIG ₂ signal is transmitted to the CK clock input of flip-flop 118 (Fig. 9), while the selected CLS clock signal is transmitted to the CK clock inputs of flip-flop 110 and 120. A portion of the SIG ₂ signal is transmitted to the CK flip-flop 110 clock input. 120. The portion of signal SIG ₂ is selected by the ERES signal that activates input D of flip-flop 110. The block shown in FIG. 9 functions in a manner analogous to that described with respect to the generation of the IEX signal, and in this way an IEX ₂ signal is generated.

The signals IEXj and IEX ₂ are shown in FIG. 14. They are shown one above the other for the sake of simplicity of representation and explanation, but it is understood that they take place simultaneously. The IEX ₂ signal is then processed by wiring the expansion circuit for the time expansion shown in FIG. 13, in a manner identical to that already described with reference to this figure.

The time t ₂ , characteristic of the propagation of the ultrasonic signal transmitted by the transducer T ₂ towards the transducer T ₂ , is determined as described for time t _b The difference of these times is then calculated by the microprocessor and the flow rate of fluid Q is proportional to this difference. is then derived as follows Q = K (t ₂ - t 1) / C, where K is an expression or coefficient which takes into account the geometry of the counter and C a correction coefficient related to the speed of sound propagation in water.

The flow rate Q may also be in the form of Q = 2LS (t ₂ - ie) / (t ₁ - t ₂ ) ² with the geometry of FIG. 1, where L and S are the length of the tube and the cross-section of the tube. At L = 10 cm, S = 1 cm ² and t [+1 ₂ = 160 ps, a result of Q = 1 4061 / h is obtained.

Preferably, the CLS signal is a temporary time reference signal that is used as an interferential value to determine times t _t and _{t 2} . This fat ₂ reference signal is then removed when the difference, ie t ₂ , is determined to provide the required metrological indication.

This method does not need to reconstitute the phase of the signal to determine the propagation time of said signal, which is less energy intensive. In addition, this method is more flexible than the methods used in the prior art because it generates a time reference signal and does not need to take into account the transmitted signal. The process according to the invention is reliable because it is operated numerically and the process is also very precise.

For a 1 MHz broadcast frequency, the ultrasonic signal propagation time is about 70 to 80 ms and the phase rotation of the transmitted signal is in the range of 140 to 160 π. For example, if the side-to-side propagation time is 70 us, which corresponds to a phase rotation of 140 π, then the side-to-side propagation time may be 70 ps + 500 ns and the corresponding phase rotation is 140 π + π for the maximum water flow.

For use in domestic water counting, the maximum flow rate is, for example, 2 m ³ / h for a pipe 12 with a diameter equal to 10 mm. That is, in this case, the difference of the expanded times t ₂ t! equal to 500 ns, which corresponds to the phase shift π. Four clock signals CK, as described above, are sufficient to determine a time difference t _{2 of} 500 ns at a minimum consumption.

If the phase shift is higher than π, it is necessary to increase the number of clock signals. It is possible to increase the number of CKi clock signals to increase the flow measurement dynamics, but the energy consumption will be greater.

If the transmit frequency of the ultrasonic signals is varied, it is possible to either increase the measurement accuracy and thereby decrease the counter dynamics (increased frequency) or increase the counter dynamics, but at the same time decrease the measurement accuracy (reduced frequency).

A second embodiment is shown in FIG. 15 and will now be described. As shown in FIG. 15, the measuring device comprises means 200 for generating eight clock CK signals _; where i = 1 to 4. FIG. 16 shows the course of the generated CK signals. These means comprise a crystal controlled oscillator 202 having a frequency equal to 8 MHz. This oscillator outputs a clock signal which is applied to the clock inputs CK of the four D-type flip-flops 204, 206, 208, 210 that form the divider. The output Q of the flip-flop 210 is connected to the input D of the flip-flop 204 and the outputs Q of the flip-flops 204, 206 and 208 are connected to the input D of the flip-flop 206,208 and 210.

Assuming that the CK4 signal is 0 when the ascending face of the clock signal appears, the clock signal CKj, outputted by the flip-flop output Q, goes to 1 and the input D of flip-flop 206 thus equals 1. The clock signal CK ₅ output Thus, the Q of the flip-flop 204 goes to 0. On the next uplink face of the 8 MHz clock signal, the clock signal CK ₂ emitted by the output Q of flip-flop 206 goes to 1. The clock signal CK ₆ emitted by the output Q of flip-flop 206 0th

The following 8 MHz clock signal uplink causes the CK ₃ clock signal output by the flip-flop 208 output Q to go to 1, which causes the CK ₇ clock signal output by the flip-flop Q output 208 to go to the value of 0. The MHz will cause the clock signal CK4, outputted by the output Q of the flip-flop 210 to be set to 1, causing the clock signal CKg, outputted by the output Q of the flip-flop, to be set to 0.

At the next uplink face of the 8 MHz clock signal, the clock signal CK _X drops again to 0, while the signal CK ₅ goes to 1 and the input D of flip-flop 206 also goes to 0. When the next uplink face of the clock 8 passes

MHz, the clock signal CK ₂ emitted by the output Q of flip-flop 206 goes to 0 and the signal CKg then goes to 1.

When another uplink face of the 8 MHz clock signal appears, the clock signal emitted by the flip-flop 208 will go to 0 and the clock signal CK _{7 will} then go to 1. The next uplink face of the 8 MHz clock signal will cause the clock signal CK4 to go to 0 and clock signal CK _S to 1, which indicates flip-flop input D to 1.

At the next uplink of the 8 MHz clock signal, the clock signal CK, to 1, and the clock signal CK _5, to 0. The following uplink face of the 8 MHz clock signal causes the clock signal CK ₂ to move to 1 and hence clock CK ₆ to 0. The 8 MHz uplink of the clock signal causes the CK ₃ clock signal to go to 1 and the CK ₇ clock signal to 0. On the next 8 MHz clock upward, the CK4 clock goes to 1 and the CK ₈ clock goes to 0 , forcibly bringing the input D of flip-flop 204 to 0.

This creates a the eight clock signals CK _3, CK _2, CK _{3, 4} CK, CK _5, CK _least, CK ₇ and CCC. These signals have the same frequency as the excitation signals SE _t and SE _{2 of the} converters (1 MHz), which are generated, for example, on the basis of a clock signal CK ₃ . The signals are phase-shifted by π / 4 relative to each other and are in a fixed phase relationship with respect to the energizing signals in the converter. In addition, these signals have transitions between logic 0 and logic 1.

As shown in FIG. 3, the ERS synchronization signal 24 is generated by the decoder 28 of the sequential unit 24 and its course is shown in FIG. 5a and 5b. Its logic value is 0 and at the end of a period of 95 ms its value passes to a value of 1 when the received signal lies in its middle part, which is less disturbed than the beginning or end of said received signal. This signal triggers the start of the selection phase of the clock signal CK.

As shown in FIG. 15, the ERS signal is transmitted to input D of the D-type flip-flop 212. This flip-flop allows to generate at its output Q an ERSS signal corresponding to an ERS signal synchronized to the clock signal CK _b that is transmitted to the clock input CK of flip-flop 212. was chosen arbitrarily.

The ERE signal is generated by the decoder 28 of the sequential unit 26 (FIG. 3) and its course is shown in FIG. 5b. Its logic value is 0 and 2 ms after passing the ERS signal to 1, its value goes to 1. This signal triggers the start of the measurement phase.

As shown in FIG. 15, the ERE signal is transmitted to the input. D of the D-type flip-flop 214 whose reset input C (clear) for resetting to zero is connected to a signal R that initiates it at the start of the measurement. The output Q of flip-flop 214 is connected to one of the inputs of NOR logic member 216, the other input receiving an ERSS signal. The output of this logic element 216 is connected to a converter 218, to the output of which one of the inputs of the logic element NOR 220 is connected, the other input receiving an 8 MHz clock signal. At the output of this logic element 220, a C8M frequency signal equal to 8 MHz is generated. The C8M signal is re-injected onto the clock input CK of flip-flop 214. The C8M signal is triggered by the transition of the ERSS signal to 0 and is canceled when the ERE signal appears, synchronized by the same C8M signal.

The output Q of flip-flop 214 provides an ERES signal that corresponds to an ERE signal synchronized to the C8M signal. This signal is used to activate the measuring block. The synchronized ERSS signal is transmitted to reset input C (clear) to type D flip-flop 222. The SIG signal (SIG ₂ or SIG ₂ ) is output to the clock input C of that flip-flop whose input D is at value 1.

The output Q of flip-flop 222 is connected to input D of flip-flop 224 of type D. The C8M signal is sent to the clock input C of that flip-flop, and the reset input C (clear) to reset to zero is connected to the RG signal. initiate this flip-flop at the beginning of the complete measurement cycle.

When the ERSS signal at output Q of flip-flop 212 goes to 1, the first ascending face of the adjusted signal SIG! (or SIG ₂ ) causes the flip-flop output Q to pass to 1, allowing the flip-flop output Q to pass at the first ascending face of the C8M signal to 1. The SIG1S signal thus generated corresponds to a SIGi signal synchronized to the C8ML signal

The ERSS signal is also transmitted to input D of the D-type flip-flop 225. The reset input C ("clear" to zero) of the flip-flop 225 receives the previous RG signal.

The common SIG1S signal is transmitted to one of the inputs of a NAND-type logic member 226, the output of which is routed to an inverter 227 which sends an inverted signal to the D-input of eight flip-flops 228, 230,232,234,236, 238, 240, 242. A reset input C ("clear" to reset to zero) of each flip-flop is connected to the output Q of flip-flop 225.

When the ERSS signal is set to 1, the first uplink SIG1S starts the flip-flop 225 and outputs Q to 1. The first uplink SIG1S, appearing after the ERSS signal reaches 1, releases reset input C (clear) for resetting to zero) of eight flip-flops 228 to 242. The outputs Q of flip-flops 228-242 are received at clock inputs CK of eight other flip-flops 244, 246, 248, 250, 252, 254, 256, 258, type D. of these flip-flops 244-258 is permanently set to 1 and their reset input C ("clear" to reset to zero) is connected to a common initialization signal RG. Flip-flop outputs 244 258 are coupled to a corresponding one input of eight logic members 260, 262, 264, 266, 268, 270, 272, 274 NAND, the other of which receives the corresponding clock signals CK _X to Cl < ₈ . The outputs of logic elements 260 to 274 are coupled to eight inputs of logic element_276 NAND.

Flip-flop outputs 244-258 are connected to four inputs of NAND logic module 278, whose output is inverted by logic inverter 280, and is then re-injected to second logic member input 226. Once the uplink SIG1S signal has been identified by eight flip-flops 228-242 , these flip-flops are activated and receive clock signals CK ₂ to CK ₈ at their corresponding clock inputs CK.

The common RG signal is 1 (initialization of the start of measurement), flip-flops 244-258 are activated and are therefore sensitive to the output Q of flip-flops 228-242. The first pass or ascending face of the first clock signal coming immediately after it appears the ascending face of the signal S1G1S, triggers the output Q of the flip-flop receiving the respective clock signal.

For example, if CK _{5 is} selected as the clock is closer to the SIG1S signal, selecting this signal by flip-flop 236 will cause the output Q of this flip-flop to go to 1, which also causes the output Q of corresponding flip-flop 252 to 1. Circuits 228 to 234 and 238 to 242 are still 0.

Thus, the output Q of the flip-flop 252 is at 0, thus causing the logic member 278 to go to 1. The inverted signal arriving at the second input of logic member 226 is at 0, which blocks the logic member and converts the common signal to 0, In this way, the flip-flops 228 to 242 become insensitive to the clock signals CK, and the outputs Q of these flip-flops remain at 0. This makes it possible to prevent other clocks from being selected. signals and in this way the selected clock signal CK _{5 is} stored.

When the output Q of flip-flop 252 is at 1, the CK signal ₅ is released by logic element 268 and is routed to one of the four inputs of logic element 276. The other inputs of this logic element 276 are at value 1, relative to state 0 at the flip-flop 244-250 and 254-258, and as a result, the output of logic element 276 outputs a CK signal ₅ , hereinafter referred to as CLS signal. The CLS signal corresponds to the clock signal selected by the circuit described. Because the signal STGj, synchronized signal C8M, allowing it to prevent the entire signal S1G ₂ and CLS emerged simultaneously.

Everything previously described in relation to FIG. 9 to 14, remains valid for the second embodiment just described. By way of example, when four 4 MHz clock signals CK are used and when the flip-flop 70 synchronizes the SIGj signal with the C4M signal, the CK ₂ , CK ₃ , C4M, SIGj, SIG1S and IEXi signals, for example, have a waveform shown. FIG.

17th

Thus, when measuring the width of a rectangular pulse formed between the uplink face of a SIG signal and the first uplink face of a clock signal CK that occurs immediately thereafter (in the selected example, it is a CK signal ₃ ), it can be observed that (downstream signal transmission) decomposes into two parts, the first random part of duration τ ₂ , which corresponds to the synchronization of the SIG signal! with a C4M signal, wherein the duration τ, is in the range of 0 to 250 ns according to the relative position of the two signals SIG! and C4M, and a second fixed portion of duration τ ₂ , which corresponds to a 125 ns C4M signal half-period. Thus, the rectangular pulse duration is a maximum of 375 ns.

When, on the other hand, the rectangular pulse width formed between the uplink face of the SIG ₂ signal and the first uplink face of the selected clock signal CK ₃ (upstream signal) is to be measured, the rectangular pulse time width is at most 1 ps. 1 ms represents the 1 MHz signal period and e is the safety factor which guarantees the proper functioning of the flip-flops 118 and 120 of FIG. 9. If the timing of the two preceding pulses is read, a maximum duration of 595 ns is obtained.

Thus, using eight 8 MHz clock CK signals, the rectangular pulse time width obtained for the upstream signal transmission is always the sum of two values τ ₂ and τ ₂ , where ή is between 0 and 125 ns (based on synchronization with C8M signal) ) and τ ₂ is 62.5 ns (corresponding to the C8M signal half-period), indicating the time-width of this rectangular pulse to a maximum of 187.5 ns.

The rectangular pulse time width obtained for the downstream signal transmission remains unchanged (970 ns) and the maximum difference between the two values is 782.5 ns. This corresponds to an increase in the dynamics of the measuring device of 1.3 (= 782.5 / 595).

Thus, for example, when the flow rate range covered by a four-hour meter is from 0 to 1500 l / h, the eight-hour meter allows a covered range of up to 19,901 / h.

It should be noted that in order to increase the dynamics of a measuring device using at least four clock signals, it is possible to replace the logical delay corresponding to the time τ _{2 by a} shorter delay which is still compatible with the technology of the logic circuit used. This time can be obtained, for example, by a cascade of inverters or by means of an RC circuit followed by a trigger circuit.

According to the invention, an average of five cycles (one cycle corresponding to the upstream and downstream signals) is sufficient to obtain a resolution of 50 ps.

Claims (26)

PATENT CLAIMS A method of measuring a flowing fluid flow in which two ultrasonic signals are transmitted successively between two ultrasonic transducers spaced apart in the direction of fluid flow, which propagate in opposite directions, each transducer receiving one corresponding ultrasonic signal SIGi , SIG ₂ , characterized in that n clock signals CKj are generated, where i = 1 to nan> 4, containing transitions phase shifted by 2π / η relative to each other in a fixed phase relationship with respect to the drive driver signal and the same frequencies as this signal, the characteristic part of the period of the first signal SIG is selected. received in one propagation direction, the first clock signal transition occurring immediately after the characteristic portion appears, this clock signal CLS is stored, the time ie corresponding to the sum of times in m consecutive periods elapsed in m is determined. the periods between the moment when the characteristic portion of the signal period SIG _b appears and the first successive transition of the clock signal CLS, where m is an integer, the same characteristic portion is identified in m consecutive periods of the second signal SG ₂ received in the opposite direction; time t ₂ , corresponding to the sum of the periods in m periods elapsed between the time at which the characteristic part of the SIG ₂ signal period appears and the time at which the first subsequent CLS signal transition occurs, the difference | t _{2 -} ti | and derive a flow rate Q of the fluid that is proportional to the fe til · Method according to claim 1, characterized in that m = 1. The method of claim 1, wherein m is different from 1 and the period in which the characteristic portion is selected corresponds to the first change of the successive periods of the received first signal SIG _b. The method of claim 1, wherein m is different from 1 and the period in which the characteristic portion is selected is preceded by m consecutive periods of the received first signal SIG. Method according to at least one of Claims 1 to 4, characterized in that the received signals SIG ₁ and SIG _{2 are} processed in the form of rectangular pulses. 6. The method of claim 5, wherein the characteristic portion of the periods of the received signals corresponds to the ascending face of each rectangular pulse. 7. The method of claim 5, wherein the characteristic portion of the received signals corresponds to the downward face of each rectangular pulse. Method according to at least one of claims 1 to 7, characterized in that the clock signals CK are in the form of rectangular pulses. 9. The method of claim 1, wherein the first clock signal CLS transition is an ascending face. The method of claim 1, wherein the first clock signal CLS pass is a descending face. Method according to at least one of Claims 1 to 10, characterized in that corresponding differences SIG 1 - CLS and SIG ₂ - CLS are generated between the signals in order to obtain corresponding signals IEX ₁ and IEX ₂ , which allow to determine corresponding times at ₂ . Method according to claim 5, 8 and 11, characterized in that the IEX! and IEX ₂ are in the form of rectangular pulses, and the method expands the cumulative duration of all rectangular pulses to determine the corresponding times and t ₂ . Method according to at least one of Claims 1 to 12, characterized in that the clock signal CKi is in phase with the drive signal of the converters. Method according to at least one of claims 1 to 13, characterized in that four clock signals CK i are generated, wherein i = 1 to 4. Method according to at least one of Claims 1 to 13, characterized in that eight clock signals CK i are generated, wherein i = 1 to 8. Method according to at least one of Claims 1 to 15, characterized in that a SIGS signal is generated for each received signal, phase shifted relative to the clock signals CK1. 17. The method of claim 16, wherein the SIGS signal is phase shifted by n / n relative to the clock signals CKi. A fluid flow measuring device comprising at least two ultrasonic transducers (T _b T ₂ ) spaced apart from one another in the direction of fluid flow, means for generating an excitation signal of said transducers, means for receiving two ultrasonic signals SIGi and SIG ₂ transmitted by corresponding of said converters in opposite directions and in succession, characterized in that the device further comprises - means (52, 54, 56; 202 - 210) for generating n clock signals CK, where i = lane> 4, which contain the transitions, are phase shifted by 2π / η, are in a fixed phase relation with respect to the energizing signal and have the same frequency as this signal, - further identifying means (76, 78, 80, 82; 228 242) of a characteristic portion of the period of the first received signal SIGj, - select means (76, 78, 80, 82; 228-242) of the first clock signal CKj that occurs immediately after said characteristic portion appears, - means (84, 86, 88, 90; 244-258) for storing this clock signal as a CLS signal, - means for determining the time t1 corresponding to the sum in m of the successive SIG _b periods elapsed between the time when the characteristic portion of each change of the SIG _t signal periods occurs and the moment the first successive CLS signal transition occurs, where m is an integer, - means (76, 78, 80, 82; 228-242) for identifying the same characteristic part in m consecutive periods of the second received signal SIG ₂₎ - means for determining the time t ₂ , corresponding to the sum of the individual sub-periods in each m period elapsed between the time at which the characteristic part of the SIG ₂ signal period appears and the moment at which the first subsequent CLS signal transition occurs - and means for generating the difference | t ₂ - t, and deriving a fluid flow rate Q that is proportional to t ₂ - t _b Device according to claim 18, characterized in that m = 1. 20. The apparatus of claim 18, wherein m is different from 1 and the period in which the characteristic portion is selected corresponds to a first change of successive periods of the received first signal SIG _b. 21. The apparatus of claim 18, wherein m is different from 1 and the period in which the characteristic portion is selected precedes successive periods of the received first signal SIG _b. Device according to at least one of claims 18 to 22 21, characterized in that the means for generating clock signals CK comprises a crystal controlled oscillator (52, 202) followed by n / 2 type D flip-flops (54, 56; 204, 206, 208, 210) forming a divider and enabling thus obtaining signals CK _ir phase shifted by 2π / η between them. Device according to at least one of claims 18 to 23 22, characterized in that the first pass signal selection means comprises n type D flip-flops (76, 78, 80, 82; 228-242), called select flip-flops, each input D of which is connected to a received common SIG signal] or SIG ₂ , wherein each clock input CK receives a different clock signal CKi, differing from one flip-flop to another, and which can be activated by one RAZ input so that when the flip-flop RAZ input is at 1 and the common signal is at 1, there are shown flip-flops sensitive to CK signals. Apparatus according to at least one of claims 18 to 22, characterized in that the selection means of the first clock signal transmission also comprises n logic gates (101, 103, 105, 107) each receiving a common received signal SIG! or SIG ₂ and monostable circuits (106, 108, 190, 111) each receiving a different clock signal CK1 on input, and outputting each of which to one of the other inputs n of the logic gates (101, 103, 105, 107). Apparatus according to claim 23 or 24, characterized in that the means for storing the CLS clock signal comprises n type D flip-flops (84, 86, 88, 90; 244-258), each received as clock clocks. input CK the output signal from the output Q of the selector flip-flop (76, 87, 80, 82; 228-242) and the logic NAND (278) with n inputs, each connected to the output Q of each memory flip-flop, the first signal received at the clock input CK of one of the flip-flops (84, 86, 88. 90; 244-258) activates the memory function of this flip-flop by flipping the output Q of that flip-flop to 1 and output Q to a value of 0 and activate the blocking circuit (102, 104, 74; 278, 280, 226) of the common received signal SIG; or SIG ₂ . The apparatus of claim 25, wherein the NANDs (92, 94, 96, 98; 270-274) receive a clock CK signal at each of their inputs _; and an output signal from output Q of a corresponding memory flip-flop (84, 86, 88, 90; 244-258), the output of each of the logic members being coupled to one of the inputs of the NAND logic member (100, 126) with n inputs, logic members (92,94, 96,98; 260-274) release the associated clock signal CK; when the memory function of the corresponding memory flip-flop is activated.