SK182098A3 - Method and device for measuring the rate of flow of a flowing fluid - Google Patents

Abstract

The invention concerns a method for measuring the rate of flow of a fluid from two ultrasonic signals consecutively transmitted in mutually opposite directions between two transducers. This method consists in: forming n clock signals CKi, i = 1 to n, mutually dephased by 2 pi /n; locating and memorising the first clock signal, called CLS, that is produced immediately after the occurrence of a characteristic part of the first ultrasonic signal received SIG1; determining the time t1 corresponding to the sum over a whole number m of consecutive periods of each of the time lapses between the occurrence of the characteristic part of each of the m periods and the occurrence of the CLS signal which follows, similarly, for the signal received from the opposite direction SIG2, determining the time t2 corresponding to the sum over m consecutive periods of each of the time lapses between the occurrence of the characteristic part of each period and the occurrence of the CLS signal which follows; forming the difference |t2-t1| and deducing therefrom the rate of flow.

Description

METHOD AND DEVICE FOR MEASURING FLOW FLOW FLOW

Technical field

BACKGROUND OF THE INVENTION The present invention relates to a method for measuring the flow of a flowing fluid, comprising successively transmitting two ultrasonic signals between two ultrasonic transducers (sensors, transducers) spaced apart from one another in the direction of fluid flow. in opposite directions to each other, each transducer receiving a corresponding one of these ultrasonic signals. The invention also relates to an apparatus for measuring the flow of a flowing fluid.

BACKGROUND OF THE INVENTION

For many years, the flow rate of a fluid such as warm water flowing in a pipeline has been measured in such a way that the propagation time of the respective ultrasonic signals transmitted in opposite directions to each other downstream and downstream between two ultrasonic transducers located at two points lying spaced from one another in the direction of fluid flow.

In the field of hot water flow measurement, a method is known according to WO 86/02722 comprising simultaneously transmitting an ultrasonic signal from each transducer to a second transducer, the two signals thus propagating in mutually opposite directions. With respect to the flow, the propagation time T2 of the signal transmitted in the direction opposite to the flow direction is higher than the propagation time T1 of the signal transmitted in the flow direction.

The measurement of the two propagation times T1, T2 allows to derive from these times the flow rate of hot water according to the formula Q = K (T2 - T1) / C, where K is a factor taking into account the computer geometry and C is a correction factor related to the speed of sound propagation in water. However, this method presents a considerable disadvantage. Indeed, when one of the converters has been energized, it continues to transmit a signal while receiving a signal from the other converter. When water temperature changes, drifts and drifts are observed

4 4 A 4 / D additional parasitic phase shifts in the received ultrasonic signals. In order to overcome this problem, it is necessary to perform a temperature measurement and to correct the flow measurement according to temperature variations, which complicates the measurement method.

In addition, other methods of measurement, such as those described in EP 0 426 309, are known in which acoustic signals are sent successively in opposite directions in the flowing fluid. The propagation time of each of these signals is measured by detecting, at each of the received acoustic signals, the moment corresponding to the phase change relative to the time reference signal that is coupled to the respective broadcast signal. The detection of this moment is done by a phase detector, but this detection is not accurate.

For each of the acoustic signals, this measurement will be associated with a measurement of the acoustic phase shift induced in the acoustic signal under consideration due to the propagation of this signal in the current. The acoustic phase shift measurement is performed by sampling the received signal in eight capacitors by digitizing the sampled signal and performing synchronized detection of the digitized signal.

However, this measurement method introduces additional noise into the sampled values of the signal, and thus into the measurement itself, as a result of sampling. In addition, this method is complex because it requires a measurement of the propagation time and an acoustic phase shift measurement for each signal transmission in a given propagation direction.

As a result, it is important to find a measurement method that does not introduce additional noise into the measurement and that can be performed more easily than in the prior art.

SUMMARY OF THE INVENTION

The invention provides a method for measuring the flow rate of flowing fluid, wherein successively two ultrasonic transducers spaced apart from each other in the fluid flow direction transmit two ultrasonic signals that propagate in opposite directions, each transducer receiving one respective ultrasonic signal SIGi, SIG ₂ , whose essence

W / R consists in generating n clock signals CK, where i = 1 to nan> 4, containing transitions phase-shifted by 2π / η, in a fixed phase relationship with respect to the drive driver signal and the same frequencies as is this signal, a characteristic portion of the period of the first received SIGi signal in one propagation direction is selected, a first clock signal transition occurring immediately after said characteristic portion appears, this clock signal CLS is stored (memorized) , the time t1 corresponding to the sum of the individual sub-periods in m consecutive periods elapsed in each m period between the time when the characteristic portion of the SIG-γ signal period and the first subsequent transition of the CLS clock signal where m is an integer is identified; the same characteristic portion in m consecutive periods of the second SG signal ₂ , received in the opposite direction of propagation, the time t ₂ corresponding to the sum of the individual sub-periods in each m period elapsed between the time at which the characteristic portion of the SIG ₂ signal period appears and the time at which the first subsequent CLS signal transition occurs with the difference | t ₂ -ti | and the flow rate Q of the fluid, which is proportional to t ₂ - t, is derived.

By generating n intermediate clock signals CK, it is possible to provide a time reference signal that is " variable ", unlike the reference signals used in known methods of ultrasonic measurement of the flow rate of flowing fluid, since once the desired time measurement resolution is sought another more appropriate time reference signal. Since this reference signal is generated based on clock signals, no noise is introduced, as is the case with the prior art methods. In addition, the method is simple since no sampling or synchronous detection step occurs and can thus be used with simple analog means, as opposed to the prior art methods. In addition, an electronic circuit without an analog-to-digital converter can be easily integrated into an application-specific integrated circuit (ASIC).

The use of this " variable " time reference makes it possible to achieve the desired resolution with greater accuracy and faster. With n signals CKj, phase shifted by 2π / η, the resolution will be T / n (T is the resolution

141 / B capability obtained by means of a clock signal (based on which n signals can be generated) and thus it will be possible to obtain a measurement of the time elapsed between the time when the characteristic portion of each change period of said signal appeared and the first pass of the selected clock signal resolution as in the prior art.

Since the resolution increases as the number of measurements increases (according to the relation 1 / λ / Ν, where N is the number of measurements), it is clear that the introduction of that "variable" time reference allows directly to increase the resolution so less measurements are required. to achieve the desired resolution.

Advantageously, the method makes it possible to reduce the energy consumption to obtain an ultrasonic measurement of fluid flow with the same resolution as in the prior art methods.

Furthermore, it should be noted that when sound frequencies of about 1 MHz are used, for example for liquids such as water, the prior art methods (such as those described in EP 0 426 309) are very energy intensive, in view of this. There is a need for an analog-to-digital converter which is capable of sampling a 1 MHz signal and the method is thus very expensive, as opposed to the invention.

The integer number of m periods can be equal to 1 or have other values. When the number m is different from 1, the period in which the characteristic portion is selected may correspond to or precede the first of m consecutive periods.

The received signals SIG1 and SIG2 according to the invention can be processed in the form of rectangular pulses, and in this case the characteristic part of the periods of the received signals corresponds to the ascending or descending front of each rectangular pulse.

According to the invention, the clock signals may be in the form of rectangular pulses, and in this case the first pass of the selected clock signal is an ascending or descending face.

141 / B

In the method according to the invention, corresponding differences SIGi - CLS and SIG ₂ - CLS are generated between the signals in order to obtain the corresponding signals ΙΕΧί and IEX ₂₎ which allow to determine the corresponding times t! at ₂ . The signals IEX1 and IEX ₂ may be in the form of rectangular pulses, and the method of the invention consists in expanding the cumulative duration of all rectangular pulses to determine the corresponding periods t-1 and t ₂ .

For example, the clock signal CK1 is in phase with the drive driver signal. According to the first embodiment, four clock signals are generated. According to the second embodiment, eight clock signals are generated. Preferably, based on each received signal, a SIGS signal is shifted in phase relative to the clock signals, in order to avoid the presently mentioned signals. For example, the SIGS signal is phase shifted by π / η.

The invention further relates to a fluid flow measuring device comprising at least two ultrasonic transducers spaced apart from one another in the direction of fluid flow, means for generating an excitation signal of said transducers, means for receiving two ultrasonic transducers SIG1 and SIG ₂₁ transmitted corresponding to said transducers in said transducer. in which the device further comprises means for generating n clock signals CKj, where i = 1 to nan> 4, which contain transitions, are phase shifted by 2π / η between them, are in fixed phase relation to the excitation signal and having the same frequency as the excitation signal, furthermore, identifying means of a characteristic portion of one period of the first received signal SIG1, selecting means of the first clock signal CKj transition that occurs immediately after a dilute characteristic portion, means for storing the clock signal as a CLS signal, means for determining the time t1 corresponding to the sum of m consecutive SIG1 signal periods elapsed between the time the characteristic portion of each change of the SIG1 signal period occurs and the moment when the first subsequent CLS signal transition occurs, where m is an integer,

141 / B means for identifying the same characteristic portion in m consecutive periods of the second received signal SIG2, means for determining a time t ₂ corresponding to the sum of the individual sub-periods in each m period elapsed between the moment the characteristic portion of the signal period SIG ₂ appears the time at which the first subsequent transition of the CLS signal and the means for generating the difference [t ₂ -t ₁ ] and deriving a flow rate Q of the fluid proportional to t ₂ -t ₁ occurs.

The device can be implemented with simple analog means, such as mainly D or RS flip-flops, thus allowing no analog-to-digital converter or multiple capacitors to store different sampled values.

The means for generating CK clock signals may comprise a crystal controlled oscillator followed by n / 2 type D flip-flops forming a divider, thereby allowing the CK signals to be obtained phase shifted by 2π / η between them.

The first clock signal selection means may comprise n type D flip-flops, called selectors, each input D of which is connected to a received common signal SIG1 or SIG ₂ , each clock input CK receiving a different clock signal CK, different from one flip-flop to the other, and which can be activated by one RAZ input such that when the RAZ input of the flip-flops is 1 and the common signal is 1, said flip-flops are sensitive to CK signals.

The first clock signal selection means may also include n logic gates receiving each at one input a common received signal SIG1 or SIG ₂ and monostable circuits receiving each different clock signal input CK _h and outputting each to one of other inputs n logic gates.

The means for storing the CLS clock signal may comprise both n type D flip-flops, called memory, receiving each as clock input CK the output signal from output Q of the select flip-flop, and secondly a n input logic N n connected to each Q output of each memory

141 / R of the flip-flop, the input D of these memory flip-flops is permanently 1 and the first signal received at the clock input CK of one of the flip-flops activates the memory function of the flip-flop by flipping the output

Q of this flip-flop to 1 and output Q to 0 activates the blocking circuit of the received common signal SIG ^ SIG2.

In a device according to the invention, n NANDs receive at each of their inputs a clock signal CK, and an output signal from output Q of a corresponding memory flip-flop, the output of each of the logic members being coupled to one of the NAND inputs with n inputs, The logic members release the associated clock signal CK, when the memory function of the corresponding flip-flop is activated.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is explained in more detail in the following description, by way of non-limiting examples, with reference to the accompanying drawings, in which:

Fig. 1 shows an arrangement of ultrasonic transducers with respect to a fluid flow according to an embodiment of the invention, FIG. 2 shows another arrangement of ultrasonic transducers with respect to fluid flow, FIG. 3 is a simplified schematic view of a sequential unit used in the apparatus of the invention; FIG. Fig. 4 is a schematic view of one part of the device according to the invention comprising, from a transmit block of ultrasonic signals, a switching block of converters and a block for processing the received ultrasonic signals; 5a a SIG1 signal (SIG2), based on the received ultrasonic signal,

141 / B fig. 5b shows the phase of transmitting and receiving ultrasonic signals, FIG. Fig. 6 is a schematic view of a portion of a device according to the invention comprising a clock block CK, (i = 1 to 4), as well as blocks for selecting and storing a clock signal CLS. 7 shows the course of four clock signals CK in their relationship to each other, FIG. 8a shows a variant of part of the apparatus of FIG. 6, which selects the CLS clock signal; FIG. 8b shows an alternative part of the device of FIG. 6, which selects and stores the CLS clock signal; FIG. 8c shows the course of the main signals used as a function of time, FIG. Fig. 9 is a schematic view of part of a device according to the invention comprising a simplified block for generating signals IEXt and IEX ₂ (SIGi-CLS and SIG ₂ -CLS); 10 a diagram showing the step of generating signals iExit and IEX _2, FIG. 11 shows the waveform of the SIG1, CLS and IEX1 signals; FIG. 12a is a schematic view showing the principle of time expansion; FIG. 12b is a simplified diagram of a time expander; FIG. 13 is a schematic diagram of a portion of a device according to the invention comprising a time expander, FIG. 14 shows the course of the various signals SIG ^ SIG ₂ , ΙΕΧί and IEX ₂₎ FIG. 15 is a diagram of part of the apparatus shown in FIG. 6 according to a second embodiment of the invention, FIG. 16 shows the course of eight clock signals CK, in relation to each other, and FIG. 17 signals CKi, CK3, C4M, SIG1, SIG1S and IEX1.

141 / B

DETAILED DESCRIPTION OF THE INVENTION

A device for measuring the flow of a fluid such as hot water is shown in FIG. 1, 2, 4, 7 and 11 and is generally referred to as device 10. As shown in FIG. 1, the device according to the invention comprises two ultrasonic transducers (sensors, sensors) T _it T2 disposed in a flow and spaced apart from one another in the direction of the fluid flow so that they can read the fluid velocity information. In FIG. 1, the transducers Τ1, T2 are located opposite each other at opposite ends of the measuring tube 12 in which fluid flows in the direction of arrow F.

Another example of an arrangement of transducers T1, T2 is shown in FIG. 2, wherein the transducers are seated in the foot of the storage pockets 14 and 16 perpendicular to the direction of fluid flow indicated by the arrow F. The fluid flows in a measuring tube 18 housing two mirrors 20 and 22 intended to reflect ultrasonic signals as indicated. FIG. 2. The ultrasonic transducers T1, T2 are driven by an excitation signal that passes from the sequential unit (controller) 24, shown in simplified form in FIG. 3. The sequential unit comprises a 16-bit computer 26, a decoder 28 connected to the computer, and a block 30 made up of multiple logic elements (gates).

The computer 26 and the block 30 are powered by a 1 MHz clock signal CK-γ originating from a 4 MHz clock signal, which block also receives the TE signal coming from the decoder 28 and allowing the transmission of an ultrasonic signal. Block 30 outputs an excitation signal SE, which has the role of a pilot signal. The computer 26 is activated when a RAZ signal is emitted by a standby clock (not shown).

As shown in FIG. 4, a signal SE, referred to as SJE signal (intended to drive the converter T1), is transmitted to two respective inputs of two NANDs 32 and 34 mounted in parallel to reduce the internal impedance of this circuit. The second input of each of the NAND logic members is connected to a logic signal of value 1. These logic circuits may be replaced by inverters. The output of both logic elements 32 and 34 is connected to a capacitor Cn connected in series with resistor R1, with resistor R1 connected to resistor R2 which is connected

141 / B to the two terminals of the converter Ti. The terminal T1 of the transducer, which is connected to the resistors R1 and R2, is also connected to the resistor R3 to which the current coming from the collector of the switching transistor 36 is supplied.

PNP transistor 36 is supplied to its emitter voltage V _dd. Serial mounting of resistors R2 and R3 allows to obtain a stable voltage for polarization of converters, equal to V _dd / 2. Capacitor Ci, isolates the voltage V _dd from the input (on the SE signal side) to cancel the potential of the splitter circuit with resistors R? and £3 when mainly the signal SE ^ is at a quiet level. This also makes it possible to avoid excessive consumption.

The resistor isolates the Ti converter from the input signal to ensure that the right-angled pulse SE1 signal is compatible with the high-capacity converter and allows better control of the emission impedance.

For the transducer T2, a symmetrical circuit is generated, generated by the SE2 signal, with NAND 38 and 40 logic elements, resistors R4, R5 and Rg, capacitor C2 and transistor 42.

Since the two symmetrical wiring branches are not connected to each other, a good isolation between the two transistors is thus ensured.

When the transistor Τχ transmits an ultrasonic signal based on an excitation signal with a frequency equal to 1 MHz, the switch block switch 44 is open and the switch 46 connected to the converter T2 is closed. The ultrasonic transmission signal E shown in FIG. 5, has a duration of, for example, equal to 40 ps. Approximately 80 ms after the start of the broadcast signal, an ultrasonic signal is received by the T2 converter (Fig. 5b). The received signal, indicated by the signal R in FIG. 5a and 5b, is processed by an inverter 48 (FIG. 4), for example a HCO4 type CMOS inverter comprising three cascaded inverters that output a SIGi signal in the form of a rectangular pulse shown in FIG. 5a.

Alternatively, the processing may be performed using a differential comparator whose one input receives a signal output from the switching block and the other input receives a reference signal output from a specialized divider or from an RC network defining the mean value of the signal.

141 / B

As shown in FIG. 6, the device 10 comprises means 50 for generating four clock signals CKj, where i = 1 to 4. These means comprise a 4 MHz crystal controlled oscillator 52. This oscillator emits a clock signal applied to the clock inputs CK of the two D-type flip-flops 54, 56 that form the divider. The waveform of the 4 MHz clock signal is shown in FIG. 7th

The flip-flop output 56 is connected to the flip-flop input 54 and the flip-flop output 54 is connected to the flip flop input 56. As shown in FIG. 7, as the 4 MHz uplink of the signal arrives, the clock signal CK1, outputted by the flip-flop output 54, is passed to 1, and the flip-flop input D is also equal to 1.

Thus, the clock signal CK3 output of flip-flop 54 goes to 0. At the next ascending face of the 4 MHz clock signal, clock signal C Kg output of flip-flop 56 goes to 1. Clock signal CK4 output from flip-flop output Q In the future ascending face of the 4 MHz clock signal, the clock signal CK-kles decreases again to 0, while the signal CK3 goes to 1 and the signal to input D of flip-flop 56 also goes to 0.

When the following ascending face arrives the edge of the 4 MHz clock signal, the clock signal C Kg, outputted by the flip-flop 56 output Q, goes to 0, and the signal CK4 thus goes to 1, resulting in the signal at input D of flip-flop 54 At the next ascending face of the 4 MHz clock signal, the clock signal CK3 goes to 1, the clock signal CK3 goes to 0, and the input D of flip-flop 56 goes to 1. '

The following ascending face of the 4 MHz clock signal causes the clock signal C Kg to pass to 1, and thus the clock signal CK4 and the input D of the flip-flop 54 to 0. In FIG. 7th

141 / B

The four clock signals CKg, CKg, CK3 and CK4 shown in FIG. 7. These signals have the same frequency as the excitation signals SEg and S E? converters (1 MHz), which are based on the clock signal CKg. The signals are phase shifted by π / 2 relative to each other and are in a fixed phase relationship with respect to the drive driver signals. In addition, these signals have transitions between logic 0 and logic 1.

An alternative to wiring 50 is to generate a 1 MHz clock signal C K1 based on a 2 MHz clock signal generated by the oscillator and via the D-type flip-flop. is thus formed by signals CKG the creation of an artificial delay, for example, by the monostable circuit (or the delay circuit) and the signal CK ₃ and CK4 are easily obtained based on the signals CKG C and the inverting kg.

As shown in FIG. 3, an ERS synchronization signal is generated by the decoder 28 of the sequential unit 26, its course being shown in FIG. 5 and 5a. Its logic value is 0 and after a time period of 95 ms its value passes to 1 when the received signal is in its middle part, which is less disturbed than the beginning or end of the received signal. This signal triggers the start of the phase in which the clock signal CK is selected.

As shown in FIG. 6, the ERS signal is transmitted to input D of the D-type flip-flop 58. This flip-flop makes it possible to produce at its output Q an ERSS signal corresponding to an ERS signal synchronized to the clock signal CK1 which is transmitted to the clock input CK of flip-flop 58. was chosen arbitrarily.

An ERE signal is generated by the decoder 28 of the sequential unit 26 (FIG. 3) and its course is shown in FIG. 5b. Its logic value is 0 and 2 ms after the ERS signal reaches 1, its value goes to 1. This signal triggers the start of the measurement phase.

As shown in FIG. 6, the ERE signal is transmitted to input D of the Type D flip-flop 60, whose reset input C ("clear") to reset to zero is connected to the R signal, which reinitializes it at the start of the measurement. Output Q

141 / B of flip-flop 60 is connected to one of the inputs of NOR logic member 62, the other input of which receives an ERSS signal. The output of this logic member 62 is connected to an inverter 64, the output of which is connected to one of the inputs of a NOR logic member 66, the other input of which receives a 4 MHz clock signal. At the output of this logic member 66, a 4M frequency signal of 4 MHz is output. The C4M signal is re-injected at the clock input CK of flip-flop 60. The C4M signal is triggered by transitioning the TRSS signal to zero and is blocked when an ERE signal synchronized with the same C4M signal occurs. It should be noted that this logic connection limits the presence of the C4M signal mainly at the CK inputs of flip-flops 60 and 70, minimizing circuit consumption (Fig. 8c).

The output Q of flip-flop 60 provides an ERES signal corresponding to the ERE signal synchronized with the C4M signal, the course of which is shown in FIG. 8c. This signal is used to activate the measuring block, which will be described below. The synchronized ERSS signal is sent to reset input c (clear to zero) of D-type flip-flop 68. The SIG signal (SIG1 or SIG2) is output to the clock input C of that flip-flop whose input D is at first

Flip-flop output 68 is connected to input D of flip-flop 70. The C4M signal is output to clock input C of that flip-flop 70 and reset input C (clear to zero) is connected to RG, the function of which is to initialize the flip-flop at the beginning of a complete measurement cycle, which is constituted by transmitting an ultrasonic signal in the direction of fluid flow called "downstream transmission" and transmitting a signal in the opposite direction, referred to as "countercurrent transmission".

When the ERSS signal at the output Q of flip-flop 58 goes to 1, the first ascending face of the adjusted signal SIG-γ (or SIG ₂ ) allows the signal at the output Q of flip-flop 68 to pass to 1, circuit 70 to a value of 1 at the first ascending face of the C4M signal. The SIG1S signal thus generated corresponds to the SIG1 signal synchronized with the C4M signal.

141 / B

To obtain a phase shifted signal SIG1S relative to the signal SIG1, the flip-flop 70 can be replaced by four logic inverters connected in series at the output Q of flip-flop 68. The ERSS signal is also transmitted to input D of flip-flop 72. The reset circuit 72 receives a previous RG signal. Clock input CK of flip-flop 72 is connected to SIG1S signal.

The common SIG1S signal is also transmitted to one of the inputs of the NAND logic element 74, the output of which is routed to an inverter 75 that sends a SIG1S signal to input D of the four D-type flip-flops 76, 78, 80, 82. Clear (reset to zero) is connected to output Q of flip-flop 72.

When the ERSS signal is set to 1, the first ascending face of the SIG1S signal triggers the flip-flop 72 and sets its output Q to 1. The first ascending face of the SIG1S signal appearing after the ERSS signal reaches 1 releases reset input C ("clear" , to reset to zero) of the four flip-flops 76, 78, 80, 82.

The signals from the outputs Q of the flip-flops 76, 78, 80, 82 are received by the clock inputs CK of four other type D flip-flops 84, 86, 88, 90, respectively. The input D of these flip-flops 84, 86, 88, 90 is permanently set to 1, and the reset input C ("clear") of these circuits is connected to a common initialization signal RG.

The outputs Q of flip-flops 84 to 90 are each connected to a corresponding one input of four NAND logic elements 92, 94, 96, 98, while the second input of these NAND logic elements receives clock signals CK ^ C Kg, CK3, CK4 · Logic outputs members 92 to 98 are connected to four inputs of logic member 100 NAND.

The outputs Q of the logic members 84-90 are coupled to four inputs of the NAND logic member 102 whose output signal is inverted by the logic inverter 104 and then re-injected into the second input of the logic member 74. From the moment the uplink face of the SIG1S signal is identified forms a kind

141 / B of the signal) by the four flip-flops 76, 78, 80, 82, these flip-flops are activated and receive at their input a CK clock signal corresponding to a clock signal CK1, CK3, CK3, CK4 ·

The common RG signal is 1 (start of measurement start), the flip-flops 84 to 90 are activated and are therefore sensitive to output signals from the outputs Q of flip-flops 76, 78, 80, 82.

The first transition or the ascending face of the first clock signal, which comes immediately after the ascending face of the SIG1S signal has appeared, triggers the output Q of the flip-flop receiving the respective clock signal.

The flip-flops 76, 78, 80, 82 allow identification of the uplink face of the SIG1S signal and the selection of the first clock signal CK transition that occurs immediately after the uplink face has occurred. For example, if the CK3 clock signal is selected because it is closest to the SIG1S signal at a given time, selecting that signal by flip-flop 80 causes the output of flip-flop Q to 1, which also causes output Q of corresponding flip-flop 88 to 1. the other flip-flops 76, 78 and 82 are still at 0.

Thus, the output Q of the flip-flop 88 is at 0, causing the output of the logic member 102 to pass 1. The inverted signal arriving at the second input of the logic member 74 is at 0, blocking the logic member and causing the common signal output thus, the flip-flops 76 to 82 become insensitive to the clock signals CK, and the outputs Q of these flip-flops remain at 0.

.from

This makes it possible to prevent other clock signals from being selected and thus the selected clock signal CK3 is stored.

When the output Q of the flip-flop 88 is at 1, the CK3 signal is released by the logic member 96 and fed to one of the four inputs of the logic member 100. The other inputs of this logic member 100 are at 1 relative to the 0 state of the flip-flop outputs. , 86 and 90, and thus outputs the logic member 100

141 / B signal CK3, hereinafter referred to as CLS signal. The CLS signal corresponds to the clock signal selected by the circuit just described. Because the signal

The SIG ₁ has been synchronized with the C4M signal, which prevents the SIGi and CLS faces from appearing simultaneously.

In the alternative embodiment shown in FIG. 8a, the functions of identifying the uplink face of the signal period SIG1S and selecting the first transition (uplink face) of the clock signal CKi, which occurs immediately after the uplink face of the signal period SIG1S occurs, may also be implemented in the following manner. The common SIG1S signal is transmitted to each of the two inputs of the four AND 101, 103, 105, 107 logic elements and the CK signals, each to a corresponding input of the monostable circuit 106,108, 109, 111, the output of which is connected to the other of the four inputs. AND 101, J.Q3, 105, 107. The outputs of the four said ANDs are provided to the corresponding CK clock inputs of the four memory flip-flops 84, 86, 88, and 90.

Fig. 8b shows a variant of the embodiment of FIG. 6, according to which the degree of flip-flops type D 84 to 90 is omitted. In this figure, only the elements which, with respect to FIG. 6 changed. A common SIG1S or SIG2S signal outputting from the output Q of flip-flop 70 is transmitted to input D of four D flip-flops 300, 302, 304, 306 and clock input CK of another flip-flop 308 of type D whose output Q is connected to the reset input C ("clear", to reset to zero) of said flip-flops 300 to 306.

The D-type flip-flop 310 receives, at its clock input, an ERSS signal whose input D is permanently at 1 and whose output signal from output Q is transmitted to one of the two inputs of each of the four logical members AND 312, 314, 316, 318, which the other of these logic elements receives the corresponding clock signals CK _lt CK2, CK3 and CK4 ·

When the ERSS signal is set to 1, the output Q of flip-flop 310 is set to 1, releasing the clock signals CK. Half the C4M signal period later, the ascending SIG1S signal front appears on the D flip-flop inputs

141 / B of the circuits 300 to 306 and at the same time activates reset inputs C ("clear" to reset to zero) of these flip-flops by flip-flop 308.

The first uplink face of the clock signal CK, for example CK3, immediately following the uplink face of the SIG1S signal, activates the corresponding type D flip-flop 304 whose output Q passes to 1.

Because each output Q of the D-type flip-flop 300 to 306 is transmitted to the input of the corresponding NAND logic member 320, 322, 324, 326 and the second input of each logic member receives a corresponding different CKi signal where i = 1 to 4 304 to a value of 1 releases the CK3 signal of logic member 324, which is routed to one of the four inputs of logic member NAND 328. Three other inputs of logic member 328 are connected to the outputs of logic members 320, 322 and 326 so that the CK3 signal released by logic member 324 , is again at the output of logic member 328.

The flip-flop outputs 300-306 are connected to four inputs of a NAND 330 logic element whose output signal is sent to a logic inverter 332, which is connected to the set input of the flip-flop RS 334. Output flip-flop 334 it is routed to the flip-flop reset C input and the flip-flop reset C input 334 receives a re-initialization signal Tfô that occurs at every two measurements (after "upstream" and "downstream" broadcasting ,,).

Thus, when the output Q of flip-flop 304 goes to 1, the output Q becomes 0, the output of logic member 330 goes to 1, and the input S of flip-flop 334 is 0, forcing the output Q of flip-flop 334 to 1 and the flip-flop output Q is 0. The flip-flop input C (clear) of the flip-flop 310 goes to 0 and the Q-flip-flop is 0, blocking the logic elements 312 to 318. Thus, the flip-flop RS 334 ensures clock selection and the clock signal CK3 (CLS) selected by the flip-flop 304 is thus stored in flip-flop 304. This variant makes it possible to reduce the power consumption of the device since the CK signals are not addressed directly to the clock inputs of the flip-flop CK 300 - 306.

141 / B

The following description, with reference to FIG. Figures 9 and 10 show the generation of a SIGi-CLS signal, denoted by ΙΕΧ-ι, which is formed from a number of m (where m is an integer) of consecutive SIGy signal periods The lEXi signal is in the form of m rectangular pulses. elapsed between the moment when the characteristic part of the signal period SIG ^ appears, for example its ascending face and the moment when the first subsequent transition of the CLS signal occurs, i.e. for example, the ascending face of this signal (Fig. 10). For example, the number m is equal to 16 in order to reduce the noise accompanying the measurement and its function is averaging.

When the output Q of flip-flop 60 (FIG. 1) goes to 1, the ERES signal allows the D flip-flop 110 (FIG. 9) to activate the selected CLS clock signal on the clock input CK of flip-flop 110. Reset input C (clear) For resetting), the flip-flop 110 is connected to a resetting signal R for resetting to zero, which is activated at the beginning of each measurement.

With the ascending CLS signal (FIG. 10), the output Q of flip-flop 110 goes to 1, indicating the output Q of this flip-flop to 0, releasing the reset input "Reset" to counter 112 16 bits , such as the HC4040, which starts a 16 right-angled countdown. The output Q5 of the counter 112 passes to the value of 1 at the beginning of the sixteenth rectangular pulse and the inverted value of this signal is transmitted to the reset input C (to reset to zero) of the D-type flip-flop 114.

The output Q of the flip-flop 110 is coupled to the CK input of the flip-flop 114 clock signal, whose input D is permanently at 1 and the transition of the output Q of flip-flop 110 forces the output Q of flip-flop 114 to zero. The output Q of this flip-flop 114 is transmitted to a NAND 116 logic member whose second input is permanently at 1 and whose output is connected to input D of the D-flip-flop 118.

141 / B

When output Q of flip-flop 114 goes to state 0, input D of flip-flop 118 goes to state 1 (FIG. 10). The first ascending face of the SIG signal that arrives at the clock input CK of the flip-flop 118 after the output D has gone to state 1 causes the flip-flop output Q to go to the state 1 (FIG. 10).

The output Q of flip-flop 118 is connected both to input D of flip-flop 120 and to reset input C (clear to zero) of this flip-flop, and second to one of the inputs of the NAND 122 logic member whose output is fed to the clock input CK of the counter 112. The flip-flop output Q is connected to the reset input C (clear to zero) of flip-flop 118. When the output Q of flip-flop 118 is at 0, the logic member 122 receives at one of its inputs, a logic signal of value 0 and the output of this logic element is therefore at value 1. When the output Q of flip-flop 118 goes to state 1, the output of logic element 122 goes to state 0 and the downward face thus formed triggers the first rectangular pulse reading. 112. At the same time, the output Q of the flip-flop 118, which was in state 1, goes to state 0, forcibly converting the output of logic member 124 to state 1.

As soon as the first ascending face of the selected CLS clock signal appears (FIG. 10) at the clock input CK of the flip-flop 120, the output of that flip-flop goes to state 0, forcibly converting the output of flip-flop 118 to state 0. from the output Q of the flip-flop 118 goes to state 1 and the first rectangular pulse of the lEXi signal is formed (FIG. 10). By analogy, sixteen consecutive rectangular pulses are generated.

The arrival of the 16th uplink face of the SIGi signal in the same way causes the signal at the output of the logic element 122 to go to state 0, thereby activating counting of the last rectangular pulse by the counter 112. For example, the clock input CK of counter 112 causes the counter Q5 to pass to state 1, and thus inverted output to state 0, thereby blocking the NAND 122 logic element.

141 / B

Thus, the signal at the output of logic member 122 goes to state 1 (FIG. 10), which stops reading. The reset input C of the flip-flop 114 goes to 0, forcibly bringing the output Q of flip-flop 114 to state 1, and thus the input D of flip-flop 118 to state 0, which blocks this flip-flop circuit.

When the following ascending face of the selected clock signal appears at the clock input CK of the flip-flop 120, its output Q goes to state 0, forcibly bringing the output Q of the flip-flop 118 to state 1 and generating a sixteenth rectangular pulse. .

The next step consists in determining the time t1, which corresponds to the sum of times in the sixteen right-angled pulses elapsed in each period of the signal SIGi between the moment at which the ascending head of said signal appears and the moment at which the first immediately following ascending head of the CLS signal appears. This step thus consists in determining the sum of the widths of the sixteen formed rectangular pulses (FIG. 11), of which in FIG. 11 only three.

Fig. 12b is a simplified diagram of a time expander. The time expander is suitable due to the small "width" of the rectangular pulses of the IEX _X signal, which cannot be determined by conventional means such as pulse reading that would require a clock and a very high frequency counter. For example, the "width" of each of the rectangular pulses of the IEX signals obtained with the four clock signals may represent a unit time of the order of 130 to 375 ns.

As shown in this figure, the signal lEX,, represented by the voltage V _e , can take logic values of 0 or 1, is transmitted to a current generator Gi providing a current Ιχ. This generator is connected by one of its terminals to point A. A capacitor C with a capacity of, for example, 22 nF is connected by one of its boards to point A, the voltage Us at the terminals of the capacitor is applied to the inverting input of the operational amplifier A0 used as a comparator. The non-inverting input of this comparator A0 is powered by a reference voltage Vr (eg +1.5 V). The comparator is supplied with a voltage of V _d d (for example 3.3 V). The output of comparator A0 is connected to the trigger logic inverter JL, the output of which is transmitted to the second

141 / B of the current generator G ₂ , which emits current l ₂ . This second generator is powered by V _dd and is connected to one of the terminals by one of the terminals.

When the voltage V _{e is} equal to 0 (Fig. 12a), the current h is zero, the voltage Uc at the capacitor terminals remains higher than the reference voltage Vr, the comparator VAO output is zero, the inverter IL output is 1 and the current ₁₂ is zero. For example, when the voltage V _{e is} 1 (Fig. 12a), the current Ii is 3 mA and the capacitor C discharges up to a certain value Uc lower than Vr, for which the voltage V _{e is} again zeroed. Output voltage VAO goes back to a maximum value (e.g. equal to 2.8 V), a voltage inverter logic passes to the value 0, which allows the re-phasing capacitor charging current l ₂ with a value equal to about 3 μΑ to a value higher than the voltage Vr whereupon the VAO voltage value drops again to zero (Fig. 12a) and the IL voltage returns to 1 and ₂ again to zero.

Since ht _e l = ₂ T _p = CU _c = constant, it derives the ratio h / 12, which is for example equal to 1000, where h = 3 mA = ₂ Al 3 μΑ. The ratio T _s / t _e is thus equal to 1000.

As a result, for each "width" or duration t _{e of the} rectangular pulse, an expanded time T _s at the output of the comparator is obtained, which can be determined by the classical method to derive a width t _e = T _s / 1000 therefrom. For example, the time T _s is determined by the value of the resistor R 10 in the circuit in FIG. 13th

The wiring in FIG. 13 is an example of a wiring performing the function of the time expander described above. The circuitry comprises a resistor R7, through which the signal lEX ^ (Figs. 9 and 10) passes, connected to point B, to which diode D1 is connected, in series, with resistor Rs and with base of transistor NPN 130. Emitter of this transistor The NPN is connected to ground through a resistor Rg, while the collector is connected to point C.

from

Logic level 1 on the signal ΙΕΧ-ι defines the network R7, Di, Rs potential B to which the base of transistor 130 is exposed. The current is thus defined essentially by the formula i = (Vb - Vbe) / R9, where V _v b denotes the base voltage - the emitter of transistor 130, which is approximately 0.65 V.

141 / B

The point C is connected by its capacitor plate C3, which is in turn connected to the inverting input of comparator 132, voltage supply V _dd, the inverting input of the comparator is connected to the reference voltage Vr. The output signal is transmitted both to the measurement timer associated with the microprocessor (not shown) and to the resistor Rio. Resistor Rio is connected to point D, to which diode D ₂ is also connected, connected in series with resistor R11 and base of transistor 136. The emitter of transistor PNP 136 is connected to resistor R12, while the collector is connected to the above point C. The wiring is powered by V _dd .

The wiring operates as described above with reference to FIG. 12a and 12b. The generators Gy and G ₂ of FIG. 12b are replaced by transistors 130 and 136, while a diode and a resistor have been connected in series to each of the transistors to compensate for the drift of the emitter / base diodes of the transistor. By expanding the time corresponding to the sum of the widths of the sixteen rectangular pulses of the signal ΙΕΧ-ι, the time t1, which is characteristic of the propagation of the ultrasonic signal transmitted by the converter Ti towards the converter downstream (FIG. 1). .

Approximately 40 ms after the transmission of the signal from the converter Ti is started, a reset signal R (for resetting to zero) is generated to re-initialize the logic blocks to process the IEX signals. The transmitter T ₂ of the transmitted ultrasonic signal to the transducer Ti, and the excitation drive signal SEG at a frequency equal to 1 MHz, generated by the sequencer unit 24. The switching block controlled by the microprocessor, the switch such that the switch 44 is opened and switch 46 is closed . The transducer T1 receives an ultrasonic signal that propagates from the downstream side to the upstream side approximately 90 ms after the start of transmission, and this signal is processed by the inverter 48 to obtain a SIG signal. which has the course shown in FIG. 5a.

The block described in relation to FIG. 6, it remains activated in the state it was in when the CLS clock signal was selected, and this block thus outputs the CLS signal. The SIG ₂ signal is synchronized with the C4M signal to generate a SIG2S signal. The SIG ₂ signal is transmitted to the clock input CK of flip-flop 118 (Fig. 9), while the selected CLS clock signal is transmitted to the clock

141 / B CK inputs of flip-flops 110 and 120. Part of the SIG ₂ signal is sent to the CK clock input of flip-flops 110 and 120. The SIG ₂ signal part is selected by the signal

ERES, which activates the input D of flip-flop 110. The block shown in FIG. 9 functions in a manner analogous to that described with respect to the generation of the IEX signal, and in this way the IEX signal is generated.

The signals 1EX 1 and IEX ₂ are shown in FIG. 14. They are shown one above the other for the sake of simplicity of representation and explanation, but it is understood that they take place simultaneously. The IEX ₂ signal is then processed by wiring the expansion circuit for the time expansion shown in FIG. 13, in a manner identical to that already described with reference to this figure.

The time t ₂ , characteristic of the propagation of the ultrasonic signal transmitted by the converter T ₂ towards the converter T 1, is determined as described above for the time t 1. The difference in these times is then calculated by the microprocessor and the flow rate Q, which is proportional to this difference, is then derived as follows Q = K (t ₂ - ti) / C, where K is an expression or coefficient that takes into account the geometry of the reader. C correction factor linked to the speed of sound propagation in ¹ water.

The flow rate Q may also be in the form of Q = 2LS (t ₂ -ti) / (t ₁ -t ₂ ) ² with the geometry of FIG. 1, where L and S are the length of the tube and the cross-section of the tube. At L = 10 cm, S = 1 cm ² and t 1 +1 ₂ = 160 ps, a result of Q = 1 406 l / h is obtained.

Preferably, the CLS signal is a temporary time reference signal that is used as an interferential value to determine times t1. at ₂ . This reference signal t ₁ and t ₂ is then removed when the difference t ₁ - t ₂ is determined which provides the required metrological indication.

r

This method does not need to reconstitute the phase of the signal to determine the propagation time of said signal, which is less energy intensive. In addition, this method is more flexible than the methods used in the prior art because it generates a time reference signal and does not need to take into account the transmitted signal. The process according to the invention is reliable because it is operated numerically and the process is also very precise.

141 / B

For a 1 MHz transmission frequency, the ultrasonic signal propagation time is about 70 to 80 ms and the phase rotation of the transmitted signal is in the range of 140 to 160 π. For example, if the side-to-side propagation time is 70 με, which corresponds to a phase rotation of 140 π, then the side-to-side propagation time may be 70 με + 500 ns and the corresponding phase rotation is 140 π + π for maximum water flow.

For use in domestic water counting, the maximum flow rate is, for example, equal to 2 m ³ / h for pipes 12 with a diameter of 10 mm. This means that in this case, the difference in the expanded times t ₂ - t will be 500 ns, which corresponds to the phase shift π. Four clock signals CKj, as described above, are sufficient to determine a time difference t _{2 of} 500 ns at minimum consumption.

In case the phase shift is higher than π, it is necessary to increase the number of clock signals. It is possible to increase the number of clock signals C K to increase the flow measurement dynamics, but the energy consumption will be higher.

If the transmit frequency of the ultrasonic signals is varied, it is possible to either increase the measurement accuracy and thereby decrease the counter dynamics (increased frequency) or increase the counter dynamics, but at the same time decrease the measurement accuracy (reduced frequency).

A second embodiment is shown in FIG. 15 and will now be described. As shown in FIG. 15, the measuring device includes means 200 for generating eight clock signals CKj, where i = 1 to 4. FIG. 16 shows the course of the generated signals CKi. These means comprise a crystal controlled oscillator 202 having a frequency of 8 MHz. This oscillator outputs a clock signal that is applied to the clock inputs CK of the four D-type flip-flops 204, 206, 208, 210 that form the divider. The flip-flop output 210 is connected to the flip-flop input D and the flip-flop outputs 204, 206 and 208 are connected to the flip-flop input D, 206, 208, and 210.

Assuming that the CK4 signal is 0 when the ascending face of the clock signal appears, the clock signal CKi, outputted by the flip-flop output Q, goes to 1 and the input D of flip-flop 206 also

Thus, the clock signal C Kg emitted by the output Q of flip-flop 204 goes to 0. On the next ascending face of the 8 MHz clock signal, the clock signal CK ₂ emitted by the output Q of flip-flop 206 goes to 1. Clock signal C Thus, the Kg output of the flip-flop 206 is converted to 0.

The following 8 MHz clock signal uplink causes the CK3 clock signal output of the flip-flop 208 output to go to 1, which causes the CK7 clock signal output of the flip-flop 208 to transmit to 0. The next 8 MHz clock signal closes transition of the clock signal CK4 output of flip-flop 210 to 1, causing the clock signal C Kg output Q of said flip-flop to 0, and thus input D of flip-flop 204 also goes to 0.

At the next uplink of the 8 MHz clock signal, the clock signal K K- drops again to 0, while the CK5 signal goes to 1, and the D input of the flip-flop 206 also goes to 0. When the next 8 MHz clock signal goes up , clock signal CK? provided by the output Q of flip-flop 206 goes to 0 and the Cg signal then goes to 1.

When another uplink face of the 8 MHz clock signal appears, the clock signal emitted by the flip-flop 208 goes to 0 and the clock signal CK7 then moves to 1. The next uplink face of the 8 MHz clock signal causes the clock signal CK4 to move to 0 and clock. the signal CK _f1 to 1, which indicates the flip-flop input D to 1.

At the next 8 MHz clock signal uplink, the clock signal CK-ι goes to 1 and the clock signal CK5 to 0. The next uplink face of the 8 MHz clock signal causes the clock signal CK ₂ to pass to 1 and hence the clock signal C Kg to 0. The 8 MHz uplink of the clock signal causes the CK3 clock signal to be set to 1 and the CK7 clock signal to 0. On the next 8 MHz clock signal, the clock signal CK4 passes to 1 and the clock signal.

141 / B signal CKa goes to 0, forcibly bringing the D input of flip-flop 204 to 0.

This creates a the eight clock signals CK _lt C K2, C K3, CK4, CK ₅ CK6, CK7, and C each. These signals have the same frequency as the excitation signals SE1 and SE _{2 of the} converters (1 MHz), which are generated, for example, on the basis of the clock signal CK-ι. The signals are phase-shifted by π / 4 relative to each other and are in a fixed phase relationship with respect to the excitation signals in the transmitter. In addition, these signals have transitions between logic 0 and logic 1.

As shown in FIG. 3, the ERS synchronization signal 24 is generated by the decoder 28 of the sequential unit 24 and its course is shown in FIG. 5a and 5b. Its logic value is 0, and at the end of a period of 95 ms, its value becomes 1 when the received signal lies in its middle portion, which is less disturbed than the beginning or end of said received signal. This signal triggers the start of the selection phase of the clock signal CKi.

As shown in FIG. 15, the ERS signal is transmitted to the D input of the D-type flip-flop 212. This flip-flop allows to generate at its output Q an ERSS signal corresponding to an ERS signal synchronized with the clock signal C K1 which is transmitted to the clock input CK of the flip-flop 212. Kg was chosen arbitrarily.

The ERE signal is generated by the decoder 28 of the sequential unit 26 (FIG. 3) and its course is shown in FIG. 5b. Its logic value is 0 and 2 ms after passing the ERS signal to 1, its value goes to 1. This signal triggers the start of the measurement phase.

As shown in FIG. 15, the ERE signal is transmitted to input D of flip-flop 214 at

Type D, whose reset input C ("clear") for resetting to zero is connected to the R signal that initiates it at the start of the measurement. The output Q of flip-flop 214 is coupled to one of the inputs of the NOR logic member 216, the other input receiving the ERMS signal. The output of this logic element 216 is coupled to an inverter 218, to the output of which one of the inputs of the logic element NOR 220 is connected, the other input receiving an 8 MHz clock signal. At the output of this logic element 220, a C8M frequency signal equal to 8 MHz is generated. The C8M signal is

141 / B re-injects the CK clock input of flip-flop 214. The C8M signal is triggered by the transition of the ERSS signal to 0 and is canceled when the ERE signal appears, synchronized with the same C8M signal.

The output Q of flip-flop 214 provides an ERES signal that corresponds to an ERE signal synchronized to the C8M signal. This signal is used to activate the measuring block. The synchronized ERSS signal is transmitted to reset input C (clear to zero) of the D-type flip-flop 222. The SIG signal (SIG ^ or SIG2) is transmitted to the clock input C of that flip-flop whose input D is at value 1.

The output Q of flip-flop 222 is connected to input D of flip-flop 224 of type D. The C8M signal is sent to the clock input C of that flip-flop, and the reset input C (clear) to reset to zero is connected to the RG signal. is to initiate this flip-flop at the beginning of the complete measurement cycle.

When the ERSS signal at the output Q of flip-flop 212 goes to 1, the first ascending face of the adjusted signal SIG ^ (or SIG2) causes the flip-flop output Q to transition to 1, allowing the flip-flop output Q to transition.

224 at the first ascending face of the C8M signal to 1. The signal SIG1S thus generated corresponds to a signal SIGj synchronized with the C8M signal.

The ERSS signal is also transmitted to input D of the D-type flip-flop 225. The reset input C ("clear" to zero) of the flip-flop 225 receives the previous RG signal.

The common SIG1S signal is transmitted to one of the inputs of a NAND-type logic member 226, the output of which is routed to an inverter 227 which sends an inverted signal to the D input of eight D-type flip-flops 228, 230, 232, 234, 236, 238, 240, 242 and to the clock input CK of the flip-flop 225. To the output Q of the flip-flop

225, a reset input C ("clear" to reset to zero) of each flip-flop is connected.

141 / B

When the ERSS signal is at 1, the first ascending face of the SIG1S signal triggers the flip-flop 225 and its output Q passes to 1. The first ascending face of the SIG1S signal, appearing after the ERSS signal has passed to 1, releases reset input C (clear, , for resetting to zero) of eight flip-flops 228 to 242. The outputs Q of flip-flops 228-242 are received at clock inputs CK of eight other flip-flops 244, 246, 248, 250, 252, 254, 256. 258 type D. Input D of these flip-flops 244-258 is permanently set to 1 and their reset input C ("clear" to reset to zero) is connected to a common initialization signal RG. Flip-flop outputs 244-258 are coupled to a corresponding one input of eight logic members 260, 262, 264, 266, 268, 270, 272, 274 of the NAND, the other of which receives the corresponding clock signals CKg to CKg. The outputs of the logic elements 260 to 274 are connected to the eight inputs of the logic element 276 of the NAND.

Flip-flop outputs 244-258 are connected to four inputs of NAND logic module 278, whose output is inverted by logic inverter 280, and is then re-injected to second logic member input 226. Once the uplink SIG1S signal has been identified by eight flip-flops 228-242 , these flip-flops are activated and receive clock signals CKg to CKg at their corresponding CK clock inputs.

The common RG signal is 1 (initialization of the start of measurement), flip-flops 244-258 are activated and are therefore sensitive to the output Q of flip-flops 228-242. First pass or ascending face of the first clock signal that comes immediately after detects the ascending face of the SIG1S signal, triggers the output Q of the flip-flop receiving the corresponding clock signal.

For example, if C Kg is selected as the clock is closer to the SIG1S signal, selecting that signal by flip-flop 236 will cause the output Q of that flip-flop to go to 1, which will also trigger the output Q of corresponding flip-flop 252 to 1. Circuits 228 to 234 and 238 to 242 are still 0.

141 / B

Thus, the output Q of the flip-flop 252 is at 0, thus causing the logic member 278 to go to 1. The inverted signal arriving at the second input of logic member 226 is at 0, which blocks the logic member and converts the common signal to 0, In this way, the flip-flops 228 to 242 become insensitive to the clock signals CK, and the outputs Q of these flip-flops remain at 0. This makes it possible to prevent other others from being selected. clock signals and in this way the selected clock signal C Ks is stored.

When the output Q of flip-flop 252 is at 1, the signal C Ks is released by logic member 268 and is routed to one of the four inputs of logic member 276. The other inputs of this logic member 276 are at 1, relative to state 0 at the flip-flop 244-250 and 254-258, and as a result, the output of logic element 276 outputs a CK signal, hereinafter referred to as CLS signal. The CLS signal corresponds to the clock signal selected by the circuit described. Since the SIGi signal has been synchronized by the C8M signal, this makes it possible to prevent the faces of the SIGi and CLS signals from appearing simultaneously.

Everything previously described in relation to FIG. 9 to 14, remains valid for the second embodiment just described. Examples include that when using four clock signals CK at a frequency of 4 MHz, and when using the flip-flop 70 synchronizes the signal SIG to the signal C4M, the signals CK _1, CKA, C4M, the signal SIG1S and Lex J are, for example, the course shown in Fig. 17th

Thus, if the width of the rectangular pulse generated between the ascending face of the SIG signal is to be measured! and the first ascending face of the clock signal CK. that occurs immediately thereafter (CK3 signal in the chosen example), it can be observed that the time width of this rectangular pulse (downstream signal transmission) decomposes into two parts, the first random portion of duration x _lt corresponding to the synchronization of the signal SIGj. with a C4M signal, wherein the duration τι is in the range of 0 to 250 ns according to the relative position of the two signals SIG1 and C4M, and a second fixed portion of duration 12 corresponding to a half-period of the C4M signal of 125 ns. The rectangular pulse duration is therefore a maximum of 375 ns.

141 / B

On the other hand, when measuring the width of the rectangular pulse formed between the uplink face of the SIGg signal and the first uplink face of the selected clock signal CK3 (upstream signal), the rectangular pulse time width is at most equal to 1 ps. represents a signal period of 1 MHz and e is a safety factor which guarantees the proper functioning of the flip-flops 118 and 120 of FIG. 9. If the timing of the two preceding pulses is read, a maximum duration of 595 ns is obtained.

Thus, when using eight clock signals CK, with a frequency of 8 MHz, the rectangular pulse time width obtained for upstream signal transmission is always the sum of two values τχ and 12, where τχ is in the range of 0 to 125 ns (based on synchronization with C8M) and τ ₂ is 62.5 ns (corresponding to the C8M signal half-period), indicating the time-width of this rectangular pulse to a maximum of 187.5 ns.

The rectangular pulse time width obtained for the downstream signal transmission remains unchanged (970 ns) and the maximum difference between the two values is 782.5 ns. This corresponds to an increase in the dynamics of the measuring device of 1.3 (= 782.5 / 595).

Thus, for example, when the flow range covered by a four-hour meter is from 0 to 1500 l / h, the eight-hour meter allows a covered range of up to 1,950 l / h.

It should be noted that in order to increase the dynamics of a measuring device using at least four clock signals, it is possible to replace the logical delay corresponding to the time τ _{2 by a} shorter delay which is still compatible with the technology of the logic circuit used. This time can be obtained, for example, by a cascade of inverters or by means of an RC circuit followed by a trigger circuit.

According to the invention, an average of five cycles (one cycle corresponding to the upstream and downstream signals) is sufficient to obtain a resolution of 50 ps.

Claims (26)

A method of measuring a flowing fluid flow in which two ultrasonic signals are transmitted successively between two ultrasonic transducers spaced apart in the direction of fluid flow, which propagate in opposite directions, each transducer receiving one corresponding ultrasonic signal SIGi , SIG2, characterized in that n clock signals CK, where i = 1 to nan> 4, containing transitions, are phase-shifted by 2π / η relative to each other in a fixed phase relationship with respect to the drive driver signal and the same frequencies as this signal, selecting a characteristic portion of the period of the first signal SIG1 received in one propagation direction, selecting the first pass of the clock signal that occurs immediately after said characteristic portion appears, this clock signal CLS is stored, the time is determined those corresponding to the sum of the individual sub d For example, in m consecutive periods elapsed in each m period between when the characteristic portion of the SIG1 signal period appears and the first successive transition of the CLS clock signal, where m is an integer, the same characteristic portion in m consecutive periods of the second SG2 signal is identified. received in the opposite propagation direction, a time t ₂ corresponding to the sum of the individual sub-periods in each m period elapsed between the time at which the characteristic portion of the SIG2 signal period appears and the time at which the first subsequent CLS signal transition occurs; | t2-ti | and deriving a flow rate Q of the fluid which is proportional to Í 2 - t 1. from Method according to claim 1, characterized in that m = 1. The method according to claim 1, wherein m is different from 1 and the period in which the characteristic portion is selected corresponds to the first of m consecutive periods of the received first signal SIG1. 31,141 / B The method of claim 1, wherein m is different from 1 and the period in which the characteristic portion is selected is preceded by m consecutive periods of the received first signal SIGi. Method according to at least one of Claims 1 to 4, characterized in that the received signals SIG ₁ and SIG _{2 are} processed in the form of rectangular pulses. Method according to claim 5, characterized in that the characteristic part of the periods of the received signals corresponds to the ascending face of each rectangular pulse. The method of claim 5, wherein the characteristic portion of the received signals corresponds to the downward face of each rectangular pulse. Method according to at least one of Claims 1 to 7, characterized in that the clock signals CKj are in the form of rectangular pulses. The method of claim 1, wherein the first clock signal CLS transition is an ascending face. The method of claim 1, wherein the first clock signal CLS pass is a descending face. Method according to at least one of Claims 1 to 10, characterized in that corresponding differences SIG ₁ - CLS and SIG ₂ - CLS are produced between the signals in order to obtain corresponding signals IEX ₁ and IEX ₂ , which allow to determine corresponding times t 1 and t ₂ . Method according to claim 5, 8 and 11, characterized in that the signals ΙΕΧϊ and IEX ₂ are in the form of rectangular pulses and the method expands the cumulative duration of all rectangular pulses to determine corresponding times ₂ . 31,141 / B Method according to at least one of Claims 1 to 12, characterized in that the CKi clock signal is in phase with the drive excitation signal. Method according to at least one of claims 1 to 13, characterized in that four clock signals CK i are generated, wherein i = 1 to 4. Method according to at least one of Claims 1 to 13, characterized in that eight clock signals CK i are generated, wherein i = 1 to 8. Method according to at least one of Claims 1 to 15, characterized in that a SIGS signal is generated for each received signal, phase shifted relative to the clock signals CK i, The method of claim 16, wherein the SIGS signal is phase shifted by π / η relative to the clock signals CK i. A fluid flow measuring apparatus comprising at least two ultrasonic transducers (Ti, T ₂ ) spaced apart from one another in the direction of fluid flow, means for generating an excitation signal for said transducers, means for receiving two ultrasonic signals SIGi and SIG ₂ transmitted by the corresponding of said converters in opposite directions and in succession, characterized in that the device further comprises - means (52, 54, 56; 202 - 210) for generating n clock signals CK, where i = 1 to nan> 4, which contain transitions, are phase shifted by 2π / η, are in a fixed phase relationship with respect to to the excitation signal and have the same frequency as this signal, - further identifying means (76, 78, 80, 82; 228-242) of the characteristic portion of the period of the first received signal SIGi, - select means (76, 78, 80, 82; 228-242) of the first clock signal CKj passing immediately after said characteristic portion appears, 31,141 / B - means (84, 86, 88, 90; 244-258) for storing this clock signal as a CLS signal, means for determining a time t1 corresponding to the sum in m of successive SIGi signal periods elapsed between the time when a characteristic portion of each of the m SIG signal periods occurs; and the moment the first subsequent CLS signal transition occurs, where m is an integer, - means (76, 78, 80, 82; 228-242) for identifying the same characteristic part in m consecutive periods of the second received signal SIG2, - means for determining the time t ₂ corresponding to the sum of the individual sub-periods in each m period elapsed between the time at which the characteristic part of the SIG ₂ signal period appears and the moment at which the first subsequent transition of the CLS signal occurs and means for generating a difference t ₂ -1 and deriving a flow rate Q of the fluid which is proportional to t ₂ - t ₁ . Device according to claim 18, characterized in that m = 1. The apparatus of claim 18, wherein m is different from 1 and the period in which the characteristic portion is selected corresponds to the first of m consecutive periods of the received first signal SIG1. The apparatus of claim 18, wherein m is different from 1 and the period in which the characteristic portion is selected is preceded by m consecutive periods of received first signal SIG1. from Apparatus according to at least one of claims 18 to 21, characterized in that the means for generating CK clock signals comprises a crystal-controlled oscillator (52, 202), followed by n / 2 flip-flops (54, 56; 204, 206, 208). , 210) of the type D, forming a divider, thereby enabling the acquisition of CKi signals, phase shifted by 2π / η between them. 31,141 / B Apparatus according to at least one of claims 18 to 22, characterized in that the selection means of the first clock signal passage comprises n type D flip-flops (76, 78, 80, 82; 228-242), called select flip-flops, each of which input D is connected to the received common SIG signal! or SIG ₂ , wherein each clock input CK receives a different clock signal CKi, differing from one flip-flop to another, and which can be activated by one RAZ input so that when the flip-flop RAZ input is at 1 and the common signal is at 1, there are shown flip-flops sensitive to CK signals. Apparatus according to at least one of claims 18 to 22, characterized in that the selection means of the first clock signal passage also comprise n logic gates (101, 103, 105, 107) each receiving a common received signal SIG1 or SIG ₂ at one input. monostable circuits (106, 108, 190, 111), each receiving a different clock signal CK, on input, and whose output is transmitted each to one of the other inputs n of the logic gates (101, 103, 105, 107). Apparatus according to claim 23 or 24, characterized in that the means for storing the CLS clock signal comprises n type-D flip-flops (84, 86, 88, 90; 244-258), each receiving as clock input CK output signal from output Q of selector flip-flop (76, 87, 80, 82; 228-242) and, second, N input logic (278) connected to each output Q of each memory flip-flop, input D of these memory flip-flops is constant at 1 and the first signal received at the clock input CK of one of the flip-flops (84, 86, 88, 90; 244-258) activates the memory function of that flip-flop by flipping the output Q of that flip-flop to 1 and output Q to 0, activating the blocking circuit (102, 104, 74; 278, 280, 226) of the common received signal SIG ₁ or SIG ₂ . -i A 4 AND 4 ID Device according to claim 25, characterized in that n of the NAND logic elements (92, 94, 96, 98; 270-274) receive at each of its inputs a clock signal CKj and an output signal from the output Q of the corresponding memory flip-flop (84). , 86, 88, 90; 244-258), the output of each of the logic elements being coupled to one of the inputs of the NAND logic element (100, 126) with the inputs, one of the logic elements (92, 94, 96, 98; 260). 274) releases the associated clock signal CKi when the memory function of the corresponding memory flip-flop is activated. 1/12 < ¹² 1 i and y ^ 2 '