BG63231B1 - Method and device for metering the discharge of a running fluid - Google Patents

Abstract

The invention relates to the measurement of the discharge of a running fluid based on two ultrasound signals transmitted simultaneouls in opposite directions between two ultrasound sensors. By the method n chronometric signals CKi are formed, i having the values from 1 to n, which signals are mutually phase-shifted by 2 pi /n, the first chronometric signal labelled as CLS which appears immediately after the apperance of the characteristic section of the first ultrasound signal SIG1 received is identitied and stored. The time t1 is determined which time corresponds to the sum of time intervals of an integer m successive periods between the moment in which the characteristic section appears of every of the m periods of signal SIG1, and the time in which the subsequent signal CLS appears. In a similar manner time t2 is determined for signal SIG2, produced in opposite direction which corresponds to the sum of time intervals of m successive periods between the moment in which the characteristic section of each period and the moment when subsequent CLS signal appears. The difference (t2-t1) is recorded and the discharge is subtracted. 26 claims, 17 figures

Description

Technical field

The invention relates to a method and apparatus for measuring the flow of a fluid fluid, the method of which is to cause the consecutive propagation in opposite directions of two ultrasonic signals between two sensors spaced apart from each other in the direction of the fluid flow, wherein each sensor receives the appropriate ultrasonic signal.

BACKGROUND OF THE INVENTION

It is known that the flow of fluid, for example, hot water flowing through a tube, can be measured by measuring the respective propagation times of ultrasonic signals emitted along and against the flow between two ultrasonic sensors located at points, spaced apart in the direction of fluid flow.

WO 86/02722 describes the measurement of hot water flow by a method that involves simultaneously emitting corresponding ultrasonic signals from two sensors, the two signals propagating in opposite directions. Because of the flow, the time T2 for propagation of the signal emitted against the current is longer than the time T1 for the propagation of the signal emitted over the current.

By measuring the two propagation times T1 and T2, it is possible to calculate the flow rate of hot water using the formula Q - K (T2-T1) / C, in which K is a coefficient taking into account the configuration of the meter and C is correction factor related to the speed of sound propagation in water.

The method has one major drawback. When one of the sensors is just activated, it continues to produce a signal while receiving the signal coming from the other sensor. When fluctuating in water temperature, drift is observed leading to deviation in readings and additional unwanted phase shifts in the received ultrasonic signals are observed.

To overcome this problem, it is necessary to make temperature measurements and adjust the flow rates as a function of temperature fluctuations, which complicates the measurement method.

Other methods of measurement are known, for example, the method described in EP 426 309, in which acoustic signals, each of which include a phase inversion, are emitted sequentially in opposite directions in a flowing fluid. The propagation time of each of the received acoustic signals is measured by determining the moment at which it becomes the phase reversal relative to the base time associated with the emission of said signal. This moment is detected by a momentary phase detector, but this is not accurate. For each of the acoustic signals 20, timing is associated with measuring the displacement of the acoustic phase caused by said acoustic signal due to the propagation of the signal in the flow.

The displacement of the acoustic phase is measured by quantization during the signal received on eight capacitors by digitally converting that quantum signal and by performing synchronous detection on the resultant signal converted to digital.

Unfortunately, due to quantization, this measurement method introduces additional noise to the quantized values of the signal and thus to the measurement itself.

In addition, this method is complex, 35 requiring measurement of the propagation time and the shift of the acoustic phase for each signal sent in a given propagation direction.

Therefore, it would be useful to measure a measurement method that does not cause additional noise to the measurement and which is easier to perform than previously known methods.

SUMMARY OF THE INVENTION

The invention provides a method for measuring the flow rate of a fluid fluid, the method comprising inducing two ultrasound 50 wave signals that are propagated sequentially in opposite directions between two ultrasonic sensors spaced apart from each other in the direction of the flow of the fluid fluid, with each sensor receiving an appropriate ultrasonic signal SIC _P SIGj, wherein the method is characterized by the following steps. Formation of η time-domain CC signals, such as i = 1 to η and η> 4, which signals include phase transitions that are phase-shifted at 2π / n and are permanently dependent on the excitation signal to activate the sensors, have the same frequency as the excitation signal. Selecting a section from the characteristic period of the first received signal SIC _p received from one of the propagation directions. Selection of the first phase transition of the chromometer signal, which occurs immediately after the appearance of the specified feature section.

Store the timed signal designated CLS. Determining the time t _p corresponding to the sum of the times elapsed between the moment at which the feature section of each of the SIG signal periods appears, the integer m of consecutive periods, and the time at which the first phase transition of the next CLS signal. Identification of the same feature region at m successive periods of the second received signal SIGj obtained from the reverse propagation direction. Determining the time t ₂ corresponding to the sum of the times elapsed between the moment at which the characteristic section of each of the m periods of the SIG ₂ signal appears and the time at which the first phase transition of the next CLS signal occurs. Reporting the difference t ₂ -t, | and hence the velocity of the flowing fluid Q, which is proportional to | t ₂ -tj.

By creating η intermediate chronometer signals, it is possible to provide a base time that is "variable" as opposed to the base times used in known methods for ultrasonic flow measurement of flowing fluid, because once the desired resolution is obtained ability to measure time, another, more appropriate base time may be sought.

Because this base time is based on timed signals, no additional noise is produced, unlike the analog-to-digital inverter.

The method is simplified because it does not use time quantization and a synchronized detection step and can therefore be performed by simplified analog means, unlike the methods known in the art.

Furthermore, an electronic circuit without an analog-to-digital inverter is easier to integrate into a specific application integrated circuit (ASIC).

By using this variable base time, it is possible to obtain the desired resolution more accurately and faster.

For η the signals of SC. with phase shifts of 2π / η the resolution is T / n (T is the time-resolved resolution based on which η signals can be generated), and it is possible to measure the time interval between the time at which it occurs the portion of the characteristic of each of the periods of said signal, and the moment at which the first phase transition of the selected chronometric signal occurs, obtaining a better resolution than that of the prior art.

The resolution thus obtained by increasing the number of measurements (dependence 1 / ^ N, where N is the number of measurements) and it is clear that the variable base time creates an opportunity to directly increase the resolution, thus achieving the desired resolution requires fewer measurements.

Another advantage of this method is that it allows to reduce the energy consumption required to obtain an ultrasonic measurement of the flow rate of a flowing fluid at the same resolution as previously known methods in the art.

In addition, it should be noted that when using frequencies to emit acoustic waves of about 1 MHz, for example for fluid as-water according to displaced methods, for example, the method described in patent EP 0426309, the energy costs are high as necessary the use of an analog-to-digital inverter capable of quantizing3

this time signal at 1 MHz and which is also expensive, unlike the method according to the invention.

The integer number m of periods may be equal to 1 or receive other values. When m is other than 1, the period from which the feature section is selected may correspond to the first of m consecutive periods or may also precede the indicated m periods. According to the invention, the received signals SIG, and SIGj can be formulated as square wave pulses, in which case the portions of the characteristic of the periods of the received signals correspond to the raised or dropped end of each pulse.

According to the invention, the timed signals can be in the form of square wave pulses, in which case 20 the first phase transition of the selected timed signal is the raised end or the dropped end.

According to the method according to the invention, the corresponding SIGj-CLS and SIG ₂ -CLS differences between the 25 signals are calculated to receive the respective IEX and 1EX ₂ signals, which makes it possible to determine the respective times tj and t ₂ .

The signals IEX and 1EX ₂ can be 30 in the form of square wave pulses and the method of the invention consists in increasing the cumulative duration of all pulses to determine the corresponding times t, and tj. 35

For example, the timed signal CK may be in phase with the excitation signal to activate the sensors.

In one variant, four time signals are formed. 40

In another embodiment, eight chronometric signals are formed.

The advantage is that, on the basis of each received signal, a SIG ₅ signal is generated, which is phase shifted with respect to the chrono-numbered signals, to prevent the said signals from being simultaneous.

For example, the SIG _s signal may be phase shifted to π / η. 50

The invention also provides a device for measuring flow of a fluid fluid, according to the invention the device includes at least two ultrasonic sensors spaced apart from each other in the direction of the fluid flow; means for generating an excitation signal to activate the sensors; and means for receiving two ultrasonic signals SIG, and SIG ₂ , emitted sequentially by respective means from said sensors in opposite directions.

According to the invention the device also includes the following means.

Means for forming η chronometric signals CK, such as i = l to η and η> 4, which signals include phase transitions, are phase shifted by 2 π / η, in constant dependence on the excitation signal to activate the sensors and are of the same frequency as the specified excitation signal.

Means for identifying a portion of the characteristic period of the first SIG signal received;

Means of selecting the first phase transition from the chronometric signal SK, which "appears immediately after the appearance of the specified characteristic region.

Means for storing the timed signal designated "CLS". The means of determining the time t _p corresponding to the sum of the times elapsed between the moment at which the characteristic section of each of the w periods of the SIG signal occurs, (npH the integer w of consecutive periods) and the time at which the first phase transition of the next CLS signal.

Means for identifying the same feature region in m successive periods of the second SIG ₂ signal received;

Means for determining the time t ₂ corresponding to the sum of the times elapsed between the moment at which the characteristic section of each of the m periods of the SIG ₂ signal appears and the time at which the first phase transition of the next CLS signal occurs; and

Difference accounting tools t ₂ -t, | and to derive from it the velocity of the fluid fluid Q, which is proportional to | t ₂ -t, |.

The device can be equipped with simple analog means, for example D-type triters or RS-type triters, and therefore it is not necessary to provide an analog-to-digital inverter or to provide multiple capacitors for storing quantized values.

Means for forming timing signals may contain a quartz generator followed by n / 2 D-type triters, forming a divider and thus making it possible to obtain CK _P signals that are phase shifted by 2 d / n.

The means for selecting the first phase transition of the timed signal may comprise n selectable D-type triters, with the D input of each of the triters connected to the total received signal SIG, or SIG ₂ , the timed input CK of each of the triters receiving the respective chronometrated signal SK., which is different from one triter to another, making it possible to activate the triters through RAZ reset inputs in such a way that when the tritorial inputs RAZ on the triters are at 1 and when the total signal is at 1, the indicated triters are felt. Vital to the signals SK.

The means of selecting the first phase transition from the timed signal may also contain η logical pain, each of which receives the total received SIG signal, or SIG ₂ through a corresponding input and η monostable circuits, each receiving a different chronometric signal CKi and transmitting its output signal respectively to one of the other inputs of the η logic blocks.

The timing signal storage means CLS may first comprise η the number of D-type storage triters each receiving, such as a timed input SK, an output Q of a respective selector triter, and a second NAND logic block having n inputs, each of which is connected to the Q output of the respective storage triter, with the D input of each of the storage triters constant at 1, and the first signal received at the timed input SK of one of the triters activates its storage function by triggering the output Q of the specified triter to go to 1 and its Q output to go to 0, thereby activating a blocking loop to hold the total received signal SIG, or SIG ₂ .

In the device according to the invention, each of the n NAND logic blocks receives a timed signal CKi and the output Q of the respective storage triter through its respective inputs, the output of each of the blocks is connected to a corresponding input of the NAND logic block having η inputs, one of the η logic blocks releases the associated chronometric signal CKi when the storage function of the respective storage triter is activated.

Description of the attached figures

The invention is illustrated by an example which does not limit it, and by the accompanying figures, of which:

Figure 1 shows the location of the ultrasonic sensors with respect to fluid flow in a first embodiment;

FIG. 2 is another embodiment of how ultrasonic sensors can be positioned relative to the fluid flow; FIG.

Figure 3 is a simplified schematic view of a sequence sensor used in the device according to the invention;

FIG. 4 is a schematic view of a portion of the device according to the invention, including the units for emitting ultrasonic signals, a node for switching on the sensors and a node for conditioning the received ultrasonic signals;

Figure 5a shows the SIG signal (SIG ₂ ) formed on the basis of the ultrasonic signal received;

Figure 5b shows the steps of emitting and receiving ultrasonic signals;

Figure 6 is a schematic view of a portion of the device according to the invention, comprising a node for generating chronometric signals CKi (i-1 to 4) and assemblies for selecting and storing the timing signal CLS;

Figure 7 shows the waveforms of the four time-lapse CK signals compared to each other;

8a is an embodiment of the part of the device of FIG. 6, which selects the timed CLS signal;

Figure 8b is an embodiment of the portion of the device of Figure 6 that shows the nodes for selecting and storing the CLS timed signal;

Figure 8c is the waveforms of the main signals used in the time function;

Figure 9 is a schematic simplified view of a part of the device according to the invention comprising the IEX signal generating units and IEX ₂ (SIG, -CLS and SIG ₂ -CLS);

Figure 10 is a diagram showing the step of generating IEX signals;

Figure 11 - waveforms of the SIG, SLS and IEX signals;

Figure 12a is a schematic view showing the principle of extended time;

Figure 12b is a simplified schematic view of a time expander;

Figure 13 is a schematic view of a part of the device according to the invention including a time expander;

Fig. 14 - Different signals SIG ,, SIG ₂ , IEX, and IEX ₂ Fig. 15 is a schematic view of the part of the device of Fig. 6 in a second embodiment of the invention;

Figure 16 shows the waveforms of the eight time-lapse CK signals juxtaposed with each other;

Figure 17 shows the waveforms of the signals CK, CK ₃ , C4M, SIG, SIG, s and IEX ,;

Examples of carrying out the invention

A device for measuring the flow rate of a fluid fluid as hot water is shown in Figures 1,2,4,7 and 11 and is indicated everywhere by heading 10.

As shown in part in FIG. 1, the device according to the invention includes two ultrasonic sensors T, and T ₂ , located in the stream and at a distance from each other in the direction of the flowing fluid, so as to collect fluid velocity information.

In FIG. 1, the sensors T, and T ₂ are arranged opposite each other at opposite ends of the measuring tube 12, in which the fluid flows in the direction indicated by arrow F.

Another example of the location of the sensors T, and T ₂ is shown in Figure 2, where the sensors are located on the back wall of recesses 14 and 16 that are perpendicular to the direction of the flowing fluid indicated by arrow F.

The fluid flows through a measuring tube 18 in which two mirrors 20 and 22 are used to reflect the ultrasonic signals, as shown in FIG. 2.

The ultrasonic sensors T, and T ₂ are triggered by an excitation signal coming from the sequence sensor 24 shown in Fig. 3. This sensor includes a 165 bit counter 26, a decoder 28 connected to the counter, and a node 30 forming a plurality of logic blocks.

A 1 MHz chronometric signal separated by a 4 MKz chronometric sig10 wave feeds the counter 26 and the node 30, which also receives a TE signal emitted by the decoder 28, and makes it possible to emit an ultrasonic signal. At its output, node 30 transmits an actuation signal SE, which acts as a pilot signal. Counter 26 is activated when the RAZ reset signal is supplied by a standby clock not shown in FIG.

As shown in FIG. 4, the SE signal serving to activate sensor T is transmitted 20 days to the respective inputs of two NAND logic units 32 and 34 connected in parallel to reduce the internal impedance of the circuit.

The other input of each of the NAND logic blocks 25 is connected to a logic signal of value 1. These blocks can be replaced by inverters.

The outputs of the two logic units 32 and 34 are connected to a capacitor C ,, connected to a resistor R ,, which resistor R is connected to another resistor R ₂ , which is connected in parallel with the terminals of the sensor T.

The terminal of the sensor T, which is connected to resistors R, and R ₂ , is also connected to a 35% resistor 1% receiving electrical current coming from the collector of the switching transistor 36.

This PNP switch 36 is powered by V _dd from its emitter. By sequentially connecting resistors R ₂ and R _{3, it} is possible to obtain a steady voltage for sensor bias, with this voltage equal to _µm .

Capacitor C isolates the voltage V _dd from the input (where the SE signal enters) to 45 to prevent the potential of the dividing circuit Rj and R ₃ from interfering, when in particular the SE signal is at rest. This also makes it possible to avoid unnecessary consumption.

The resistor R, isolating the sensor T, from the input signal to ensure that the rectangular signal SE is compatible with the high power sensor and makes it possible to control the emission impedance better.

A symmetrical circuit is formed for the T ₂ sensor, which is actuated by the signal SE ₂ , with NAND logic units 38 and 40, resistors R ₄ , R, and R ₆ , capacitor C ₂ and transistor 42.

Since the two branches of the symmetrical circuits are not connected together, thus the good release of the connections between the two sensors is ensured.

When sensor T emits an ultrasonic signal after being triggered by an excitation signal at a frequency of 1MHz, the switch 44 key is opened and the key 46 connected to the T ₂ sensor is closed.

For example, the emitted ultrasonic signal represented by letter E in FIG. 5 may have a duration equal to 40 ps.

Approximately 80 ms after the moment when the emission of the signal begins, the ultrasonic signal is received by the T ₂ sensor (Fig. 5b).

The received signal represented by the letter R in FIGS. 5a and 5b is conditioned in the inverter 48 (FIG. 4), for example a CMOS inverter of the HCO4 type containing 3 inverters arranged in a cascade transmitting a SIG square wave signal, as shown FIG. 5a.

In one embodiment, the conditioning may be performed with a differential comparator whose first input receives the signal coming from the switching device and its other input receives a base signal, coming from a specialized divider or from an RC network that sets the average value of the signal.

As shown in FIG. 6, the device 10 comprises means 50 for generating four time-lapse signals SK, such as i = l to 4.

These means include a quartz generator 52 with a frequency of 4 MHz. The generator transmits a timed signal, which is transmitted to the timed inputs of the SC inputs to two D-type tritters 54 and 56, which form a divider. The waveform of the chronometric signal at a frequency of 4 mHz is shown in Fig. 7.

The output Q of the triter 56 is connected to the input D of the triter 54, and the output Q of the triter 54 is connected to the input D of the triter 56.

As shown in FIG. 7, assuming that the signal CK ₂ is 0 and the signal CK ₄ is 1, when the raised end of the timed signal with 4 MHz comes, the timed signal CK delivered from the output Q of the triter 54 is reversed of 1 and the input D of the triter 56 thus also receives a value of 1.

The stopwatch signal CK ₃ supplied by the output Q of the gauge 54 thus becomes 0.

At the next elevated end of the 4 MHz timing signal, the timed signal SK ₂ transmitted from output Q of triter 56 becomes 1.

Thus, the timed signal CK ₄ supplied from the output Q of the triter 56 becomes 0 and the input D of the triter 54 thus also receives a value of 0.

At the next raised end of the 4 MHz timing signal, the timed signal CK returns to 0, while the CK ₃ signal becomes 1, and thus the input D of the triter 56 also becomes 0.

When the next raised end of the 4 MHz timing signal comes, the timed signal CK ₂ delivered from the output Q of the triter 56 becomes 0 and the signal CK ₄ thus becomes 1, bringing the input of D of the triter 54 to state 1. In another the raised end of the timed signal with 4 MHz the timed signal SK becomes 1, the timed signal SK ₃ becomes 0 and the input D of the triter 56 becomes 1. The next raised end of the timed signal with 4 MHz causes the timed signal SK ₂ to become 1 and thus way the timed signal SK ₄ , and the input D of the three 54 - to become 0.

The four timed signals CK, CK ₂ , CK ₃ and CK ₄ are shown in bold in Fig. 7.

These signals have the same frequency (1MHz) as the excitation signals SE, and SE ₂ to activate the sensors that the excitation signals are generated based on the timed signal SK. The timed signals are phase shifted relative to each other by π / 2 and are in constant phase connection with the excitation signals for the actuation of the sensors.

In addition, the signals have phase transitions between logic value 0 and logic value 1.

In one embodiment, the loop loop 50 consists of forming a chronometric signal SK, and 1 MHz based on a 2 MHz timed signal generated by a generator and with

using a D-type triter.

The CK ₂ signal is then formed on the basis of the CK signal by creating artificial restraint, for example by means of a monostable loop (or time-delayed loop), and the CK ₃ and CK ₄ signals are easily obtained based on the CK ₍ and CK signals). ₂ by inverting them.

As shown in Fig. 3, a synchronizing signal ERS is generated through the decoder 28 of the sequence sensor 26 and its waveforms are shown in Figs. 5 and 5a.

Its logical value is 0 and after a time interval equal to 95 ms, its value becomes 1 when the received signal is located in its central region, which is more difficult to disturb than the beginning or end of said received signal. This signal triggers the start of the step in which a timed signal CK _D is selected

Figure 6 shows that the ERS signal is sent to the input D of D-type 58. This shaker is capable of generating an ERSS signal at its output Q, which corresponds to the ERS signal synchronized with the timed signal CK _p which is sent to the timed input SK of the Titer 58.

The SK signal! was chosen at random.

The ERE signal is generated from the decoder 28 of the sequence sensor 26 (Fig. 3) and its waveform is shown in Fig. 5b.

Its logic value is 0 and 2, ms, after the ERS signal becomes 1, its value becomes 1. The signal triggers the start of the measurement step.

Figure 6 shows that the ERE signal is sent to the input D of the D-type gauge 60, whose input return to zero C (pure) is connected to the signal R, which restarts it at the beginning of the measurement.

The output Q of the trie 60 is connected to one of the inputs of the logic block 62 of the NOR type and the other input receives the ER SS signal.

The output of this block 62 is connected to an inverter 64 whose output is connected to one of the inputs of a logic block 66 of the NOR type and its other input receives a 4 MHz timed signal.

The C4M signal at a frequency of 4 MHz is transmitted to the output of this block 66. The C4M signal is re-fed to the timer63231 early input SK of the triter 60. The C4M signal is triggered by the ER SS signal which is 0 and is interrupted. when the ERE signal that is synchronized with the C5M signal C4M appears.

It should be noted that this logic loop limits the presence of the C4M signal, in particular at the inputs of the treatment SCs 60 and 70, thus minimizing the energy consumption of the circuit (Fig. 8c).

The output of Q of the triters 60 transmits an ERES signal that corresponds to the ERE signal synchronized with the C4M signal and whose waveform of a new shape is shown in FIG. 8s. This signal serves to activate the measurement node described below.

The synchronized ERSS signal is transmitted to the C input of the D-type triter 68. The SIG20 signal (SIG, or SIG ₂ ) is transmitted to the timed input CK of this triter whose D input is 1.

The output Q of the triter 68 is connected to the input D of the D-type triter 70.

The C4M signal is transmitted to the timer input SK of the triter 70, and the input C is connected to a signal RG whose task is to initialize the triter at the beginning of a complete measurement cycle, which consists of emitting an ultrasonic signal in the direction of fluid flow called a "downstream signal" and by emitting a signal in the opposite direction called an "upstream signal".

When the ERSS signal at output Q of triter 58 becomes 1, the first raised end of the conditioned signal SIG, (or SIG ₂ ) forces the output Q of triter 68 to become 1, thereby allowing the output Q of triter 70 to become 1 at the first raised end of C4M signal.

The received SIG _U signal corresponds to the C4M synchronized signal SIG _r To obtain the SIG _ls signal which is 45 phase shifted relative to the SIG _P signal it is possible to replace the Titer 70 with four logic inverters arranged in sequence at the output Q of the Titer 68 .

The ERSS signal is also transmitted to the input50 to D of the D-type triter.

The input C of the grating 72 receives the indicated signal RG.

The stopwatch timing signal SK of the tritter 72 is coupled to the signal SIG _ls .

The stopwatch timing signal SK of the tritter 72 is connected to the signal SIG _ls .

The common signal SIG _ls is also transmitted to one of the inputs of logic block 74 of the NAND type, the output of which is directed to an inverter 75, which transmits the signal SIG _ls to the D inputs of four D-type jitter 76, 78, 80, 82.

The input C of each triter is connected to the output Q of the triter 72.

When the ERSS signal is at 1, the first raised end of the SIG _ls signal triggers the gauge 72 and causes its output Q to become 1.

The first raised end of the SIGls, which appears after the ERSS has become 1, misses the C inputs of the four three 76,78,80 and 82.

Another four D-type triters 84, 86, 88, 90 receive the corresponding outputs Q of the triters 76,78,80,82 at their timing inputs SK.

The inputs D of the trimmers 84, 86, 88, 90 are permanently set to 1 and their C inputs are connected to the common starting signal RG.

The outputs Q of the triters 84 to 90 are connected to the corresponding four logic blocks 92, 94, 96 and 98 of the NAND type, the other inputs of these blocks receive the corresponding chronometric signals CK, CK ₂ , CK ₃ , and CK ₄ . The outputs of logic blocks 92 to 98 are connected to the corresponding four inputs of logic block 100 of type NAND.

The outputs Q of the trimmers 84 to 90 are connected to the corresponding four inputs of a logic block 102 of the NAND type, the output of which is inverted through a logic inverter 104 and then re-fed into the second input of the logic block 74.

Each time a raised SIG _ls signal is identified (such an end can be considered as constituting a portion of the signal characteristic), from the four tritters 76, 78, 80, 82, they are activated and receive the corresponding chronometric CK signals, , CK ₂ , CK ₃ , CK ₄ at their timekeeping inputs CK.

The total signal RG is at 1 (start at the beginning of the measurement), the triters 84 to 90 become active and thus they become sensitive to the outputs Q of the triters 76, 78, 80, 82.

The first transition or the raised end of the first chronometer signal, which comes immediately after the appearance of the raised end of the SIG _ls signal, triggers the output Q of the timer signal timer.

The trimmers 76, 78, 80, 82 make it possible to identify the raised end of SIG _ls and to select the first transition of the timed signal CK, which occurs immediately after the appearance of the raised end. For example, if CKj is the selected chronometer signal, since it is closest to SIG _ls then this signal selected by the triter 80 forces the output Q of the triter to be 1 and through it the output Q of the corresponding triter 88 to become 1.

The outputs Q of the other triters 76, 78 and 82 are always 0.

The output Q of the triter 88 is then 0 and causes the output of the logic block 102 to become 1. The inverted signal supplied to the second input of the logic block 74 is then 0, thus closing the block by inverting the common output signal from the block and the connected interfaces. your inputs D on the triters 76 to 82 to 0.

In this way, the triters 76 to 82 become insensitive to the timed signals CK] and the outputs of the triters remain 0.

This makes it possible to prevent other timed signals from being selected and thus the selected timed signal CKj is stored.

Since the output Q of the triter 88 is at 1, the signal CK ₃ is output from the logic block 96 and is fed to one of the four inputs of the logic block 100. The other inputs of this block 100 are at 1 due to the zero state of the outputs Q to the triters 84, 86 and 90 and therefore the block 100 transmits the signal CK ₃ which is hereinafter referred to as CLS. The CLS signal corresponds to the timing signal selected from the circuit described.

Because the SIG signal is synchronized with the C4M signal, it is possible to prevent the edges of the SIG _ls and CLS signals from occurring simultaneously.

With the variant shown in Fig. 8a, the functions of identifying the raised end of one period of the SIG _1a signal and selecting the first transition (elevated end) of the timed signal SK that appears immediately after the appearance of the elevated9

z /

// this end of the SIG _ls signal period can also be implemented as follows: the common SIG signal] is transmitted to one of the inputs of each of the four AND logic blocks 101, 103, 105, 107 and each of the CK signals is fed to the input of the respective monostable circuit 106, 108, 109, 111, the output of which is connected to the other input of the respective of the four AND logic blocks 101, 103, 105, 107. The outputs of the four AND logic blocks are transmitted to the stopwatch SC inputs from the corresponding four storage tars 84, 86, 88 and 90.

In FIG. 8b shows an embodiment of the device of FIG. 6. In this embodiment, a D-type triteric phase 84-90 is omitted. Only those elements which are different from the elements of FIG. 6 are shown.

The common signal SIG ^ wniSIGj ,, coming from the Q output of the triter 70 is transmitted to the D inputs of four D-type triters 300, 302, 304 and 306 and to the timing input SK of the D-type triter 308 whose output Q is connected with the C inputs of the indicated triverters 300-306.

The D-type Triter 310 receives the ERSS signal at its timing input, its D input is constant at 1 and its Q output is transmitted to the respective of the two inputs of each of the four AND logic blocks 312, 314, 316, 318, the other input of each from these blocks receives the corresponding of the chronometric signals SK _P SK ₂ , SK ₃ , SK ₄ .

Thus, when the ERSS signal becomes 1, the output Q of the triter 310 becomes 1, thus omitting the timed signals SK. After half a period of the C4M signal, the raised end of the SIG _ls signal comes at the inputs D of the triters 390-306 and at the same time activates the inputs C of these triters through the triter 308.

The first raised end of the timed signal CK, for example CK ₃ , which immediately follows the raised end of the SIG _U signal, activates the corresponding D-type triter 304 whose output Q becomes 1.

Since each of the outputs Q of the tritter D 300-306 is sent to the input of the corresponding NAND logic block 320, 322, 324, 326 and since the other input of each block receives a corresponding different signal SK., Such as i "l to 4, the output Q of the triter 304, becoming 1, omits the signal CK ₃ from the logic block

324, which signal is sent to the corresponding of the four inputs of the NAND logic block 328.

The other three inputs of block 328 are connected to the outputs of blocks 320, 322 and 326, so that the signal SK ₃ passed through block 324 goes to the output of block 328.

The outputs Q of the 300-306 triters are connected to the corresponding four inputs of the NAND logic block 330, the output of which is sent to a logic inverter 332, which is connected to the input S (set) of the RS-type triter 334.

The output Q of the triter 334 is applied to the input C of the triter 310 and the input C of the triter 334 receives the restart signal RG, which is produced every two measurements (after the downstream and downstream signal).

Thus, since the output Q of the triter 304 becomes 1, the output Q becomes 0, the output of the block 330 becomes 1 and the input S of the triter 334 is thus 0, forcing the output Q of the triter 334 to become 1 and forcing its output Q to become 0.

As a result, the input C of the triter 310 becomes 0 and the output Q becomes 0, thereby blocking logic blocks 312-318. RS triter 334 thus blocks the selection of the timed signal and the timed signal CK ₃ (CLS) selected by the timer 304 is thus stored in the timer 304.

This option makes it possible to reduce the power consumption of the device because the CK signals are not sent directly to the Clock inputs of the 300-306 CK grinders.

Figures 9 and 10 illustrate the generation of an SIG _ls CLS signal, denoted as ΙΕΧρ, which is formed on the basis of an integer m the number of consecutive periods of the SIG signal _r

The IEX signal is in the form of m square pulses, at which the width of each pulse corresponds to the interval between the moment when the characteristic portion of the signal period SIG _t appears, such as its raised edge, and the moment at which the first transition of the next CLS signal, for example the raised end of that signal (Fig. 10).

For example, the number m may be equal to 16 so as to reduce the noise accompanying the measurements and to perform a mediation function.

When the output Q of the triter 60 (Fig. 6) becomes 1, the ERES signal allows the D-type of the triter 110 (Fig. 9) to activate the selected CLS timing signal at the timing input SK of the triter 110.

The input C of the triter 110 is connected to the restart signal R, which is activated at the beginning of each measurement.

At the raised end of the CLS signal (Fig. 10), the output Q of the triter 110 becomes 1, forcing the output Q of the triter to become 0 and thus releasing the restart input of the 16-bit counter, 112, for example from the HC4040 type, which starts counting 16 pulses. The output Q5 of counter 112 becomes 1 at the beginning of the sixteenth pulse and the opposite of this signal is transmitted to the input C of the D-type of triter 114.

The output of Q of the triter 110 is connected to the timing input SK of the triter 114, whose D input is constant at 1, and the output Q of the triter 110 becomes 1, forcing the output Q of the triter 114 to become 0.

Output Q of the Triter 114 is transmitted to an input from the NAND logic block 116, whose other input is constant at 1 and whose output is connected to the D input of the D-type Triter 118.

As the Q of the triter 114 becomes 0, the input D of the triter 118 becomes 1 (Fig. 10).

The first raised end of the SIG signal, which comes to the timer input SK of the triter 118 after the D input is set to 1, forces the output Q of the triter to become 1 (Fig. 10).

The output Q of the triter 118 is connected first to the input D of the triter 120 and secondly to the input C of this triter and to one of the inputs of the NAND logic block 122, the output of which is applied to the timing input SK of the counter 112. The output Q of the triter 120 is connected to the input C of the triter 118. When the output Q of the triter 118 is 0, the block 122 receives a logical signal of value 0 at one of its inputs and the output of this block is thus 1.

As soon as the output Q of the triter 118 becomes 1, the output of block 122 becomes 0 and the resulting dropped end triggers the counting of the first pulse from counter 112.

At the same time, the output Q of the exchanger 118, which was at 1, becomes 0 and thus forces the output of logic block 124 to become 1.

As soon as the elevated end of the selected CLS timed signal reaches the timed output SK of the triter 120 (Fig. 10), the output Q of this triter becomes 0, thereby forcing the output Q of triter 118 to become 0.

As a result, the signal coming from the output Q of the triter 118 becomes 1 and the first signal impulse IEX1 is formed (Fig. 10).

Thus, in the same way, sixteen consecutive impulses are formed.

Similarly, the appearance of the sixteenth consecutive raised end of the SIGI signal causes the signal at the output of logic block 122 to become 0, thus activating the counting of the last pulse from counter 112.

The output signal from output Q of the counter 118 thus also becomes 0. The appearance of the sixteenth dropped end at the timer input of counter 112 causes the output Q5 of this counter to become 1 and thus the reverse output to become 0, thereby blocks NAND of block 122.

As a result, the signal at the output of logic block 122 returns to 1 (Fig. 10), thus stopping the counting. The input C of the triter 114 becomes 0, thereby forcing the output Q of the triter 114 to become 1 and thus the input D of the triter 118 to become 0, thereby blocking this triter.

When the next elevated end of the selected CLS timer signal appears at the timer input SK of triter 120, its output Q becomes 0, forcing the output Q of the triter 118 to become 1 and form the sixteenth pulse of signal ² EX, (Fig. 10 ).

The next step is to determine the time t, which corresponds to the sum of the intervals of each period of these sixteen pulses of the SIG signal, between the moment when the raised end of said signal appears and the moment when the first raised the end of the CLS signal that comes immediately after.

This step consists of determining the sum of the widths of the sixteen pulses formed (Fig. 11), with only three of the pulses shown in Figs. 11.

FIG. 12b is a simplified schematic view of a time expander. Vremeekspanderat is useful due to the small widths of the pulses of the signal 1EH _p and such widths is impossible to determine by conventional means, for example means for counting the pulses, which would require a clock and a counter with a very high frequency.

The width of each of the pulses of the 1EX _P signal obtained from four chronometric signals may, for example, represent a unit of time, approximately in the range of 130 ns to 375 ns.

As shown in Figure 126, the signal ΙΕΧρ represented by a voltage Ve, which can accept logic values 0 and 1, is transmitted to the current generator G _{| (} transmitter current 1p This generator is connected to point A through one of its terminals. Capacitor C , for example, with a capacity of 22 nF, is connected through one of its plates to point A, and the voltage Uc between the capacitor terminals is applied to the opposite input of an AO operational amplifier used as a comparator.

The non-inverting input of this AO comparator accepts a reference voltage V _R (for example + 1.5 V).

The comparator is powered by a voltage V ^ (eg 3.3 V).

The output of the comparator AO is connected to an actuating logic inverter IL, the output of which is sent to a second current generator G ₂ , which supplies current 1 ₂ . The second generator is energized and connected to point A through one of its terminals.

When the voltage Ve is 0 (Fig. 12a), the current I is zero, the voltage Uc between the capacitor terminals remains greater than the reference voltage V _R , the comparator output VAO is zero, the output of the inverter IL is 1 and the current 1 ₂ is zero.

When the voltage Ve is 1 (Fig. 12a), the current I is equal to, for example, 3mA and the capacitor C is diluted to a certain value Uc lower than V _R at which the value of the voltage Ve again becomes zero.

Then the output voltage VAO reaches its maximum value (for example equal to 2.8 V) and the output voltage of IL becomes 0, thus making it possible to recharge the capacitor with a current of 1 ₂ , whose value is approximately equal to 3 μΑ to a value, which is higher than the voltage V _R , then the value of the voltage VAO returns 5 to zero (Fig. 12a), the output voltage of IL becomes 1 and 1 ₂ again becomes zero.

Provided that I ₁ t _e = I ₂ T _s -CU _c = koHCTaHTa, the ratio I, / I ₂ can be deduced, which is equal to, for example, 1000, such as 1 = 3 mA and Ι ₂ = 3μΑ. 10 Thus T L = 1000.

Therefore, for any width or length t. of the pulse at the output of the comparator is obtained extended time T _at which time can be determined konventsional15 but in order to put the width t _e = T, / 1000.

The time T _s, for example, is determined by the resistance of the resistor R ₁₀ in the circuit shown in FIG. 13.

The contour shown in FIG. 13 is an example of a circuit performing the described extension function.

The circuit includes a resistor R7 through which the signal 1EH ₍ (Figs. 9 and 10) connected to point B passes, to which 25 diodes D1, connected in series with resistor R8 and secondly to NPN transistor 130, are connected first.

The emitter of the NPN transistor is connected to ground by resistor R9, while the collector is connected to point C.

The logic level 1 of the IEX signal determines potential B in the network R7, DI, R8, to which the base of transistor 130 is subordinated. Thus, the current is actually determined by the formula i = (V _B -V _{b <} .) / R9 , where Vbe shows the voltage base - emitter of the transistor 130, i. about 0.65 V.

Capacitor C3 is connected via one of its plates to point C and with the inverting input of the comparator 132, powered by a forcing 40 V ^, the inverting input of the comparator is subject to a reference voltage V _R.

The output is transmitted first to a timer connected to a microprocessor not shown in the drawings and second to a resistor R10.

Resistor R10 is connected to point D, to which also diode D2, connected in series with resistor R11, and secondly to transistor 136, are also connected.

The emitter of this PNP transistor 136 is connected to resistor R12 while the collector is connected to said point C.

The circuit is supplied with voltage V _dd . The contour works as described above in FIG. 12a and 12b.

The current generators G1 and G2 shown in FIG. 126 are respectively replaced by transistors 130 and 136, while diodes and resistors connected in series to each other are added to each of the transistors so as to compensate for the temperature drift of the emitter / base diodes of the transistors.

Thus, by extending the time corresponding to the sum of the widths of the sixteen pulses of the IEX signal, the time t is obtained, which is a characteristic of the propagation of the ultrasonic signal emitted by the sensor T to the sensor T ₂ , the latter located in the direction of flow (Fig. 1).

About 40 ms after the start of the signal emission from the sensor T, a restart signal R is generated to restart the logic nodes for signal generation ² EX.

The T ₂ sensor then emits an ultrasonic signal to the T sensor / by actuating from a SE ₂ triggering signal at a frequency equal to 1 MHz and generated by the sequence sensor 24.

The switching unit controlled by the microprocessor is switched on so that switch 44 opens and switch 46 closes.

The sensor T ₍ receives the ultrasonic signal which has propagated from the downstream to the upstream end of the stream about 90 ms after the moment when the emission starts, and the signal is conditioned by an inverter 48 to receive the waveform SIG ₂ which has the waveform shown in Fig. 5a.

The assembly of FIG. 6 remains activated in the state it was when the timed CLS signal was selected and thus the node transmits the CLS signal.

The SIG ₂ signal is synchronized with the C4M signal to generate the SIG ^ signal.

The SIG ₂ signal is transmitted to the timer input SK of the trimmer 118 (Fig. 9), while the selected CLS timed signal is transmitted to the timed inputs SK of the trimmers 110 and 120. Part of the SIG ₂ signal is selected from the ERES signal that triggers the input D of the assembly 110. The assembly of FIG. 9 operates as described for the formation of the signal 1EX _P and thus generates the signal 1EX ₂ .

The IEX, and 1EX ₂ signals are shown in FIG. 14.

They are shown on top of each other for convenience, but obviously they do not spread simultaneously over time.

Then, the signal EXE ₂ is triggered via the time-extension circuit shown in FIG. 13, as described above.

The time t ₂ characteristic of the propagation of the ultrasonic signal emitted by the sensor T ₂ to the sensor T _p is determined as described above for the time t.

Then the microprocessor calculates the difference between these times t ₂ -t, and then - the flow rate of the liquid fluid Q, which is proportional to this difference, is deduced from the following formula: Q = K (t2-tl) / C, with K being the coefficient taking into account the geometry of the meter and C being the correction factor related to the speed of sound propagation in water.

The flow rate Q can also be calculated by the formula Q = 2LS (t ₂ -t,) / (t, -t ₂ ) ² related to the geometry of FIG. 1, with L and S being the length of the pipe and the cross-section of the pipe, respectively.

At L = 10 cm, S = cm ² and t _t + t ₂ = 160 ps, Q = 1406 1 / h.

One advantage is that the CLS signal is a temporary time reference that is used as an intermediate reference to determine the times t, and t ₂ .

This reference is later disregarded in determining the difference t, -t ₂ , which difference gives the desired measurement base.

In this method, it is not necessary to reconstruct the signal phase in order to determine the propagation time of said signal, the process being cheaper in terms of energy intensity.

The method is more flexible than the known ones because it creates a time reference and therefore does not need to take into account the signal emitted.

The method according to the invention is reliable because it is digital and therefore gives very high measurement accuracy.

At a 1 MHz emission frequency, the propagation time of the ultrasonic signal is approximately in the range of 70 ms to 80 ms and the phase rotation of the emitted signal varies in the range of 140 to 160 π.

For example, if the top-down propagation time is 70 ps, which corresponds to a 140 π phase rotation, then the bottom-up propagation time may be 70 ps + 500 ns and the corresponding phase rotation is equal to at 140 π + π for maximum water flow.

For household water measurement, the maximum flow rate, for example, is 2 m ³ / h for a pipe 12 with a diameter of 10 mm.

This means that in this case the difference between the extended times t ₂ -t is equal to 500 ns, which corresponds to a phase shift with π.

Four time-lapse CC signals, as described above, are sufficient to determine the difference between the times t ₂ -t, equal to 500 ns, with minimum energy consumption.

When the phase difference is greater than π, it is important to increase the number of timed signals.

It is possible to increase the number of timing signals SK to increase the dynamic range when measuring flow, but the energy consumption will be higher.

By modifying the frequency of the ultrasonic emission, it is possible to either increase the measurement accuracy and thus to reduce the dynamic measurement range (increase the frequency) or to increase the dynamic measurement range, but with a lower accuracy. measurement (lower frequency).

A second embodiment is shown in FIG. 15 and is described below.

As shown in FIG. 15, the measuring device comprises means 200 for generating eight time-lapse signals CK, such as "l to 4." FIG. 16 shows the waveforms of the generated signals SK.

These means include a quartz oscillator 202 with a frequency of 8 MHz. This generator transmits a timed signal that is applied to the timing inputs of the SKs on four D-type trimmers 204, 206, 208, 210, forming a divider.

The output Q of the triter 210 is connected to the input D of the triter 204 and the outputs Q of the triters 204, 206 and 208 are connected to the inputs D of the respective triters 205, 208 and 210.

If it is assumed that the signal CK ₄ is 0, 5 when the raised end of the timed signal with 8 MHz comes, then the timed signal CK, transmitted through the output Q of the triter 204, becomes 1 and the input Q of the triter 206 thus also accepts value 1.

The stopwatch signal CK ₃ transmitted via the output Q of the gauge 204 thus becomes 0.

At the next raised end of the 8 MHz clock, the CK ₂ timed signal transmitted through the output Q of the triter 206 becomes 1.

Thus, the timed signal CK ₆ transmitted through the output Q of the triter 206 becomes 0.

The next elevated end of the 8 MHz clock signal causes the chronometer signal CKj transmitted through the output Q of the triter 208 to become 1, while the chronometer signal CK transmitted through the Q output of the triter becomes 0.

The next elevated end of the 8 MHz clock signal causes the chronometer signal CK ₄ transmitted through the output Q of the triter 210 to become 1, thereby forcing the chronometer signal CK transmitted via the Q output of the triter to 0 and thus the input D of the gauge 204 also takes the value 0.

At the next raised end of the 8 MHz clock signal, the CK timed signal returns to zero while the CK ₃ signal becomes 1, and thus the input D of the triter 206 also becomes 0.

When the next raised end of the 8 MHz timing signal comes, the timed signal CK ₂ transmitted through the output Q of the trimmer 206 becomes 0 and the signal CK ₆ thus becomes 1.

When another raised end of the 8 MHz clock signal arrives, the CK ₃ transmitted timer signal transmitted through the triter 208 becomes 0, and the CK time signal thus becomes 1. _z

The subsequent elevated end of the 8 MHz clock signal causes the time clocked signal CK ₄ to become 0 and the time-honored signal CK to become 1, thereby forcing the input D of the triter 204 to become 1.

At another raised end of the 8 MHz clock signal, the CK time signal becomes 1 and the CK ₅ time signal thus becomes 0. A further elevated 8 MHz clock signal causes the CK ₂ time signal to become 1 and thus force the timed signal SK ₆ to become 0.

The next erect tap of the 8 MHz clock causes the chronometer signal SK ₃ to become 1 and the timed signal SK to become 0.

At the next elevated end of the 8 MHz clock signal, the timed signal SK ₄ becomes 1 and the timed signal SK ₈ becomes 0, thereby forcing the input D of the triter 204 to become 0.

Thus forming eight clock signals CK ,, CK _2, CK ₃ SC _4, SC _5, SC _6, CK, and CK ₈ .These signals have the same frequency as the excitation signal SE ₃ SE and ₂ for actuating the transducer ( 1 MHz), which excitation signals are generated, for example, on the basis of the timed signal CK _D The signals are phase shifted by π / 4 and are in constant phase relation to the excitation signals of the sensors.

In addition, these signals have transitions between logic value 0 and logic value 1.

As shown in FIG. 3, an ERS synchronization signal is generated through the decoder 28 of the sequence sensor 26 and its waveform is shown in Figures 5 and 5a.

Its logical value is 0 and after a certain time interval equal to 95 ms, its value becomes 1 when the received signal is in its central region, which is less disturbed than the beginning or end of the received signal. This signal triggers the start of the phase in which a timed signal SK is selected.

According to FIG. 15 signals · The ERS is transmitted to the input D of the D-type shaker 212. This triter is able to generate at its output a Q signal ERSS, which corresponds to the ERS signal synchronized with the timed signal SK, which is transmitted to the timing input SK of 212 trits.

The SK signal is selected at random.

An ERE signal is generated through the decoder 28 of the sequence sensor 26 (Fig. 3) and its waveform is shown in Figs. 56. Its logical value is 0 and 2 ms, after the ERS signal becomes 1, its value becomes 1. This signal triggers the start of the measurement step.

According to FIG. 15, the ERE signal is transmitted to the input D of D-type triter 214, whose C (clean) input is coupled to the signal R, which restarts it at the beginning of the measurement.

The output Q of the triter 60 is connected to one of the inputs of logic block 216 of the NOR type, with the other input receiving an ERSS signal.

The output of this block 216 is connected to an inverter 218 whose output is connected to one of the inputs of a logic block 220 of the NOR type, with the other input receiving the 8 MHz timed signal.

The 8 MHz C8M signal is transmitted at the output of block 220. The C8M signal is reintroduced into the timer input SK of the triter 214. The C8M signal is triggered by the ERSS signal, zeroing and holding when the ERE synchronized signal appears. through the C8M signal.

Output Q of the triter 214 transmits an ERES signal that responds to the ERE signal synchronized with the C8M signal. This signal is used to activate the measuring node.

The synchronized ERSS signal is transmitted to the input C of a D-type triter 222. The SIG signal (SIG, or SIG ₂ ) is transmitted to the timing input SK of that triter whose input D is at 1.

The output Q of the triter 222 is connected to the input D of the D-type triter 224.

The C8M signal is transmitted to the timing input SK of the triter 224 and the input C is connected to the signal RG, which aims to start the triter at the beginning of the full measurement cycle.

When the ERSS signal at the output Q of the triter 212 becomes 1, the first raised end of the conditioned signal SIG, (or SIG ₂ ) forces the output Q of the triter 222 to become 1, thus allowing the output Q of the triter 224 to become 1 at the first raised signal end C8M.

The resulting SIG _ls signal corresponds to the SIG signal synchronized with the C8M signal.

//

/

The ERSS signal is also transmitted to the D input of the D-type triter 225.

Input C of Triter 225 receives the signal RG described above.

The common signal SIG _(J is also transmitted to one of the inputs of a logic block 226 of the NAND type, and whose output is directed to an inverter 227, which transmits the inverted signal to the D inputs of eight D-type trimmers 228, 230, 232, 234, 236, 238, 240, 242.

The input C of each triter is connected to the output Q of triter 225.

When the ERSS signal is at 1, the first raised end of the SIG _ls signal triggers the gauge 225 and forces its output Q to become 1.

The first raised end of SIG _ls , which occurs after the ERSS becomes 1, unlocks the C inputs of the eight triters 228 - 242.

The other eight D-type triters 244, 246, 248, 250, 252, 254, 256, 258 receive the corresponding Q inputs of the triter 228 - 242 at their timing inputs SK.

The inputs D of the trimmers 244 - 258 are permanently set to 1 and their inputs C are connected to the common starting signal RG.

The outputs Q of the 244 - 258 triters are connected respectively to eight logic blocks 260, 262, 264, 266, 268, 270, 272 and 274 of the NAND type, the other inputs of these blocks receive the corresponding timed signals CK] to CK ₈ . The outputs of logic blocks 260 274 are connected to the corresponding eight inputs of logic block 276 of the NAND type.

The outputs Q of the trimmers 244 - 258 are connected to the corresponding four inputs of a logic block 278 of the NAND type, the output of which is inverted through a logic inverter 280 and then reintroduced to the second input of the logic block 226.

Whenever a raised end of the SIG _ls signal from the eight trimers 228 to 242 is identified, they are activated and receive the corresponding timed signals CK! to SK ₈ at its stopwatch inputs SK.

The total signal RG is at 1 (start at the beginning of measurement), the trimmers 244 to 258 are activated and thus become sensitive to the outputs Q of the trimmers 228 to 242.

The first transition or raised end of the first timed signal, which comes as soon as the raised end of the signal SIG ^ appears, triggers the output Q of the timer receiving the timed signal.

For example, if CK ₅ is the selected chrono- ₅ meter signal as it is closest in time to SIG _ls , this signal selected by the triter 236 forces the output Q of the triter to be 1, also forcing the output Q of the corresponding triter 252 to become 1.

Outputs Q of the other trimmers 228 to

234 and 238 to 242 are always 0.

The output Q of the triter 252 is then 0 and thus forces the output of logic block 278 to become 1. The inverted signal 15 coming to the second input of logic block 226 then becomes 0, which blocks the block and forces the total signal output of the blocks and the connected inputs D of the trimmers 228 to 242 are zero.

In this way, the triters 228 to 242 become insensitive to the timed signals CK and the outputs Q of the triters remain at 0.

This makes it possible to prevent the selection of other stopwatch signals, and thus store the selected stopwatch signal SK ₃ .

Because the output Q of the triter 252 is at 1, the signal CK ₅ is passed from the logic block 30 268 and is fed to one of the four inputs of the logic block 276. The other inputs of this block 276 are at 1 due to the zero state of the outputs Q of the triters 244 to 250 and 254 to 258, and therefore the block 276 transmits the signal 35 CK ₃ , which is denoted below by CLS. The CLS signal corresponds to the stopwatch signal selected by the specified loop.

Since the SIG signal ₍ synchronized with the C8M signal), it is possible to prevent the edges of the SIG _t and CLS signals from occurring simultaneously.

Everything described above in FIGS. 9 to 14 remains applicable to the second embodiment of the invention described.

As an example, when using four stopwatch CK signals. with a frequency of 4 MHz and when the signal SG! is synchronized with the signal S4M using tritera 70, the signals CK ,, CK _3, S4M, SIG ,, SIG _lB and ² EXj 50 may for example have the wave forms shown in Fig. 17.

Thus, when it is necessary to measure the width of the impulse formed between the raised end of the SIG signal and the first raised end of the timed signal CK., Which appears immediately afterwards (i.e., CK ₃ in the example shown), it is observed that the width of the idulus with respect to time (flow direction signal) can be subdivided into two sections: an arbitrary first section of duration τ _ρ due to the SIG signal being synchronized with the C4M signal, such as the duration τ is in the range of 0 ns to 250 ns depending m from the relative location of the two signals SIG, and C4M; and a fixed second portion of duration τ ₂ corresponding to half the C4M signal, i.e. 125 ns.

The pulse width with respect to time is thus 375 ns.

Where it is necessary to measure the pulse width formed between the raised end of the SIG ₂ signal and the first raised end of the selected timed signal CK ₃ (signal against the flow), the pulse width with respect to time at its maximum is equal to 1 ps - ε, i.e. about 970 ns, with 1 ms representing the 1 MHz signal period and ε being the standby time, which ensures that the triters 118 and 120 of FIG. 9 work properly.

As a result, by taking the difference between the widths of the two preceding pulses in terms of time, a maximum of 595 ns is obtained.

When using eight chronometric CK signals. at 8 MHz, the pulse width obtained with respect to the time against the signal against the flow is still the sum of two times τ, and τ ₂ , noi, then lies in the range of 0 ns to 125 ns (due to the synchronization with the C8M signal) and m ₂ equals 62.5 ns (which corresponds to half the C8M signal), thus setting the maximum pulse width with respect to time at 187.5 ns.

The width of the received pulse with respect to the time for the flow direction signal remains unchanged (970 ns) and the maximum difference between the two times is then 782.5 ns.

This corresponds to an increase in the dynamic range of the measuring device by 1.3 (= 782.5 / 595).

For example, if the flow limits covered by a four-stop measuring device are from 0 to 1500 Ι / h, then the eight-stop measuring device makes it possible to cover the limits up to 1950 1 / h.

It should be noted that in order to increase the dynamic range of the measuring device using at least four timed signals, it is possible to replace the logical delay corresponding to time τ ₂ with a much smaller hold, which is also compatible with the logic circuit technology used. For example, this time can be obtained by a cascade of inverters or by an RC circuit followed by an actuator circuit.

In the invention, an average of five cycles (one cycle corresponds to upstream and downstream signals) is sufficient to obtain a resolution of 50 ps.

Claims (26)

1. A method for measuring the flow of a fluid fluid, which consists in forcing two ultrasonic signals to propagate sequentially in opposite directions between two ultrasonic sensors spaced apart from each other, in the direction of the fluid flow ', as each sensor receives the corresponding ultrasonic signal SIG ,, SIG ₂ , characterized in that it includes the following steps: formation of η chronometric signals SK., such as i = 1 to η and η> 4, which signals include phase transitions, are phase shifted 2 π / η, in constant dependence with a with respect to the excitation signal for the activation of the sensors and are of the same frequency as the excitation signal; selecting a portion of the characteristic period of a first received SIG signal received from one of the propagation directions; selecting the first phase transition of the timed signal, which occurs immediately after the occurrence of the specified feature region; storing the timed signal designated CLS; determining the time t ₍ corresponding to the sum of the times elapsed between the moment at which the feature section of each of the m periods of the SIG signal _P (the integer m of consecutive periods) appears and the time at which the first occurs phase transition of the next CLS signal; identification of the same characteristic section at m consecutive periods of a second received SIG ₂ signal received from the reverse propagation direction; determination of time t ₂ corresponding to the sum of the times elapsed between is the portion of the characteristic of each of the S periods of the SIG ₂ signal, and the moment at which the first phase transition of the next CLS signal occurs; reading the difference / t ₂ -t, /; and hence the velocity of the flowing fluid Q, which is proportional to / t ₂ -t, /. 2. The method of claim 1, wherein m has a value of one. 3. The method of claim 1, wherein sh has a value other than one, and the period from which the feature region is selected corresponds to the first of m successive periods of the first SIG signal received. 4. The method of claim 1, wherein m has a value other than one, and the period from which the feature region is selected precedes m successive periods of the first received signal SIG _P A method according to any one of claims 1 to 4, comprising the conditional reception of SIG signals and SIG ₂ in the form of rectangular wave pulses. The method of claim 5, wherein the portions of the characteristic response periods of the received signals correspond to the elevated end of each pulse. A method according to claim 5, wherein the characteristic signal regions of the received signals correspond to the dropped end of each pulse. A method according to any one of claims 1 to 7, wherein the timed signals CK are in the form of square wave pulses. The method of claim 1, wherein the first transition of the CLS timed signal is a raised end. The method of claim 1, wherein the first transition of the CLS timed signal has dropped. A method according to any one of claims 1 to 10, comprising taking into account the respective SIG, - CLS and SIG ₂ - CLS differences between the signals so as to obtain the corresponding IEX] and 1EX ₂ signals that make it possible to determine the corresponding times t, Htj. A method according to claims 5, 8 and 11, wherein the signals 1EX ₍ and 1EX ₂ are in the form of rectangular pulses and which consists of extending the cumulative duration of all pulses to determine the corresponding times t ₍ and t ₂ . A method according to any one of claims 1 to 12, wherein the timed signal CK is in phase with the excitation signal to activate the sensors. A method according to any one of claims 1 to 13, comprising generating four time-honored CK signals, with i being a value from 1 to 4. A method according to any one of claims 1 to 13, comprising generating eight time-lapse CK signals, wherein ί has a value from 1 to 8. A method according to any one of claims 1 to 15, comprising forming for each received signal a signal SIG _P that is phase shifted relative to the timed signals CK. The method of claim 16, wherein the SIG _s signal is phase shifted by π / n relative to the timed signals CK. 18. A device for measuring the flow of a fluid fluid comprising at least two ultrasonic sensors (T _p T ₂ ) spaced apart from each other in the direction of the fluid flow; means for generating an excitation signal to activate the sensors; and means for receiving two ultrasonic signals SIG and SIGj emitted sequentially by the respective of said sensors in opposite directions, said device characterized in that it also contains means (52, 54, 56; 202 - 210) for forming η chronometric SC signals, such as i = 1 to η and n> 4, which signals include phase transitions, are phase shifted by 2π / η, are in constant relation to the excitation signal and are of the same frequency as the excitation signal ; means (76, 78, 80, 82; 228 - 242) for identifying a portion of the characteristic period of the first SIG _P signal received (76, 78, 80, 82; 228 - 242) for selecting the first phase transition from the timed an SK signal that appears shortly after the appearance of said characteristic region; means (84, 86, 88, 90; 244 - 258) for storing the timed signal, designated CLS; means for determining the time t, corresponding to the sum of the times elapsed between the moment in which the characteristic section of each of the m periods of the SIG signal appears (in the whole number of m consecutive periods), and the time at which the first phase transition of the next CLS signal occurs; means (76, 78, 80, 82; 228 - 242) for identifying the same feature region at m successive periods of the second received signal SIG ₂ ; means for determining the time t ₂ corresponding to the sum of the times elapsed between the moment at which the characteristic section of each of the m periods of the SIG ₂ signal appears and the moment when the first phase transition of the next CLS signal occurs; and means for reading the difference / tj-t, / and for deriving from it the velocity of the flowing fluid Q, which is proportional to / t ₂ -t, /. A device according to claim 18, wherein m has a value of one. 20. A device according to claim 18, wherein m has a value other than one, and the period from which the characteristic region is selected corresponds to the first of m successive periods of the first received signal SIG _r 21. The device of claim 18, wherein sh has a value other than one, and the period from which the characteristic region is selected precedes m the successive periods of the first signal SIG _r received _. A device according to any one of claims 18 to 21, as the means for generating the timed signals SK. include a quartz oscillator (52; 502), followed by n / 2 D-type triggers (54, 56; 204, 206, 208, 210), forming a divisor and thus creating the possibility of receiving CC signals that are mutually phase shifted to 2π / π. A device according to any one of claims 18 to 22, wherein the means for selecting the first time transition of the timing signal comprise η selectable D-type triggers (76, 78, 80, 82; 228 - 242), with the input D of each of the triggers is connected to the total received signal SIG, or SIG ₂ , the clock timing input SK of each of the triggers receives a corresponding timed signal SC, which is different for different triggers and so it is possible to activate the triggers through RAZ resetting inputs, so that when the reset RAZ inputs of the triggers are one and when the common signal is one, said triggers are sensitive to the signals. .. A device according to any one of claims 18 to 22, wherein the means for selecting the first transition of the timed signal comprise η logic blocks (101, 103, 105, 107), each of which receives the total received signal SIG or SIG ₂ through a corresponding input and η monostable circuits (106, 108, 109, 111), each of which receives a different clock signal SK. and its output is transmitted to the corresponding of the inputs of the η logic block (101, 103, 105, 107). A device according to claim 23 or 24, wherein the timing signal storage means CLS first comprise η storing D-type triggers (84, 86, 88, 90; 244 - 258), each of which receives, as a timing input SK, the output Q of a corresponding selector trigger (76, 78, 80, 82; 228 - 242) and a second NAND logic block (278) having n inputs, each of which is connected to the output Q of a respective storage trigger, such as the input D of each storage trigger is constant in unity and the first signal received at the timing input SK of one of the triggers (84, 86, 88, 90; 244 - 258) activates the function for storing by forcing the output Q of said trigger to become one and its output Q to become 0, thereby activating a blocking loop (102, 104, 74; 278, 280, 226) to block the total received signal SIG, or SIG ₂ . 26. The device of claim 25, wherein each of the n NAND logic blocks (92, 94, 96; 260 - 274) receives a timed signal SK. and the output Q of the respective storage trigger (84, 86, 88, 90; 244 - 258) through its respective inputs, the output of each block being connected to a corresponding input by a NAND logic block (100; 276) having η input, one of the η logic blocks (92, 94, 96, 98; 260 - 274) triggers the associated chronometric signal SK when the storage function of the respective storage trigger is activated.