SG87865A1 - A data bus structure for use with multiple memory storage and driver receiver technologies and a method of operating such structures - Google Patents

A data bus structure for use with multiple memory storage and driver receiver technologies and a method of operating such structures

Info

Publication number
SG87865A1
SG87865A1 SG9906251A SG1999006251A SG87865A1 SG 87865 A1 SG87865 A1 SG 87865A1 SG 9906251 A SG9906251 A SG 9906251A SG 1999006251 A SG1999006251 A SG 1999006251A SG 87865 A1 SG87865 A1 SG 87865A1
Authority
SG
Singapore
Prior art keywords
structures
operating
data bus
memory storage
multiple memory
Prior art date
Application number
SG9906251A
Other languages
English (en)
Inventor
Jay Dell Timothy
A Grundon Steven
William Kellogg Mark
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of SG87865A1 publication Critical patent/SG87865A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
SG9906251A 1999-01-29 1999-12-09 A data bus structure for use with multiple memory storage and driver receiver technologies and a method of operating such structures SG87865A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/240,647 US6347367B1 (en) 1999-01-29 1999-01-29 Data bus structure for use with multiple memory storage and driver receiver technologies and a method of operating such structures

Publications (1)

Publication Number Publication Date
SG87865A1 true SG87865A1 (en) 2002-04-16

Family

ID=22907373

Family Applications (1)

Application Number Title Priority Date Filing Date
SG9906251A SG87865A1 (en) 1999-01-29 1999-12-09 A data bus structure for use with multiple memory storage and driver receiver technologies and a method of operating such structures

Country Status (5)

Country Link
US (1) US6347367B1 (ko)
JP (1) JP2000231534A (ko)
KR (1) KR100330531B1 (ko)
SG (1) SG87865A1 (ko)
TW (1) TW457434B (ko)

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US6636980B1 (en) * 1999-08-19 2003-10-21 International Business Machines Corporation System for launching data on a bus by using first clock for alternately selecting data from two data streams and using second clock for launching data thereafter
KR100322546B1 (ko) * 2000-05-08 2002-03-18 윤종용 독립적인 전원 전압을 사용하는 메모리와 메모리 컨트롤러간의 인터페이스 시스템
JP2002007200A (ja) 2000-06-16 2002-01-11 Nec Corp メモリ制御装置及び動作切替方法並びにインターフェース装置、半導体集積チップ、記録媒体
US6590827B2 (en) * 2000-11-21 2003-07-08 Via Technologies, Inc. Clock device for supporting multiplicity of memory module types
US6510100B2 (en) * 2000-12-04 2003-01-21 International Business Machines Corporation Synchronous memory modules and memory systems with selectable clock termination
US6466472B1 (en) * 2001-04-13 2002-10-15 Giga-Byte Technology Co., Ltd. Common module for DDR SDRAM and SDRAM
US6675272B2 (en) 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
JP2003115550A (ja) * 2001-10-05 2003-04-18 Nec Microsystems Ltd 半導体記憶装置
DE10158271B4 (de) * 2001-11-28 2004-04-08 Infineon Technologies Ag Halbleiterschaltungsanordnung mit Abschlussimpedanzeinrichtung
KR100546148B1 (ko) * 2001-12-28 2006-01-24 주식회사 하이닉스반도체 범용 인터페이스를 사용하는 보드
SG126691A1 (en) * 2002-02-28 2006-11-29 Ibm Synchronous memory modules and memory systems withselectable clock termination
US6894691B2 (en) * 2002-05-01 2005-05-17 Dell Products L.P. Dynamic switching of parallel termination for power management with DDR memory
KR100929143B1 (ko) 2002-12-13 2009-12-01 삼성전자주식회사 컴퓨터 및 그 제어방법
JP5019573B2 (ja) * 2006-10-18 2012-09-05 キヤノン株式会社 メモリ制御回路とメモリシステム、及びそのメモリ制御方法、及び集積回路
US8151009B2 (en) * 2007-04-25 2012-04-03 Hewlett-Packard Development Company, L.P. Serial connection external interface from printed circuit board translation to parallel memory protocol
US8102671B2 (en) * 2007-04-25 2012-01-24 Hewlett-Packard Development Company, L.P. Serial connection external interface riser cards avoidance of abutment of parallel connection external interface memory modules
US7739441B1 (en) 2007-04-30 2010-06-15 Hewlett-Packard Development Company, L.P. Communicating between a native fully buffered dual in-line memory module protocol and a double data rate synchronous dynamic random access memory protocol
US9405339B1 (en) 2007-04-30 2016-08-02 Hewlett Packard Enterprise Development Lp Power controller
US7996602B1 (en) 2007-04-30 2011-08-09 Hewlett-Packard Development Company, L.P. Parallel memory device rank selection
US7711887B1 (en) 2007-04-30 2010-05-04 Hewlett-Packard Development Company, L.P. Employing a native fully buffered dual in-line memory module protocol to write parallel protocol memory module channels
US9336387B2 (en) * 2007-07-30 2016-05-10 Stroz Friedberg, Inc. System, method, and computer program product for detecting access to a memory device
JP4705613B2 (ja) * 2007-08-02 2011-06-22 技嘉科技股▲ふん▼有限公司 Ｄｄｒｉｉｓｄｒａｍおよびｄｄｒｉｉｉｓｄｒａｍに対応する共通モジュール
TW200921595A (en) * 2007-11-14 2009-05-16 Darfon Electronics Corp Multi-lamp backlight apparatus
JP5217520B2 (ja) * 2008-03-06 2013-06-19 株式会社リコー 電子機器
US7915912B2 (en) * 2008-09-24 2011-03-29 Rambus Inc. Signal lines with internal and external termination
US7868651B1 (en) * 2009-12-08 2011-01-11 International Business Machines Corporation Off-die termination of memory module signal lines
US8495330B2 (en) 2010-04-02 2013-07-23 Intel Corporation Method and apparatus for interfacing with heterogeneous dual in-line memory modules
US8456928B2 (en) 2010-05-24 2013-06-04 International Business Machines Corporation Dynamic adjustment of reference voltage in a computer memory system
TWI460728B (zh) * 2010-12-29 2014-11-11 Silicon Motion Inc 記憶體控制器、記憶裝置以及判斷記憶裝置之型式的方法
WO2015193992A1 (ja) * 2014-06-18 2015-12-23 ゼンテルジャパン株式会社 半導体回路装置及び半導体メモリシステム
US9837169B2 (en) * 2016-02-24 2017-12-05 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Memory system for rapidly testing data lane integrity

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5343503A (en) * 1990-06-24 1994-08-30 Next, Inc. Method and apparatus for clock and data delivery on a bus
US5687330A (en) * 1993-06-18 1997-11-11 Digital Equipment Corporation Semiconductor process, power supply and temperature compensated system bus integrated interface architecture with precision receiver
US5802395A (en) * 1996-07-08 1998-09-01 International Business Machines Corporation High density memory modules with improved data bus performance
US6043694A (en) * 1998-06-24 2000-03-28 Siemens Aktiengesellschaft Lock arrangement for a calibrated DLL in DDR SDRAM applications
US6049476A (en) * 1995-05-15 2000-04-11 Silicon Graphics, Inc. High memory capacity DIMM with data and state memory
US6111757A (en) * 1998-01-16 2000-08-29 International Business Machines Corp. SIMM/DIMM memory module

Family Cites Families (6)

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JPH0589656A (ja) * 1991-09-30 1993-04-09 Nec Corp 記憶装置
JPH05166361A (ja) * 1991-12-12 1993-07-02 Hitachi Ltd 半導体集積回路装置
US5838177A (en) * 1997-01-06 1998-11-17 Micron Technology, Inc. Adjustable output driver circuit having parallel pull-up and pull-down elements
KR100432573B1 (ko) * 1997-12-26 2004-07-16 삼성전자주식회사 임피던스 조절이 가능한 출력 구동 회로를 갖는 반도체 장치
KR100278653B1 (ko) * 1998-01-23 2001-02-01 윤종용 이중 데이터율 모드 반도체 메모리 장치
JP3512332B2 (ja) * 1998-04-07 2004-03-29 富士通株式会社 内部電圧発生回路

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5343503A (en) * 1990-06-24 1994-08-30 Next, Inc. Method and apparatus for clock and data delivery on a bus
US5448591A (en) * 1990-06-24 1995-09-05 Next, Inc. Method and apparatus for clock and data delivery on a bus
US5687330A (en) * 1993-06-18 1997-11-11 Digital Equipment Corporation Semiconductor process, power supply and temperature compensated system bus integrated interface architecture with precision receiver
US6049476A (en) * 1995-05-15 2000-04-11 Silicon Graphics, Inc. High memory capacity DIMM with data and state memory
US5802395A (en) * 1996-07-08 1998-09-01 International Business Machines Corporation High density memory modules with improved data bus performance
US6111757A (en) * 1998-01-16 2000-08-29 International Business Machines Corp. SIMM/DIMM memory module
US6043694A (en) * 1998-06-24 2000-03-28 Siemens Aktiengesellschaft Lock arrangement for a calibrated DLL in DDR SDRAM applications

Also Published As

Publication number Publication date
KR100330531B1 (ko) 2002-04-01
JP2000231534A (ja) 2000-08-22
TW457434B (en) 2001-10-01
KR20000053529A (ko) 2000-08-25
US6347367B1 (en) 2002-02-12

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