SG85106A1 - Soi substrate and method and system for manufacturing the same - Google Patents

Soi substrate and method and system for manufacturing the same

Info

Publication number
SG85106A1
SG85106A1 SG9900695A SG1999000695A SG85106A1 SG 85106 A1 SG85106 A1 SG 85106A1 SG 9900695 A SG9900695 A SG 9900695A SG 1999000695 A SG1999000695 A SG 1999000695A SG 85106 A1 SG85106 A1 SG 85106A1
Authority
SG
Singapore
Prior art keywords
manufacturing
same
soi substrate
soi
substrate
Prior art date
Application number
SG9900695A
Other languages
English (en)
Inventor
Atoji Tadashi
Original Assignee
Canon Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Kk filed Critical Canon Kk
Publication of SG85106A1 publication Critical patent/SG85106A1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67092Apparatus for mechanical treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B01PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01DSEPARATION
    • B01D46/00Filters or filtering processes specially modified for separating dispersed particles from gases or vapours
    • B01D46/42Auxiliary equipment or operation thereof
    • B01D46/48Removing dust other than cleaning filters, e.g. by using collecting trays
    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F24HEATING; RANGES; VENTILATING
    • F24FAIR-CONDITIONING; AIR-HUMIDIFICATION; VENTILATION; USE OF AIR CURRENTS FOR SCREENING
    • F24F3/00Air-conditioning systems in which conditioned primary air is supplied from one or more central stations to distributing units in the rooms or spaces where it may receive secondary treatment; Apparatus specially designed for such systems
    • F24F3/12Air-conditioning systems in which conditioned primary air is supplied from one or more central stations to distributing units in the rooms or spaces where it may receive secondary treatment; Apparatus specially designed for such systems characterised by the treatment of the air otherwise than by heating and cooling
    • F24F3/16Air-conditioning systems in which conditioned primary air is supplied from one or more central stations to distributing units in the rooms or spaces where it may receive secondary treatment; Apparatus specially designed for such systems characterised by the treatment of the air otherwise than by heating and cooling by purification, e.g. by filtering; by sterilisation; by ozonisation
    • F24F3/167Clean rooms, i.e. enclosed spaces in which a uniform flow of filtered air is distributed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Combustion & Propulsion (AREA)
  • Mechanical Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Element Separation (AREA)
  • Filtering Materials (AREA)
  • Weting (AREA)
SG9900695A 1998-03-03 1999-02-23 Soi substrate and method and system for manufacturing the same SG85106A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10050650A JPH11251207A (ja) 1998-03-03 1998-03-03 Soi基板及びその製造方法並びにその製造設備

Publications (1)

Publication Number Publication Date
SG85106A1 true SG85106A1 (en) 2001-12-19

Family

ID=12864826

Family Applications (1)

Application Number Title Priority Date Filing Date
SG9900695A SG85106A1 (en) 1998-03-03 1999-02-23 Soi substrate and method and system for manufacturing the same

Country Status (7)

Country Link
US (1) US20020004286A1 (fr)
EP (1) EP0940847A3 (fr)
JP (1) JPH11251207A (fr)
KR (1) KR100322194B1 (fr)
CN (1) CN1227964A (fr)
SG (1) SG85106A1 (fr)
TW (1) TW476113B (fr)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU4962399A (en) * 1998-07-01 2000-01-24 Exxon Chemical Patents Inc. Elastic blends comprising crystalline polymer and crystallizable polymers of propylene
KR100774066B1 (ko) 1999-09-29 2007-11-06 신에쯔 한도타이 가부시키가이샤 웨이퍼, 에피택셜웨이퍼 및 이들의 제조방법
JP2002134375A (ja) * 2000-10-25 2002-05-10 Canon Inc 半導体基体とその作製方法、および貼り合わせ基体の表面形状測定方法
US8507361B2 (en) * 2000-11-27 2013-08-13 Soitec Fabrication of substrates with a useful layer of monocrystalline semiconductor material
FR2851846A1 (fr) * 2003-02-28 2004-09-03 Canon Kk Systeme de liaison et procede de fabrication d'un substrat semi-conducteur
KR100572887B1 (ko) * 2004-01-19 2006-04-24 삼성전자주식회사 케미컬 필터 및 이를 갖는 팬 필터 유닛
JP2005333072A (ja) * 2004-05-21 2005-12-02 Sumco Corp 半導体基板の評価方法
KR20120011095A (ko) * 2004-09-21 2012-02-06 소이텍 접합될 표면의 처리를 수반한 전달 방법
JP5109287B2 (ja) 2006-05-09 2012-12-26 株式会社Sumco 半導体基板の製造方法
JP5082299B2 (ja) 2006-05-25 2012-11-28 株式会社Sumco 半導体基板の製造方法
FR2910177B1 (fr) * 2006-12-18 2009-04-03 Soitec Silicon On Insulator Couche tres fine enterree
JP5469840B2 (ja) * 2008-09-30 2014-04-16 昭和電工株式会社 炭化珪素単結晶基板の製造方法
US10896127B2 (en) * 2013-01-23 2021-01-19 Lucata Corporation Highly configurable memory architecture for partitioned global address space memory systems
CN104752311B (zh) * 2013-12-27 2018-02-06 中芯国际集成电路制造(上海)有限公司 一种绝缘体上硅衬底及其制造方法
JP6137165B2 (ja) * 2014-12-25 2017-05-31 株式会社Sumco 半導体エピタキシャルウェーハの製造方法および固体撮像素子の製造方法
JP5923197B2 (ja) * 2015-04-17 2016-05-24 株式会社日立国際電気 基板処理装置および半導体装置の製造方法
KR102321839B1 (ko) * 2016-05-09 2021-11-05 어플라이드 머티어리얼스, 인코포레이티드 트랜지스터의 소스/드레인 영역 상의 에피택셜 필름에 대한 선택적 식각 방법
CN114828611B (zh) * 2022-03-02 2023-02-17 深圳市兆兴博拓科技股份有限公司 一种pcb板上全自动贴装设备及贴装方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4983251A (en) * 1985-06-20 1991-01-08 U.S. Philips Corporation Method of manufacturing semiconductor devices
US5551984A (en) * 1993-12-10 1996-09-03 Tokyo Electron Kabushiki Kaisha Vertical heat treatment apparatus with a circulation gas passage

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2633536B2 (ja) * 1986-11-05 1997-07-23 株式会社東芝 接合型半導体基板の製造方法
US4962879A (en) * 1988-12-19 1990-10-16 Duke University Method for bubble-free bonding of silicon wafers
JP2517112B2 (ja) * 1989-06-21 1996-07-24 松下電器産業株式会社 クリ―ントンネル
JP2850502B2 (ja) * 1990-07-20 1999-01-27 富士通株式会社 Soi基板の製造方法
JP3416163B2 (ja) * 1992-01-31 2003-06-16 キヤノン株式会社 半導体基板及びその作製方法
JP2723787B2 (ja) * 1993-08-20 1998-03-09 信越半導体株式会社 結合型基板の製造方法
JP3352340B2 (ja) * 1995-10-06 2002-12-03 キヤノン株式会社 半導体基体とその製造方法
US5507847A (en) * 1994-07-29 1996-04-16 W. L. Gore & Associates, Inc. ULPA filter
TW444266B (en) * 1998-07-23 2001-07-01 Canon Kk Semiconductor substrate and method of producing same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4983251A (en) * 1985-06-20 1991-01-08 U.S. Philips Corporation Method of manufacturing semiconductor devices
US5551984A (en) * 1993-12-10 1996-09-03 Tokyo Electron Kabushiki Kaisha Vertical heat treatment apparatus with a circulation gas passage

Also Published As

Publication number Publication date
EP0940847A2 (fr) 1999-09-08
TW476113B (en) 2002-02-11
CN1227964A (zh) 1999-09-08
KR100322194B1 (ko) 2002-02-04
EP0940847A3 (fr) 2000-07-05
JPH11251207A (ja) 1999-09-17
US20020004286A1 (en) 2002-01-10
KR19990077561A (ko) 1999-10-25

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