SG71909A1 - Method for making field effect transistors having sub-lithographic gates with vertical side walls - Google Patents

Method for making field effect transistors having sub-lithographic gates with vertical side walls

Info

Publication number
SG71909A1
SG71909A1 SG1999000606A SG1999000606A SG71909A1 SG 71909 A1 SG71909 A1 SG 71909A1 SG 1999000606 A SG1999000606 A SG 1999000606A SG 1999000606 A SG1999000606 A SG 1999000606A SG 71909 A1 SG71909 A1 SG 71909A1
Authority
SG
Singapore
Prior art keywords
lithographic
gates
sub
side walls
field effect
Prior art date
Application number
SG1999000606A
Other languages
English (en)
Inventor
Diane C Boyd
Stuart M Burns
Hussein I Hanafi
Yuan Taur
William C Wille
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of SG71909A1 publication Critical patent/SG71909A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
SG1999000606A 1998-02-19 1999-02-15 Method for making field effect transistors having sub-lithographic gates with vertical side walls SG71909A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/026,261 US6040214A (en) 1998-02-19 1998-02-19 Method for making field effect transistors having sub-lithographic gates with vertical side walls

Publications (1)

Publication Number Publication Date
SG71909A1 true SG71909A1 (en) 2000-04-18

Family

ID=21830786

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1999000606A SG71909A1 (en) 1998-02-19 1999-02-15 Method for making field effect transistors having sub-lithographic gates with vertical side walls

Country Status (3)

Country Link
US (1) US6040214A (zh)
CN (1) CN1114939C (zh)
SG (1) SG71909A1 (zh)

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US6204148B1 (en) * 1999-06-11 2001-03-20 Advanced Micro Devices, Inc. Method of making a semiconductor device having a grown polysilicon layer
US7001792B2 (en) * 2000-04-24 2006-02-21 Eagle Research & Development, Llc Ultra-fast nucleic acid sequencing device and a method for making and using the same
US8232582B2 (en) 2000-04-24 2012-07-31 Life Technologies Corporation Ultra-fast nucleic acid sequencing device and a method for making and using the same
US6413792B1 (en) 2000-04-24 2002-07-02 Eagle Research Development, Llc Ultra-fast nucleic acid sequencing device and a method for making and using the same
US6559062B1 (en) 2000-11-15 2003-05-06 Agere Systems, Inc. Method for avoiding notching in a semiconductor interconnect during a metal etching step
US20020127855A1 (en) * 2001-01-04 2002-09-12 Sauer Jon Robert Method for fabricating a pattern in a mask on a surface of an object and product manufactured thereby
US6635923B2 (en) 2001-05-24 2003-10-21 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
US6756637B2 (en) * 2001-07-06 2004-06-29 International Business Machines Corporation Method of controlling floating body effects in an asymmetrical SOI device
KR100453951B1 (ko) * 2002-01-16 2004-10-20 주식회사 하이닉스반도체 반도체소자의 패드산화막 형성방법
US6756284B2 (en) * 2002-09-18 2004-06-29 Silicon Storage Technology, Inc. Method for forming a sublithographic opening in a semiconductor process
US6656824B1 (en) 2002-11-08 2003-12-02 International Business Machines Corporation Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch
US6806534B2 (en) * 2003-01-14 2004-10-19 International Business Machines Corporation Damascene method for improved MOS transistor
JP4917246B2 (ja) * 2003-11-17 2012-04-18 ローム株式会社 半導体装置およびその製造方法
EP1709680A4 (en) * 2004-01-21 2008-07-02 Atmel Corp VERTICAL GRID CMOS WITH INDEPENDENT GRID LENGTH OF LITHOGRAPHY
US7087532B2 (en) * 2004-09-30 2006-08-08 International Business Machines Corporation Formation of controlled sublithographic structures
US8195693B2 (en) 2004-12-16 2012-06-05 International Business Machines Corporation Automatic composition of services through semantic attribute matching
US7345370B2 (en) * 2005-01-12 2008-03-18 International Business Machines Corporation Wiring patterns formed by selective metal plating
US20060253476A1 (en) * 2005-05-09 2006-11-09 Roth Mary A Technique for relationship discovery in schemas using semantic name indexing
EP2064745A1 (en) * 2006-09-18 2009-06-03 QuNano AB Method of producing precision vertical and horizontal layers in a vertical semiconductor structure
US7384852B2 (en) 2006-10-25 2008-06-10 International Business Machines Corporation Sub-lithographic gate length transistor using self-assembling polymers
CN102315830A (zh) * 2011-04-25 2012-01-11 浙江大学 一种薄膜体声波谐振器的制备方法
CN102832172A (zh) * 2011-06-17 2012-12-19 北大方正集团有限公司 一种低压金属栅互补金属氧化物半导体及其制备方法
US20150050792A1 (en) * 2013-08-13 2015-02-19 Globalfoundries Inc. Extra narrow diffusion break for 3d finfet technologies
KR102306674B1 (ko) 2015-03-17 2021-09-29 삼성전자주식회사 반도체 소자 및 그 제조방법
US10553547B2 (en) 2015-05-15 2020-02-04 Skyworks Solutions, Inc. Radio frequency isolation cavity formation using sacrificial material
CN106057680B (zh) * 2016-07-08 2019-05-31 清华大学 环形栅薄膜晶体管及其制备方法
CN106449407B (zh) * 2016-07-08 2019-05-31 清华大学 环形栅薄膜晶体管及其制备方法

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US5792686A (en) * 1995-08-04 1998-08-11 Mosel Vitelic, Inc. Method of forming a bit-line and a capacitor structure in an integrated circuit

Also Published As

Publication number Publication date
CN1114939C (zh) 2003-07-16
US6040214A (en) 2000-03-21
CN1226741A (zh) 1999-08-25

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