SG53118A1 - Row redundancy block architecture - Google Patents

Row redundancy block architecture

Info

Publication number
SG53118A1
SG53118A1 SG1997003935A SG1997003935A SG53118A1 SG 53118 A1 SG53118 A1 SG 53118A1 SG 1997003935 A SG1997003935 A SG 1997003935A SG 1997003935 A SG1997003935 A SG 1997003935A SG 53118 A1 SG53118 A1 SG 53118A1
Authority
SG
Singapore
Prior art keywords
row redundancy
redundancy block
block architecture
architecture
row
Prior art date
Application number
SG1997003935A
Other languages
English (en)
Inventor
John Debrosse
Toshiaki Kirihata
Hing Wong
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of SG53118A1 publication Critical patent/SG53118A1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
SG1997003935A 1996-12-03 1997-11-01 Row redundancy block architecture SG53118A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/758,783 US5691946A (en) 1996-12-03 1996-12-03 Row redundancy block architecture

Publications (1)

Publication Number Publication Date
SG53118A1 true SG53118A1 (en) 1998-09-28

Family

ID=25053105

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1997003935A SG53118A1 (en) 1996-12-03 1997-11-01 Row redundancy block architecture

Country Status (9)

Country Link
US (1) US5691946A (de)
EP (1) EP0847010B1 (de)
JP (1) JP3229260B2 (de)
KR (1) KR100266116B1 (de)
CN (1) CN1132187C (de)
DE (1) DE69718609D1 (de)
MY (1) MY116164A (de)
SG (1) SG53118A1 (de)
TW (1) TW334531B (de)

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Publication number Priority date Publication date Assignee Title
JPH10241398A (ja) * 1997-02-28 1998-09-11 Nec Corp 半導体メモリ装置
US5831913A (en) * 1997-03-31 1998-11-03 International Business Machines Corporation Method of making a memory fault-tolerant using a variable size redundancy replacement configuration
US5831914A (en) * 1997-03-31 1998-11-03 International Business Machines Corporation Variable size redundancy replacement architecture to make a memory fault-tolerant
TW358939B (en) * 1997-07-03 1999-05-21 United Microelectronics Corp Reparable memory module and method of repairing the memory module
CN1094719C (zh) * 1997-08-21 2002-11-20 联华电子股份有限公司 可修护的存储模块与修护存储模块的方法
JP3206541B2 (ja) * 1998-03-04 2001-09-10 日本電気株式会社 半導体記憶装置
US5963489A (en) * 1998-03-24 1999-10-05 International Business Machines Corporation Method and apparatus for redundancy word line replacement in a repairable semiconductor memory device
US6018483A (en) * 1998-12-10 2000-01-25 Siemens Aktiengesellschaft Distributed block redundancy for memory devices
US6115310A (en) * 1999-01-05 2000-09-05 International Business Machines Corporation Wordline activation delay monitor using sample wordline located in data-storing array
US6185135B1 (en) 1999-01-05 2001-02-06 International Business Machines Corporation Robust wordline activation delay monitor using a plurality of sample wordlines
US6101138A (en) * 1999-07-22 2000-08-08 Eton Technology, Inc. Area efficient global row redundancy scheme for DRAM
US6195300B1 (en) 2000-03-24 2001-02-27 International Business Machines Corporation CBR refresh control for the redundancy array
JP4553464B2 (ja) * 2000-08-29 2010-09-29 ルネサスエレクトロニクス株式会社 半導体記憶装置
US6445626B1 (en) * 2001-03-29 2002-09-03 Ibm Corporation Column redundancy architecture system for an embedded DRAM
US6400619B1 (en) 2001-04-25 2002-06-04 International Business Machines Corporation Micro-cell redundancy scheme for high performance eDRAM
US6751113B2 (en) * 2002-03-07 2004-06-15 Netlist, Inc. Arrangement of integrated circuits in a memory module
US20050018495A1 (en) * 2004-01-29 2005-01-27 Netlist, Inc. Arrangement of integrated circuits in a memory module
WO2005081260A1 (ja) * 2004-02-20 2005-09-01 Spansion Llc 半導体記憶装置および半導体記憶装置の冗長方法
US6982911B2 (en) * 2004-03-18 2006-01-03 Infineon Technologies Ag Memory device with common row interface
US7110319B2 (en) * 2004-08-27 2006-09-19 Micron Technology, Inc. Memory devices having reduced coupling noise between wordlines
JP2006107590A (ja) * 2004-10-04 2006-04-20 Nec Electronics Corp 半導体集積回路装置及びそのテスト方法
KR100704039B1 (ko) 2006-01-20 2007-04-04 삼성전자주식회사 디코딩 신호가 워드라인 방향으로 버싱되는 반도체 메모리장치
JP5137408B2 (ja) * 2007-02-05 2013-02-06 パナソニック株式会社 電気ヒューズ回路
US8238173B2 (en) * 2009-07-16 2012-08-07 Zikbit Ltd Using storage cells to perform computation
US9799412B2 (en) * 2014-09-30 2017-10-24 Sony Semiconductor Solutions Corporation Memory having a plurality of memory cells and a plurality of word lines

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Publication number Priority date Publication date Assignee Title
US4051354A (en) * 1975-07-03 1977-09-27 Texas Instruments Incorporated Fault-tolerant cell addressable array
US4047163A (en) * 1975-07-03 1977-09-06 Texas Instruments Incorporated Fault-tolerant cell addressable array
US5046046A (en) * 1978-03-10 1991-09-03 Intel Corporation Redundancy CAM using word line from memory
US4228528B2 (en) * 1979-02-09 1992-10-06 Memory with redundant rows and columns
EP0070823A1 (de) * 1981-02-02 1983-02-09 Mostek Corporation Identifizierungsschaltung für ein redundantes element eines halbleiterspeichers
US4922128A (en) * 1989-01-13 1990-05-01 Ibm Corporation Boost clock circuit for driving redundant wordlines and sample wordlines
US5134616A (en) * 1990-02-13 1992-07-28 International Business Machines Corporation Dynamic ram with on-chip ecc and optimized bit and word redundancy
US5268866A (en) * 1992-03-02 1993-12-07 Motorola, Inc. Memory with column redundancy and localized column redundancy control signals
JP2734315B2 (ja) * 1992-09-24 1998-03-30 日本電気株式会社 半導体メモリ装置
US5422850A (en) * 1993-07-12 1995-06-06 Texas Instruments Incorporated Semiconductor memory device and defective memory cell repair circuit
KR0174338B1 (ko) * 1994-11-30 1999-04-01 윌리엄 티. 엘리스 간단하게 테스트할 수 있는 구성을 갖는 랜덤 액세스 메모리
US5517442A (en) * 1995-03-13 1996-05-14 International Business Machines Corporation Random access memory and an improved bus arrangement therefor
US5574688A (en) * 1995-05-10 1996-11-12 Sgs-Thomson Microelectronics, Inc. Apparatus and method for mapping a redundant memory column to a defective memory column
US5625603A (en) * 1995-06-07 1997-04-29 Sgs-Thomson Microelectronics, Inc. Integrated circuit with unequally-sized, paired memory coupled to odd number of input/output pads

Also Published As

Publication number Publication date
EP0847010A3 (de) 1999-08-18
EP0847010B1 (de) 2003-01-22
TW334531B (en) 1998-06-21
KR19980063434A (ko) 1998-10-07
CN1184316A (zh) 1998-06-10
MY116164A (en) 2003-11-28
JP3229260B2 (ja) 2001-11-19
KR100266116B1 (ko) 2000-10-02
CN1132187C (zh) 2003-12-24
DE69718609D1 (de) 2003-02-27
JPH10162599A (ja) 1998-06-19
US5691946A (en) 1997-11-25
EP0847010A2 (de) 1998-06-10

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