SG50950A1 - A system level mechanism for invalidating data stored in the external cache of a processor in a computer system - Google Patents
A system level mechanism for invalidating data stored in the external cache of a processor in a computer systemInfo
- Publication number
- SG50950A1 SG50950A1 SG1996006437A SG1996006437A SG50950A1 SG 50950 A1 SG50950 A1 SG 50950A1 SG 1996006437 A SG1996006437 A SG 1996006437A SG 1996006437 A SG1996006437 A SG 1996006437A SG 50950 A1 SG50950 A1 SG 50950A1
- Authority
- SG
- Singapore
- Prior art keywords
- processor
- data stored
- external cache
- computer system
- level mechanism
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0817—Cache consistency protocols using directory methods
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US41436595A | 1995-03-31 | 1995-03-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG50950A1 true SG50950A1 (en) | 1998-07-20 |
Family
ID=23641138
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG1996006437A SG50950A1 (en) | 1995-03-31 | 1996-03-29 | A system level mechanism for invalidating data stored in the external cache of a processor in a computer system |
Country Status (5)
Country | Link |
---|---|
US (1) | US5737755A (fr) |
EP (1) | EP0735481B1 (fr) |
JP (1) | JP3887036B2 (fr) |
DE (1) | DE69628079T2 (fr) |
SG (1) | SG50950A1 (fr) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5835950A (en) * | 1996-07-12 | 1998-11-10 | Samsung Electronics Co., Ltd. | Self-invalidation method for reducing coherence overheads in a bus-based shared-memory multiprocessor apparatus |
US6412047B2 (en) * | 1999-10-01 | 2002-06-25 | Stmicroelectronics, Inc. | Coherency protocol |
Family Cites Families (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4228503A (en) * | 1978-10-02 | 1980-10-14 | Sperry Corporation | Multiplexed directory for dedicated cache memory system |
US4638431A (en) * | 1984-09-17 | 1987-01-20 | Nec Corporation | Data processing system for vector processing having a cache invalidation control unit |
DE3740834A1 (de) * | 1987-01-22 | 1988-08-04 | Nat Semiconductor Corp | Aufrechterhaltung der kohaerenz zwischen einem mikroprozessorenintegrierten cache-speicher und einem externen speicher |
JPH065524B2 (ja) * | 1987-11-18 | 1994-01-19 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 記憶装置管理方法 |
US5058006A (en) * | 1988-06-27 | 1991-10-15 | Digital Equipment Corporation | Method and apparatus for filtering invalidate requests |
US5226146A (en) * | 1988-10-28 | 1993-07-06 | Hewlett-Packard Company | Duplicate tag store purge queue |
EP0380842A3 (fr) * | 1989-02-03 | 1991-06-12 | Digital Equipment Corporation | Méthode et appareil pour réaliser l'interfaçage entre l'unité de commande système pour un multiprocesseur et les unités centrales de traitement |
CA1325289C (fr) * | 1989-02-03 | 1993-12-14 | Digital Equipment Corporation | Methode pour realiser la coherence des donnees entre plusieurs antememoires et la memoire principale d'un ordinateur multiprocesseur |
US5222224A (en) * | 1989-02-03 | 1993-06-22 | Digital Equipment Corporation | Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system |
US5036459A (en) * | 1989-03-09 | 1991-07-30 | U.S. Philips Corporation | Multi-processor computer system with distributed memory and an interprocessor communication mechanism, and method for operating such mechanism |
JPH0666056B2 (ja) * | 1989-10-12 | 1994-08-24 | 甲府日本電気株式会社 | 情報処理システム |
JP2833062B2 (ja) * | 1989-10-30 | 1998-12-09 | 株式会社日立製作所 | キャッシュメモリ制御方法とこのキャッシュメモリ制御方法を用いたプロセッサおよび情報処理装置 |
US5297269A (en) * | 1990-04-26 | 1994-03-22 | Digital Equipment Company | Cache coherency protocol for multi processor computer system |
US5249284A (en) * | 1990-06-04 | 1993-09-28 | Ncr Corporation | Method and system for maintaining data coherency between main and cache memories |
DE69127936T2 (de) * | 1990-06-29 | 1998-05-07 | Digital Equipment Corp | Busprotokoll für Prozessor mit write-back cache |
US5193170A (en) * | 1990-10-26 | 1993-03-09 | International Business Machines Corporation | Methods and apparatus for maintaining cache integrity whenever a cpu write to rom operation is performed with rom mapped to ram |
CA2051209C (fr) * | 1990-11-30 | 1996-05-07 | Pradeep S. Sindhu | Protocoles de coherence pour multiprocesseurs a memoire commune |
US5265235A (en) * | 1990-11-30 | 1993-11-23 | Xerox Corporation | Consistency protocols for shared memory multiprocessors |
JPH04318654A (ja) * | 1991-02-13 | 1992-11-10 | Hewlett Packard Co <Hp> | マイクロプロセッサへの割り込みのリダイレクションシステム |
US5303362A (en) * | 1991-03-20 | 1994-04-12 | Digital Equipment Corporation | Coupled memory multiprocessor computer system including cache coherency management protocols |
JP2703417B2 (ja) * | 1991-04-05 | 1998-01-26 | 富士通株式会社 | 受信バッファ |
AU2270892A (en) * | 1991-06-26 | 1993-01-25 | Ast Research, Inc. | Automatic distribution of interrupts controller for a multiple processor computer system |
JPH0512117A (ja) * | 1991-07-04 | 1993-01-22 | Toshiba Corp | キヤツシユ一致化方式 |
DE69230428T2 (de) * | 1991-09-27 | 2000-08-03 | Sun Microsystems, Inc. | Verklemmungserkennung und Maskierung enthaltende Busarbitrierungsarchitektur |
EP0553743A1 (fr) * | 1992-01-31 | 1993-08-04 | Motorola, Inc. | Contrôleur d'antémémoire |
US5319766A (en) * | 1992-04-24 | 1994-06-07 | Digital Equipment Corporation | Duplicate tag store for a processor having primary and backup cache memories in a multiprocessor computer system |
US5553266A (en) * | 1992-04-24 | 1996-09-03 | Digital Equipment Corporation | Update vs. invalidate policy for a snoopy bus protocol |
US5319753A (en) * | 1992-09-29 | 1994-06-07 | Zilog, Inc. | Queued interrupt mechanism with supplementary command/status/message information |
US5434993A (en) * | 1992-11-09 | 1995-07-18 | Sun Microsystems, Inc. | Methods and apparatus for creating a pending write-back controller for a cache controller on a packet switched memory bus employing dual directories |
US5604882A (en) * | 1993-08-27 | 1997-02-18 | International Business Machines Corporation | System and method for empty notification from peer cache units to global storage control unit in a multiprocessor data processing system |
JPH07105031A (ja) * | 1993-09-20 | 1995-04-21 | Internatl Business Mach Corp <Ibm> | 多重プロセッサ・コンピュータ・システム内で割込み情報を伝えるための方法および装置 |
US5603005A (en) * | 1994-12-27 | 1997-02-11 | Unisys Corporation | Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed |
-
1996
- 1996-03-15 EP EP96301804A patent/EP0735481B1/fr not_active Expired - Lifetime
- 1996-03-15 DE DE69628079T patent/DE69628079T2/de not_active Expired - Fee Related
- 1996-03-29 SG SG1996006437A patent/SG50950A1/en unknown
- 1996-03-29 JP JP09959596A patent/JP3887036B2/ja not_active Expired - Lifetime
-
1997
- 1997-02-12 US US08/797,995 patent/US5737755A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0735481A1 (fr) | 1996-10-02 |
JP3887036B2 (ja) | 2007-02-28 |
DE69628079D1 (de) | 2003-06-18 |
DE69628079T2 (de) | 2004-02-26 |
EP0735481B1 (fr) | 2003-05-14 |
US5737755A (en) | 1998-04-07 |
JPH0922382A (ja) | 1997-01-21 |
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