JPH0619759B2
(ja)
*
|
1990-05-21 |
1994-03-16 |
富士ゼロックス株式会社 |
マルチプロセッサシステムにおける相互通信方法
|
US5426747A
(en)
*
|
1991-03-22 |
1995-06-20 |
Object Design, Inc. |
Method and apparatus for virtual memory mapping and transaction management in an object-oriented database system
|
US5490261A
(en)
*
|
1991-04-03 |
1996-02-06 |
International Business Machines Corporation |
Interlock for controlling processor ownership of pipelined data for a store in cache
|
US5826055A
(en)
*
|
1991-07-08 |
1998-10-20 |
Seiko Epson Corporation |
System and method for retiring instructions in a superscalar microprocessor
|
US5493687A
(en)
|
1991-07-08 |
1996-02-20 |
Seiko Epson Corporation |
RISC microprocessor architecture implementing multiple typed register sets
|
US5539911A
(en)
*
|
1991-07-08 |
1996-07-23 |
Seiko Epson Corporation |
High-performance, superscalar-based computer system with out-of-order instruction execution
|
US5359569A
(en)
*
|
1991-10-29 |
1994-10-25 |
Hitachi Ltd. |
Semiconductor memory
|
US5966728A
(en)
*
|
1992-01-02 |
1999-10-12 |
International Business Machines Corp. |
Computer system and method for snooping date writes to cacheable memory locations in an expansion memory device
|
JPH0727494B2
(ja)
*
|
1992-01-02 |
1995-03-29 |
インターナショナル・ビジネス・マシーンズ・コーポレイション |
キャッシュ・スヌープ/データ無効化機能を有するコンピュータ・システム
|
JPH05241827A
(ja)
*
|
1992-02-27 |
1993-09-21 |
Nec Ibaraki Ltd |
命令バッファ制御装置
|
DE69311330T2
(de)
|
1992-03-31 |
1997-09-25 |
Seiko Epson Corp |
Befehlsablauffolgeplanung von einem risc-superskalarprozessor
|
US5485592A
(en)
*
|
1992-04-07 |
1996-01-16 |
Video Technology Computers, Ltd. |
Write back cache controller method and apparatus for use in a system having a CPU with internal cache memory
|
JP3637920B2
(ja)
|
1992-05-01 |
2005-04-13 |
セイコーエプソン株式会社 |
スーパースケーラマイクロプロセサに於て命令をリタイアさせるシステム及び方法
|
US5450547A
(en)
*
|
1992-10-01 |
1995-09-12 |
Xerox Corporation |
Bus interface using pending channel information stored in single circular queue for controlling channels of data transfer within multiple FIFO devices
|
US5353415A
(en)
*
|
1992-10-02 |
1994-10-04 |
Compaq Computer Corporation |
Method and apparatus for concurrency of bus operations
|
US5448708A
(en)
*
|
1992-10-30 |
1995-09-05 |
Ward; James P. |
System for asynchronously delivering enqueue and dequeue information in a pipe interface having distributed, shared memory
|
US5434993A
(en)
*
|
1992-11-09 |
1995-07-18 |
Sun Microsystems, Inc. |
Methods and apparatus for creating a pending write-back controller for a cache controller on a packet switched memory bus employing dual directories
|
US5664149A
(en)
*
|
1992-11-13 |
1997-09-02 |
Cyrix Corporation |
Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol
|
US5628021A
(en)
|
1992-12-31 |
1997-05-06 |
Seiko Epson Corporation |
System and method for assigning tags to control instruction processing in a superscalar processor
|
US5604912A
(en)
*
|
1992-12-31 |
1997-02-18 |
Seiko Epson Corporation |
System and method for assigning tags to instructions to control instruction execution
|
EP0849665B1
(de)
*
|
1992-12-31 |
2001-10-04 |
Seiko Epson Corporation |
System und Verfahren zur Änderung der Namen von Registern
|
US5581727A
(en)
*
|
1993-03-22 |
1996-12-03 |
Compaq Computer Corporation |
Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control
|
EP0619547A1
(de)
*
|
1993-04-05 |
1994-10-12 |
Motorola, Inc. |
Verfahren zur Datenabfrage und Einrichtung dafür
|
US5506967A
(en)
*
|
1993-06-15 |
1996-04-09 |
Unisys Corporation |
Storage queue with adjustable level thresholds for cache invalidation systems in cache oriented computer architectures
|
US5553270A
(en)
*
|
1993-09-01 |
1996-09-03 |
Digital Equipment Corporation |
Apparatus for providing improved memory access in page mode access systems with pipelined cache access and main memory address replay
|
JP2675981B2
(ja)
*
|
1993-09-20 |
1997-11-12 |
インターナショナル・ビジネス・マシーンズ・コーポレイション |
スヌープ・プッシュ・オペレーションを回避する方法
|
JPH0793216A
(ja)
*
|
1993-09-27 |
1995-04-07 |
Hitachi Ltd |
キャッシュ記憶制御装置
|
US5636365A
(en)
*
|
1993-10-05 |
1997-06-03 |
Nec Corporation |
Hierarchical buffer memories for selectively controlling data coherence including coherence control request means
|
JP3200757B2
(ja)
*
|
1993-10-22 |
2001-08-20 |
株式会社日立製作所 |
並列計算機の記憶制御方法および並列計算機
|
US5664137A
(en)
*
|
1994-01-04 |
1997-09-02 |
Intel Corporation |
Method and apparatus for executing and dispatching store operations in a computer system
|
KR970010368B1
(ko)
*
|
1994-01-18 |
1997-06-25 |
삼성전자 주식회사 |
캐시라인 리프레이스장치 및 방법
|
US5623628A
(en)
*
|
1994-03-02 |
1997-04-22 |
Intel Corporation |
Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue
|
US5666509A
(en)
*
|
1994-03-24 |
1997-09-09 |
Motorola, Inc. |
Data processing system for performing either a precise memory access or an imprecise memory access based upon a logical address value and method thereof
|
US5572698A
(en)
*
|
1994-04-18 |
1996-11-05 |
Rolm Company |
System and method for allocating memory resources where the category of a memory resource determines where on a circular stack a pointer to the memory resource is placed
|
JP2778913B2
(ja)
*
|
1994-04-26 |
1998-07-23 |
株式会社東芝 |
マルチプロセッサシステム及びメモリアロケーション方法
|
EP0683457A1
(de)
*
|
1994-05-20 |
1995-11-22 |
Advanced Micro Devices, Inc. |
Computersystem mit einer Snoopsteuerschaltung
|
US5621896A
(en)
*
|
1994-06-01 |
1997-04-15 |
Motorola, Inc. |
Data processor with unified store queue permitting hit under miss memory accesses
|
US5768558A
(en)
*
|
1994-08-29 |
1998-06-16 |
Intel Corporation |
Identification of the distinction between the beginning of a new write back cycle and an ongoing write cycle
|
US5832304A
(en)
*
|
1995-03-15 |
1998-11-03 |
Unisys Corporation |
Memory queue with adjustable priority and conflict detection
|
US5657472A
(en)
*
|
1995-03-31 |
1997-08-12 |
Sun Microsystems, Inc. |
Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor
|
US5907485A
(en)
*
|
1995-03-31 |
1999-05-25 |
Sun Microsystems, Inc. |
Method and apparatus for flow control in packet-switched computer system
|
US5710891A
(en)
*
|
1995-03-31 |
1998-01-20 |
Sun Microsystems, Inc. |
Pipelined distributed bus arbitration system
|
US5581729A
(en)
*
|
1995-03-31 |
1996-12-03 |
Sun Microsystems, Inc. |
Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system
|
US5634068A
(en)
*
|
1995-03-31 |
1997-05-27 |
Sun Microsystems, Inc. |
Packet switched cache coherent multiprocessor system
|
EP0735480B1
(de)
*
|
1995-03-31 |
2003-06-04 |
Sun Microsystems, Inc. |
Cache-kohärentes Computersystem, das Entwertungs- und Rückschreiboperationen minimiert
|
US5689713A
(en)
*
|
1995-03-31 |
1997-11-18 |
Sun Microsystems, Inc. |
Method and apparatus for interrupt communication in a packet-switched computer system
|
US5684977A
(en)
*
|
1995-03-31 |
1997-11-04 |
Sun Microsystems, Inc. |
Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system
|
EP0735481B1
(de)
*
|
1995-03-31 |
2003-05-14 |
Sun Microsystems, Inc. |
Mechanismus auf Systemebene zum Entwerten von Daten, die im externen Cache eines Prozessors in einem Computersystem gespeichert sind
|
US5655100A
(en)
*
|
1995-03-31 |
1997-08-05 |
Sun Microsystems, Inc. |
Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system
|
US5737756A
(en)
*
|
1995-04-28 |
1998-04-07 |
Unisys Corporation |
Dual bus computer network using dual busses with dual spy modules enabling clearing of invalidation queue for processor with store through cache while providing retry cycles for incomplete accesses to invalidation queue
|
US5943494A
(en)
*
|
1995-06-07 |
1999-08-24 |
International Business Machines Corporation |
Method and system for processing multiple branch instructions that write to count and link registers
|
GB9521977D0
(en)
*
|
1995-10-26 |
1996-01-03 |
Sgs Thomson Microelectronics |
Cache memory
|
GB9521978D0
(en)
*
|
1995-10-26 |
1996-01-03 |
Sgs Thomson Microelectronics |
Computer instruction supply
|
US5778431A
(en)
*
|
1995-12-19 |
1998-07-07 |
Advanced Micro Devices, Inc. |
System and apparatus for partially flushing cache memory
|
US5765196A
(en)
*
|
1996-02-27 |
1998-06-09 |
Sun Microsystems, Inc. |
System and method for servicing copyback requests in a multiprocessor system with a shared memory
|
US5778422A
(en)
*
|
1996-04-04 |
1998-07-07 |
International Business Machines Corporation |
Data processing system memory controller that selectively caches data associated with write requests
|
US5920891A
(en)
*
|
1996-05-20 |
1999-07-06 |
Advanced Micro Devices, Inc. |
Architecture and method for controlling a cache memory
|
JPH1078934A
(ja)
*
|
1996-07-01 |
1998-03-24 |
Sun Microsyst Inc |
パケット切替えコンピュータ・システムのマルチサイズ・バス結合システム
|
US5893165A
(en)
*
|
1996-07-01 |
1999-04-06 |
Sun Microsystems, Inc. |
System and method for parallel execution of memory transactions using multiple memory models, including SSO, TSO, PSO and RMO
|
US6199152B1
(en)
|
1996-08-22 |
2001-03-06 |
Transmeta Corporation |
Translated memory protection apparatus for an advanced microprocessor
|
US5926832A
(en)
*
|
1996-09-26 |
1999-07-20 |
Transmeta Corporation |
Method and apparatus for aliasing memory data in an advanced microprocessor
|
US5835908A
(en)
*
|
1996-11-19 |
1998-11-10 |
Microsoft Corporation |
Processing multiple database transactions in the same process to reduce process overhead and redundant retrieval from database servers
|
US5895486A
(en)
*
|
1996-12-20 |
1999-04-20 |
International Business Machines Corporation |
Method and system for selectively invalidating cache lines during multiple word store operations for memory coherence
|
US6336166B1
(en)
*
|
1997-04-07 |
2002-01-01 |
Apple Computer, Inc. |
Memory control device with split read for ROM access
|
US5894569A
(en)
*
|
1997-04-14 |
1999-04-13 |
International Business Machines Corporation |
Method and system for back-end gathering of store instructions within a data-processing system
|
US5956503A
(en)
*
|
1997-04-14 |
1999-09-21 |
International Business Machines Corporation |
Method and system for front-end and back-end gathering of store instructions within a data-processing system
|
US5960457A
(en)
*
|
1997-05-01 |
1999-09-28 |
Advanced Micro Devices, Inc. |
Cache coherency test system and methodology for testing cache operation in the presence of an external snoop
|
US5900017A
(en)
*
|
1997-05-14 |
1999-05-04 |
International Business Machines Corporation |
Snooping a variable number of cache addresses in a multiple processor system by a single snoop request
|
KR19990003937A
(ko)
*
|
1997-06-26 |
1999-01-15 |
김영환 |
프리페치 장치
|
US6505290B1
(en)
*
|
1997-09-05 |
2003-01-07 |
Motorola, Inc. |
Method and apparatus for interfacing a processor to a coprocessor
|
US5983338A
(en)
*
|
1997-09-05 |
1999-11-09 |
Motorola, Inc. |
Method and apparatus for interfacing a processor to a coprocessor for communicating register write information
|
US6101420A
(en)
*
|
1997-10-24 |
2000-08-08 |
Compaq Computer Corporation |
Method and apparatus for disambiguating change-to-dirty commands in a switch based multi-processing system with coarse directories
|
US6112270A
(en)
*
|
1997-10-31 |
2000-08-29 |
International Business Machines Corporation |
Method and system for high speed transferring of strictly ordered bus operations by reissuing bus operations in a multiprocessor system
|
US6145038A
(en)
*
|
1997-10-31 |
2000-11-07 |
International Business Machines Corporation |
Method and system for early slave forwarding of strictly ordered bus operations
|
US6366979B1
(en)
*
|
1997-12-16 |
2002-04-02 |
Cypress Semiconductor Corp. |
Apparatus and method for shorting retransmit recovery times utilizing cache memory in high speed FIFO
|
US6209052B1
(en)
*
|
1998-09-30 |
2001-03-27 |
Compaq Computer Corporation |
System and method for suppressing processor cycles to memory until after a peripheral device write cycle is acknowledged by the memory arbiter
|
GB2345987B
(en)
*
|
1999-01-19 |
2003-08-06 |
Advanced Risc Mach Ltd |
Memory control within data processing systems
|
US6321303B1
(en)
*
|
1999-03-18 |
2001-11-20 |
International Business Machines Corporation |
Dynamically modifying queued transactions in a cache memory system
|
US6230256B1
(en)
*
|
1999-03-31 |
2001-05-08 |
Bull Hn Information Systems Inc. |
Data processing system having a bus wider than processor instruction width
|
US6289420B1
(en)
|
1999-05-06 |
2001-09-11 |
Sun Microsystems, Inc. |
System and method for increasing the snoop bandwidth to cache tags in a multiport cache memory subsystem
|
US6732254B1
(en)
|
1999-09-15 |
2004-05-04 |
Koninklijke Philips Electronics N.V. |
Can device featuring advanced can filtering and message acceptance
|
US6748589B1
(en)
|
1999-10-20 |
2004-06-08 |
Transmeta Corporation |
Method for increasing the speed of speculative execution
|
US6415357B1
(en)
*
|
1999-12-23 |
2002-07-02 |
Unisys Corporation |
Caching method and apparatus
|
US6581138B2
(en)
*
|
2000-02-29 |
2003-06-17 |
Stmicroelectronics, Inc. |
Branch-prediction driven instruction prefetch
|
US6968469B1
(en)
|
2000-06-16 |
2005-11-22 |
Transmeta Corporation |
System and method for preserving internal processor context when the processor is powered down and restoring the internal processor context when processor is restored
|
US6438647B1
(en)
|
2000-06-23 |
2002-08-20 |
International Business Machines Corporation |
Method and apparatus for providing battery-backed immediate write back cache for an array of disk drives in a computer system
|
US6434673B1
(en)
*
|
2000-06-30 |
2002-08-13 |
Intel Corporation |
Optimized configurable scheme for demand based resource sharing of request queues in a cache controller
|
WO2002038739A1
(en)
*
|
2000-11-09 |
2002-05-16 |
Univ Queensland |
Bacterial expression systems
|
US6732236B2
(en)
*
|
2000-12-18 |
2004-05-04 |
Redback Networks Inc. |
Cache retry request queue
|
US20030033433A1
(en)
*
|
2001-08-08 |
2003-02-13 |
Stroll Zoltan Z. |
Processing satellite web proxy cache
|
US7472230B2
(en)
*
|
2001-09-14 |
2008-12-30 |
Hewlett-Packard Development Company, L.P. |
Preemptive write back controller
|
US6704844B2
(en)
*
|
2001-10-16 |
2004-03-09 |
International Business Machines Corporation |
Dynamic hardware and software performance optimizations for super-coherent SMP systems
|
US7895239B2
(en)
*
|
2002-01-04 |
2011-02-22 |
Intel Corporation |
Queue arrays in network devices
|
US6745308B2
(en)
*
|
2002-02-19 |
2004-06-01 |
Ati Technologies, Inc. |
Method and system for bypassing memory controller components
|
US7024663B2
(en)
*
|
2002-07-10 |
2006-04-04 |
Micron Technology, Inc. |
Method and system for generating object code to facilitate predictive memory retrieval
|
US6850999B1
(en)
*
|
2002-11-27 |
2005-02-01 |
Cisco Technology, Inc. |
Coherency coverage of data across multiple packets varying in sizes
|
US7447205B2
(en)
*
|
2003-05-09 |
2008-11-04 |
Hewlett-Packard Development Company, L.P. |
Systems and methods to insert broadcast transactions into a fast data stream of transactions
|
US20040225707A1
(en)
*
|
2003-05-09 |
2004-11-11 |
Chong Huai-Ter Victor |
Systems and methods for combining a slow data stream and a fast data stream into a single fast data stream
|
US7114054B2
(en)
*
|
2003-05-09 |
2006-09-26 |
Hewlett-Packard Development Company, L.P. |
Systems and methods for increasing transaction entries in a hardware queue
|
US6996654B2
(en)
*
|
2003-05-09 |
2006-02-07 |
Hewlett-Packard Development Company, L.P. |
Systems and methods for generating multiple transaction identifiers to reduced latency in computer architecture
|
US8279886B2
(en)
|
2004-12-30 |
2012-10-02 |
Intel Corporation |
Dataport and methods thereof
|
US20060155934A1
(en)
*
|
2005-01-11 |
2006-07-13 |
Ramakrishnan Rajamony |
System and method for reducing unnecessary cache operations
|
US20070180156A1
(en)
*
|
2006-02-01 |
2007-08-02 |
International Business Machines Corporation |
Method for completing IO commands after an IO translation miss
|
US7533237B1
(en)
|
2006-05-11 |
2009-05-12 |
Nvidia Corporation |
Off-chip memory allocation for a unified shader
|
US7533236B1
(en)
*
|
2006-05-11 |
2009-05-12 |
Nvidia Corporation |
Off-chip out of order memory allocation for a unified shader
|
US8413132B2
(en)
*
|
2010-09-13 |
2013-04-02 |
Samsung Electronics Co., Ltd. |
Techniques for resolving read-after-write (RAW) conflicts using backup area
|
JP6011194B2
(ja)
*
|
2012-09-21 |
2016-10-19 |
富士通株式会社 |
演算処理装置及び演算処理装置の制御方法
|
US9639469B2
(en)
*
|
2012-09-28 |
2017-05-02 |
Qualcomm Technologies, Inc. |
Coherency controller with reduced data buffer
|
US9563560B2
(en)
|
2012-09-28 |
2017-02-07 |
Qualcomm Technologies, Inc. |
Adaptive tuning of snoops
|
US9892803B2
(en)
*
|
2014-09-18 |
2018-02-13 |
Via Alliance Semiconductor Co., Ltd |
Cache management request fusing
|
CN107025184B
(zh)
*
|
2016-02-01 |
2021-03-16 |
深圳市中兴微电子技术有限公司 |
一种数据管理方法及装置
|
US11106466B2
(en)
*
|
2018-06-18 |
2021-08-31 |
International Business Machines Corporation |
Decoupling of conditional branches
|
US11321145B2
(en)
|
2019-06-27 |
2022-05-03 |
International Business Machines Corporation |
Ordering execution of an interrupt handler
|
US10831660B1
(en)
|
2019-06-27 |
2020-11-10 |
International Business Machines Corporation |
Ordering execution of an interrupt handler
|
US11003580B1
(en)
|
2020-04-30 |
2021-05-11 |
Seagate Technology Llc |
Managing overlapping reads and writes in a data cache
|