DE69934623D1 - Cachespeicherkohärenzmechanismus - Google Patents

Cachespeicherkohärenzmechanismus

Info

Publication number
DE69934623D1
DE69934623D1 DE69934623T DE69934623T DE69934623D1 DE 69934623 D1 DE69934623 D1 DE 69934623D1 DE 69934623 T DE69934623 T DE 69934623T DE 69934623 T DE69934623 T DE 69934623T DE 69934623 D1 DE69934623 D1 DE 69934623D1
Authority
DE
Germany
Prior art keywords
cache coherency
coherency mechanism
cache
coherency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69934623T
Other languages
English (en)
Inventor
Andrew Michael Jones
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
Original Assignee
SGS Thomson Microelectronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Ltd filed Critical SGS Thomson Microelectronics Ltd
Application granted granted Critical
Publication of DE69934623D1 publication Critical patent/DE69934623D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0837—Cache consistency protocols with software control, e.g. non-cacheable data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
DE69934623T 1998-03-23 1999-03-15 Cachespeicherkohärenzmechanismus Expired - Lifetime DE69934623D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GBGB9806184.9A GB9806184D0 (en) 1998-03-23 1998-03-23 A cache coherency mechanism

Publications (1)

Publication Number Publication Date
DE69934623D1 true DE69934623D1 (de) 2007-02-15

Family

ID=10829081

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69934623T Expired - Lifetime DE69934623D1 (de) 1998-03-23 1999-03-15 Cachespeicherkohärenzmechanismus

Country Status (4)

Country Link
US (1) US6351790B1 (de)
EP (1) EP0945805B1 (de)
DE (1) DE69934623D1 (de)
GB (1) GB9806184D0 (de)

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9704542D0 (en) * 1997-03-05 1997-04-23 Sgs Thomson Microelectronics A cache coherency mechanism
US6629207B1 (en) 1999-10-01 2003-09-30 Hitachi, Ltd. Method for loading instructions or data into a locked way of a cache memory
US6449712B1 (en) 1999-10-01 2002-09-10 Hitachi, Ltd. Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions
US7072817B1 (en) 1999-10-01 2006-07-04 Stmicroelectronics Ltd. Method of designing an initiator in an integrated circuit
US6591369B1 (en) 1999-10-01 2003-07-08 Stmicroelectronics, Ltd. System and method for communicating with an integrated circuit
US6567932B2 (en) 1999-10-01 2003-05-20 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6298394B1 (en) 1999-10-01 2001-10-02 Stmicroelectronics, Ltd. System and method for capturing information on an interconnect in an integrated circuit
US6463553B1 (en) 1999-10-01 2002-10-08 Stmicroelectronics, Ltd. Microcomputer debug architecture and method
US6553460B1 (en) 1999-10-01 2003-04-22 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US7000078B1 (en) 1999-10-01 2006-02-14 Stmicroelectronics Ltd. System and method for maintaining cache coherency in a shared memory system
US6598177B1 (en) 1999-10-01 2003-07-22 Stmicroelectronics Ltd. Monitoring error conditions in an integrated circuit
US6928073B2 (en) 1999-10-01 2005-08-09 Stmicroelectronics Ltd. Integrated circuit implementing packet transmission
US6412047B2 (en) * 1999-10-01 2002-06-25 Stmicroelectronics, Inc. Coherency protocol
US7260745B1 (en) 1999-10-01 2007-08-21 Stmicroelectronics Ltd. Detection of information on an interconnect
US6732307B1 (en) 1999-10-01 2004-05-04 Hitachi, Ltd. Apparatus and method for storing trace information
US6349371B1 (en) 1999-10-01 2002-02-19 Stmicroelectronics Ltd. Circuit for storing information
US6557119B1 (en) 1999-10-01 2003-04-29 Stmicroelectronics Limited Microcomputer debug architecture and method
US6701405B1 (en) 1999-10-01 2004-03-02 Hitachi, Ltd. DMA handshake protocol
US6487683B1 (en) 1999-10-01 2002-11-26 Stmicroelectronics Limited Microcomputer debug architecture and method
US6574651B1 (en) 1999-10-01 2003-06-03 Hitachi, Ltd. Method and apparatus for arithmetic operation on vectored data
US7793261B1 (en) 1999-10-01 2010-09-07 Stmicroelectronics Limited Interface for transferring debug information
US7266728B1 (en) 1999-10-01 2007-09-04 Stmicroelectronics Ltd. Circuit for monitoring information on an interconnect
US6460174B1 (en) 1999-10-01 2002-10-01 Stmicroelectronics, Ltd. Methods and models for use in designing an integrated circuit
US6665816B1 (en) 1999-10-01 2003-12-16 Stmicroelectronics Limited Data shift register
US6693914B1 (en) 1999-10-01 2004-02-17 Stmicroelectronics, Inc. Arbitration mechanism for packet transmission
US6546480B1 (en) 1999-10-01 2003-04-08 Hitachi, Ltd. Instructions for arithmetic operations on vectored data
US6408381B1 (en) 1999-10-01 2002-06-18 Hitachi, Ltd. Mechanism for fast access to control space in a pipeline processor
US6918065B1 (en) 1999-10-01 2005-07-12 Hitachi, Ltd. Method for compressing and decompressing trace information
US6598128B1 (en) 1999-10-01 2003-07-22 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6457118B1 (en) 1999-10-01 2002-09-24 Hitachi Ltd Method and system for selecting and using source operands in computer system instructions
US6502210B1 (en) 1999-10-01 2002-12-31 Stmicroelectronics, Ltd. Microcomputer debug architecture and method
US6820195B1 (en) 1999-10-01 2004-11-16 Hitachi, Ltd. Aligning load/store data with big/little endian determined rotation distance control
US6615370B1 (en) 1999-10-01 2003-09-02 Hitachi, Ltd. Circuit for storing trace information
US6351803B2 (en) 1999-10-01 2002-02-26 Hitachi Ltd. Mechanism for power efficient processing in a pipeline processor
US6590907B1 (en) 1999-10-01 2003-07-08 Stmicroelectronics Ltd. Integrated circuit with additional ports
US6826191B1 (en) 1999-10-01 2004-11-30 Stmicroelectronics Ltd. Packets containing transaction attributes
US6542983B1 (en) 1999-10-01 2003-04-01 Hitachi, Ltd. Microcomputer/floating point processor interface and method
US6779145B1 (en) 1999-10-01 2004-08-17 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6859891B2 (en) 1999-10-01 2005-02-22 Stmicroelectronics Limited Apparatus and method for shadowing processor information
US6633971B2 (en) 1999-10-01 2003-10-14 Hitachi, Ltd. Mechanism for forward data in a processor pipeline using a single pipefile connected to the pipeline
US6629115B1 (en) 1999-10-01 2003-09-30 Hitachi, Ltd. Method and apparatus for manipulating vectored data
US6772325B1 (en) * 1999-10-01 2004-08-03 Hitachi, Ltd. Processor architecture and operation for exploiting improved branch control instruction
US6601189B1 (en) 1999-10-01 2003-07-29 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6684348B1 (en) 1999-10-01 2004-01-27 Hitachi, Ltd. Circuit for processing trace information
US6412043B1 (en) 1999-10-01 2002-06-25 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6530047B1 (en) 1999-10-01 2003-03-04 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6694417B1 (en) * 2000-04-10 2004-02-17 International Business Machines Corporation Write pipeline and method of data transfer that sequentially accumulate a plurality of data granules for transfer in association with a single address
US6615321B2 (en) * 2001-02-12 2003-09-02 International Business Machines Corporation Mechanism for collapsing store misses in an SMP computer system
US6615320B2 (en) * 2001-02-12 2003-09-02 International Business Machines Corporation Store collapsing mechanism for SMP computer system
US7394823B2 (en) 2001-11-20 2008-07-01 Broadcom Corporation System having configurable interfaces for flexible system configurations
US7206879B2 (en) 2001-11-20 2007-04-17 Broadcom Corporation Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems
US6748479B2 (en) 2001-11-20 2004-06-08 Broadcom Corporation System having interfaces and switch that separates coherent and packet traffic
US6965973B2 (en) 2002-05-15 2005-11-15 Broadcom Corporation Remote line directory which covers subset of shareable CC-NUMA memory space
US7266587B2 (en) 2002-05-15 2007-09-04 Broadcom Corporation System having interfaces, switch, and memory bridge for CC-NUMA operation
US6993631B2 (en) 2002-05-15 2006-01-31 Broadcom Corporation L2 cache maintaining local ownership of remote coherency blocks
US7003631B2 (en) 2002-05-15 2006-02-21 Broadcom Corporation System having address-based intranode coherency and data-based internode coherency
US7934080B2 (en) * 2008-05-28 2011-04-26 Oracle America, Inc. Aggressive store merging in a processor that supports checkpointing
WO2009153703A1 (en) * 2008-06-17 2009-12-23 Nxp B.V. Multiprocessor system with mixed software hardware controlled cache management
KR102533241B1 (ko) 2018-01-25 2023-05-16 삼성전자주식회사 적응적으로 캐시 일관성을 제어하도록 구성된 이종 컴퓨팅 시스템

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4755930A (en) * 1985-06-27 1988-07-05 Encore Computer Corporation Hierarchical cache memory system and method
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
US5025365A (en) * 1988-11-14 1991-06-18 Unisys Corporation Hardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessors
EP0447145B1 (de) * 1990-03-12 2000-07-12 Hewlett-Packard Company Durch Anwender festgelegter direkter Speicherzugriff mit Anwendung von virtuellen Adressen
US5394555A (en) * 1992-12-23 1995-02-28 Bull Hn Information Systems Inc. Multi-node cluster computer system incorporating an external coherency unit at each node to insure integrity of information stored in a shared, distributed memory
US5978874A (en) * 1996-07-01 1999-11-02 Sun Microsystems, Inc. Implementing snooping on a split-transaction computer system bus
US6134634A (en) * 1996-12-20 2000-10-17 Texas Instruments Incorporated Method and apparatus for preemptive cache write-back
US6128706A (en) * 1998-02-03 2000-10-03 Institute For The Development Of Emerging Architectures, L.L.C. Apparatus and method for a load bias--load with intent to semaphore

Also Published As

Publication number Publication date
EP0945805B1 (de) 2007-01-03
EP0945805A1 (de) 1999-09-29
GB9806184D0 (en) 1998-05-20
US6351790B1 (en) 2002-02-26

Similar Documents

Publication Publication Date Title
DE69934623D1 (de) Cachespeicherkohärenzmechanismus
EP0667578A3 (de) Doppelter Abhörmechanismus für Cache-Speicher.
DE69915462D1 (de) Sehr leistungsstarker objektcache
DE69900821D1 (de) Modifizierter kurbelmechanismus
DE69530776D1 (de) Zweiwege set-assoziativer cache-speicher
ID28648A (id) Perangkat penyerapan inter-labial
GB9715399D0 (en) Cache coherency using path directories
DE59901964D1 (de) Wendestangenanordnung
DK1418174T3 (da) Amorf ritonavir
DE69910860D1 (de) Cache-Speicherkohärenzprotokoll mit Schwebe- (H) und vorigen (R) Zuständen
DE19983106T1 (de) Führungsmechanismus
SG93196A1 (en) Cache pollution avoidancd instructions
PT1076650E (pt) Compostos azapoliciclicos fundidos com arilo
GB0015276D0 (en) Coherence free cache
DE19981165T1 (de) Einstellmechanismus
DE69908202D1 (de) Cache-Speicherkohärenzprotokoll mit einem Schwebezustand
DE29903817U1 (de) Radiator-Konvektor-Einheit
DE69634464D1 (de) Cachespeicher
DE69808700T2 (de) Cachespeichervorrichtung
PT1102746E (pt) Fenilamidinas substituidas com accao antitrombotica
DE29816842U1 (de) Taubenvertreibungsvorrichtung
DE69928065D1 (de) Transfermechanismus
DE19980350D2 (de) Geschwindigkeitsoptimiertes Cachesystem
DE69723804D1 (de) Prozessor mit befehlscachespeicher
DE59808264D1 (de) Mehrprozessor-Steuervorrichtung

Legal Events

Date Code Title Description
8332 No legal effect for de