DE69723804D1 - Prozessor mit befehlscachespeicher - Google Patents

Prozessor mit befehlscachespeicher

Info

Publication number
DE69723804D1
DE69723804D1 DE69723804T DE69723804T DE69723804D1 DE 69723804 D1 DE69723804 D1 DE 69723804D1 DE 69723804 T DE69723804 T DE 69723804T DE 69723804 T DE69723804 T DE 69723804T DE 69723804 D1 DE69723804 D1 DE 69723804D1
Authority
DE
Germany
Prior art keywords
processor
command cache
cache
command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69723804T
Other languages
English (en)
Other versions
DE69723804T2 (de
Inventor
Michael Ang
Eino Jacobs
Hari Hampapuram
C Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
TRIMEDIA TECHNOLOGIES Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/649,732 external-priority patent/US5862398A/en
Priority claimed from US08/648,333 external-priority patent/US6131152A/en
Application filed by TRIMEDIA TECHNOLOGIES Inc filed Critical TRIMEDIA TECHNOLOGIES Inc
Application granted granted Critical
Publication of DE69723804D1 publication Critical patent/DE69723804D1/de
Publication of DE69723804T2 publication Critical patent/DE69723804T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69723804T 1996-05-15 1997-05-14 Prozessor mit befehlscachespeicher Expired - Lifetime DE69723804T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US08/649,732 US5862398A (en) 1996-05-15 1996-05-15 Compiler generating swizzled instructions usable in a simplified cache layout
US08/648,333 US6131152A (en) 1996-05-15 1996-05-15 Planar cache layout and instruction stream therefor
US649732 1996-05-15
US648333 1996-05-15
PCT/IB1997/000552 WO1997043715A2 (en) 1996-05-15 1997-05-14 Processor with an instruction cache

Publications (2)

Publication Number Publication Date
DE69723804D1 true DE69723804D1 (de) 2003-09-04
DE69723804T2 DE69723804T2 (de) 2004-05-27

Family

ID=27095356

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69723804T Expired - Lifetime DE69723804T2 (de) 1996-05-15 1997-05-14 Prozessor mit befehlscachespeicher

Country Status (5)

Country Link
EP (1) EP0846291B1 (de)
JP (1) JP3706633B2 (de)
CN (1) CN1145099C (de)
DE (1) DE69723804T2 (de)
WO (1) WO1997043715A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000070446A2 (en) * 1999-05-13 2000-11-23 Arc International U.S. Holdings Inc. Method and apparatus for loose register encoding within a pipelined processor
GB0400660D0 (en) * 2004-01-13 2004-02-11 Koninkl Philips Electronics Nv Method and related device for use in decoding executable code
US7296120B2 (en) * 2004-11-18 2007-11-13 International Business Machines Corporation Mechanism that provides efficient multi-word load atomicity

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5179680A (en) * 1987-04-20 1993-01-12 Digital Equipment Corporation Instruction storage and cache miss recovery in a high speed multiprocessing parallel processing apparatus
JP2810068B2 (ja) * 1988-11-11 1998-10-15 株式会社日立製作所 プロセッサシステム、コンピュータシステム及び命令処理方法
WO1991004536A1 (en) * 1989-09-20 1991-04-04 Dolphin Server Technology A/S Instruction cache architecture for parallel issuing of multiple instructions
WO1994010630A1 (en) * 1992-11-05 1994-05-11 The Commonwealth Of Australia Data formatter
WO1994027216A1 (en) * 1993-05-14 1994-11-24 Massachusetts Institute Of Technology Multiprocessor coupling system with integrated compile and run time scheduling for parallelism

Also Published As

Publication number Publication date
WO1997043715A3 (en) 1998-01-22
JPH11509663A (ja) 1999-08-24
EP0846291B1 (de) 2003-07-30
CN1145099C (zh) 2004-04-07
WO1997043715A2 (en) 1997-11-20
JP3706633B2 (ja) 2005-10-12
CN1197519A (zh) 1998-10-28
DE69723804T2 (de) 2004-05-27
EP0846291A2 (de) 1998-06-10

Similar Documents

Publication Publication Date Title
DE69529374D1 (de) Datenprozessor mit Teilassoziativer Einheit
DE69706271T2 (de) Integrierter Rechner mit Befehlsverfolgung
DE69530776D1 (de) Zweiwege set-assoziativer cache-speicher
DE69520512D1 (de) Halbleiterspeicher mit eingebautem Cachespeicher
DE69629383D1 (de) Superskalarer mikroprozessor mit risc86 befehlssatz
DE69721098T2 (de) Entwicklungsgerät
DE69208132D1 (de) Cache-Speichersteuerungsanordnung
DE69739744D1 (de) Cachespeichereffizienter Objektlader
DE69427734D1 (de) Linearadressierter Mikroprozessorcachespeicher
DE69720097T2 (de) Entwicklungsgerät
DE69715313D1 (de) Entwicklungsgerät
GB9715399D0 (en) Cache coherency using path directories
DE69735807D1 (de) Wendelantenne mit gebogenen segmenten
DE69711455D1 (de) Sojabohnen mit reduziertem linolensauregerat
DE59710022D1 (de) Prozessor mit Pipelining-Aufbau
DE69737116D1 (de) Mehrstufiger Cachespeicher
DE69726400D1 (de) Festkörper-datenprozessor mit vielseitiger mehrquellen-unterbrechungsorganisation
DE69715491T2 (de) Cache-Struktur mit mehreren Modi
DE59208307D1 (de) Zwischenspeicher
DE69634464D1 (de) Cachespeicher
DE69816784D1 (de) Prozessorbefehl mit Hashcodierung
DE69723804D1 (de) Prozessor mit befehlscachespeicher
DE59811771D1 (de) Faltenbalg mit imprägnierung
DE69330875T2 (de) Cachespeichervorrichtung.
DE69634465D1 (de) Cachespeicher

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL

R082 Change of representative

Ref document number: 846291

Country of ref document: EP

Representative=s name: MUELLER - HOFFMANN & PARTNER PATENTANWAELTE, 81667