DE69715491T2 - Cache-Struktur mit mehreren Modi - Google Patents

Cache-Struktur mit mehreren Modi

Info

Publication number
DE69715491T2
DE69715491T2 DE69715491T DE69715491T DE69715491T2 DE 69715491 T2 DE69715491 T2 DE 69715491T2 DE 69715491 T DE69715491 T DE 69715491T DE 69715491 T DE69715491 T DE 69715491T DE 69715491 T2 DE69715491 T2 DE 69715491T2
Authority
DE
Germany
Prior art keywords
multiple modes
cache structure
cache
modes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69715491T
Other languages
English (en)
Other versions
DE69715491D1 (de
Inventor
Dieter Spaderna
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Sharp Microelectronics Technology Inc
Original Assignee
Sharp Corp
Sharp Microelectronics Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp, Sharp Microelectronics Technology Inc filed Critical Sharp Corp
Application granted granted Critical
Publication of DE69715491D1 publication Critical patent/DE69715491D1/de
Publication of DE69715491T2 publication Critical patent/DE69715491T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/251—Local memory within processor subsystem
    • G06F2212/2515—Local memory within processor subsystem being configurable for different purposes, e.g. as cache or non-cache memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69715491T 1996-03-22 1997-03-03 Cache-Struktur mit mehreren Modi Expired - Lifetime DE69715491T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/621,010 US5687131A (en) 1996-03-22 1996-03-22 Multi-mode cache structure

Publications (2)

Publication Number Publication Date
DE69715491D1 DE69715491D1 (de) 2002-10-24
DE69715491T2 true DE69715491T2 (de) 2003-06-05

Family

ID=24488362

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69715491T Expired - Lifetime DE69715491T2 (de) 1996-03-22 1997-03-03 Cache-Struktur mit mehreren Modi

Country Status (6)

Country Link
US (1) US5687131A (de)
EP (1) EP0797148B1 (de)
JP (1) JPH09259038A (de)
KR (1) KR100258833B1 (de)
DE (1) DE69715491T2 (de)
TW (1) TW409208B (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6321318B1 (en) * 1997-12-31 2001-11-20 Texas Instruments Incorporated User-configurable on-chip program memory system
US6449690B1 (en) * 1999-06-25 2002-09-10 Hewlett-Packard Company Caching method using cache data stored in dynamic RAM embedded in logic chip and cache tag stored in static RAM external to logic chip
US6606686B1 (en) * 1999-07-15 2003-08-12 Texas Instruments Incorporated Unified memory system architecture including cache and directly addressable static random access memory
JP4434534B2 (ja) 2001-09-27 2010-03-17 株式会社東芝 プロセッサ・システム
US7117200B2 (en) * 2002-01-11 2006-10-03 International Business Machines Corporation Synthesizing information-bearing content from multiple channels
US6993617B2 (en) * 2002-05-01 2006-01-31 Sun Microsystems, Inc. System-on-a-chip having an on-chip processor and an on-chip dynamic random access memory (DRAM)
US6961807B1 (en) 2002-08-27 2005-11-01 Cypress Semiconductor Corporation Device, system and method for an integrated circuit adaptable for use in computing systems of differing memory requirements
EP1489490A3 (de) * 2003-06-19 2005-09-14 Texas Instruments Incorporated Verfahren zur Umwandlung eines Cachespeichers zu einem Notitzblockspeichers
JP4765249B2 (ja) * 2003-11-18 2011-09-07 セイコーエプソン株式会社 情報処理装置およびキャッシュメモリ制御方法
US9424198B2 (en) * 2012-11-30 2016-08-23 Intel Corporation Method, system and apparatus including logic to manage multiple memories as a unified exclusive memory
US20160224252A1 (en) * 2015-01-30 2016-08-04 Intel Corporation Hybrid memory architecture
EP3694202A1 (de) * 2019-02-11 2020-08-12 Prophesee Verfahren zur verarbeitung einer reihe von ereignissen, die asynchron aus einer matrix von pixeln eines ereignisbasierten lichtsensors empfangen wurden

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5363330A (en) * 1991-01-28 1994-11-08 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor memory device incorporating data latch and address counter for page mode programming
GB9118312D0 (en) * 1991-08-24 1991-10-09 Motorola Inc Real time cache implemented by dual purpose on-chip memory
US5410669A (en) * 1993-04-05 1995-04-25 Motorola, Inc. Data processor having a cache memory capable of being used as a linear ram bank
KR970002076B1 (ko) * 1994-06-09 1997-02-22 김진환 승용차의 문짝 자동개폐장치

Also Published As

Publication number Publication date
KR100258833B1 (ko) 2000-06-15
US5687131A (en) 1997-11-11
EP0797148A1 (de) 1997-09-24
KR970067364A (ko) 1997-10-13
TW409208B (en) 2000-10-21
EP0797148B1 (de) 2002-09-18
JPH09259038A (ja) 1997-10-03
DE69715491D1 (de) 2002-10-24

Similar Documents

Publication Publication Date Title
DE69535257D1 (de) Verbundmaterial mit kontrollierter Elastizität
DE69637892D1 (de) Anordnung mit Alpha-Hexathienyl
ID21031A (id) Kornea buatan
DE69719362T2 (de) Mit reinigungsmitteln imprägnierter gegenstand
DE69637610D1 (de) Nachrichtensystem mit Zwischenspeicher
DE59710628D1 (de) Starres endoskop mit beleuchtung
DE69735807D1 (de) Wendelantenne mit gebogenen segmenten
DE69711455D1 (de) Sojabohnen mit reduziertem linolensauregerat
DE69718820D1 (de) Micropumpe mit eingebautem zwischenstück
DE69736429D1 (de) Tunneleffektmessaufnehmer mit linearer kraftrückkopplung
DE69715491T2 (de) Cache-Struktur mit mehreren Modi
FI101860B1 (fi) Sovitelma anestesiahöyrystimen yhteydessä
DE69534365D1 (de) Drehschwingungsdämpfer mit mehreren reibungsstufen
ID16697A (id) Penghubung berkepadatan tinggi dengan kemampuan tinggi
BR9711708A (pt) Estrutura de suporte de carga
BR9707770A (pt) Tifluzamida com eficácia aperfeiçoada
DE69728231D1 (de) Firststruktur
KR970049457U (ko) 1인승 자전거 겸용한 2인승 자전거
DE69714970D1 (de) Hydroismerisierung mit verminderten hydrokracken
DE59911463D1 (de) Fahrzeugleitvorrichtung mit Fahrstreckenabtastung
DE69723804D1 (de) Prozessor mit befehlscachespeicher
FR2753734B1 (fr) Corniche cache reseaux
DE69722105D1 (de) Tiefkühltruhe mit Beleuchtungsvorrichtung
KR970049347U (ko) 이중 구조체를 갖는 타이어
KR970059616U (ko) 조명장치를 갖는 광고판

Legal Events

Date Code Title Description
8364 No opposition during term of opposition