DE69030072D1 - Schneller Durchschreib-Cache-Speicher - Google Patents
Schneller Durchschreib-Cache-SpeicherInfo
- Publication number
- DE69030072D1 DE69030072D1 DE69030072T DE69030072T DE69030072D1 DE 69030072 D1 DE69030072 D1 DE 69030072D1 DE 69030072 T DE69030072 T DE 69030072T DE 69030072 T DE69030072 T DE 69030072T DE 69030072 D1 DE69030072 D1 DE 69030072D1
- Authority
- DE
- Germany
- Prior art keywords
- cache
- fast write
- write
- fast
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0855—Overlapped cache accessing, e.g. pipeline
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0884—Parallel mode, e.g. in parallel with main memory or CPU
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/468,048 US5206941A (en) | 1990-01-22 | 1990-01-22 | Fast store-through cache memory |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69030072D1 true DE69030072D1 (de) | 1997-04-10 |
DE69030072T2 DE69030072T2 (de) | 1997-09-18 |
Family
ID=23858238
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69030072T Expired - Fee Related DE69030072T2 (de) | 1990-01-22 | 1990-12-12 | Schneller Durchschreib-Cache-Speicher |
Country Status (4)
Country | Link |
---|---|
US (1) | US5206941A (de) |
EP (1) | EP0438960B1 (de) |
JP (1) | JPH03225542A (de) |
DE (1) | DE69030072T2 (de) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5428761A (en) * | 1992-03-12 | 1995-06-27 | Digital Equipment Corporation | System for achieving atomic non-sequential multi-word operations in shared memory |
EP0624844A2 (de) * | 1993-05-11 | 1994-11-17 | International Business Machines Corporation | Völlig integrierte Cache-Speicherarchitektur |
KR970010368B1 (ko) * | 1994-01-18 | 1997-06-25 | 삼성전자 주식회사 | 캐시라인 리프레이스장치 및 방법 |
US5553264A (en) * | 1994-06-24 | 1996-09-03 | Digital Equipment Corporation | Method and apparatus for efficient cache refilling by the use of forced cache misses |
US5537575A (en) * | 1994-06-30 | 1996-07-16 | Foley; Denis | System for handling cache memory victim data which transfers data from cache to the interface while CPU performs a cache lookup using cache status information |
EP0713181A1 (de) * | 1994-11-16 | 1996-05-22 | International Business Machines Corporation | Datenverarbeitungssystem mit Einrichtung zur Speicherung von Adress-Etiketten |
US5895496A (en) * | 1994-11-18 | 1999-04-20 | Apple Computer, Inc. | System for an method of efficiently controlling memory accesses in a multiprocessor computer system |
USRE38514E1 (en) | 1994-11-18 | 2004-05-11 | Apple Computer, Inc. | System for and method of efficiently controlling memory accesses in a multiprocessor computer system |
US5737756A (en) * | 1995-04-28 | 1998-04-07 | Unisys Corporation | Dual bus computer network using dual busses with dual spy modules enabling clearing of invalidation queue for processor with store through cache while providing retry cycles for incomplete accesses to invalidation queue |
JP2964926B2 (ja) * | 1995-08-29 | 1999-10-18 | 富士ゼロックス株式会社 | データベース管理装置及び方法 |
US6085288A (en) * | 1997-04-14 | 2000-07-04 | International Business Machines Corporation | Dual cache directories with respective queue independently executing its content and allowing staggered write operations |
JPH10340226A (ja) * | 1997-06-09 | 1998-12-22 | Nec Corp | 連想記憶方式のキャッシュメモリ |
US6023747A (en) * | 1997-12-17 | 2000-02-08 | International Business Machines Corporation | Method and system for handling conflicts between cache operation requests in a data processing system |
US7065050B1 (en) * | 1998-07-08 | 2006-06-20 | Broadcom Corporation | Apparatus and method for controlling data flow in a network switch |
WO2013058745A1 (en) * | 2011-10-18 | 2013-04-25 | Soft Machines, Inc. | Methods and systems for managing synonyms in virtually indexed physically tagged caches |
WO2013095477A1 (en) | 2011-12-22 | 2013-06-27 | Intel Corporation | Apparatus and method for detecting and recovering from data fetch errors |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3771137A (en) * | 1971-09-10 | 1973-11-06 | Ibm | Memory control in a multipurpose system utilizing a broadcast |
US4345309A (en) * | 1980-01-28 | 1982-08-17 | Digital Equipment Corporation | Relating to cached multiprocessor system with pipeline timing |
US4332010A (en) * | 1980-03-17 | 1982-05-25 | International Business Machines Corporation | Cache synonym detection and handling mechanism |
US4439829A (en) * | 1981-01-07 | 1984-03-27 | Wang Laboratories, Inc. | Data processing machine with improved cache memory management |
US4484267A (en) * | 1981-12-30 | 1984-11-20 | International Business Machines Corporation | Cache sharing control in a multiprocessor |
DE3382152D1 (de) * | 1982-12-09 | 1991-03-07 | Sequoia Systems Inc | Sicherstellungsspeichersystem. |
US4819154A (en) * | 1982-12-09 | 1989-04-04 | Sequoia Systems, Inc. | Memory back up system with one cache memory and two physically separated main memories |
WO1984002799A1 (en) * | 1982-12-30 | 1984-07-19 | Ibm | A hierarchical memory system including separate cache memories for storing data and instructions |
US4695951A (en) * | 1983-07-07 | 1987-09-22 | Honeywell Bull Inc. | Computer hierarchy control |
US4831622A (en) * | 1987-12-22 | 1989-05-16 | Honeywell Bull Inc. | Apparatus for forcing a reload from main memory upon cache memory error |
-
1990
- 1990-01-22 US US07/468,048 patent/US5206941A/en not_active Expired - Fee Related
- 1990-11-30 JP JP2336885A patent/JPH03225542A/ja active Granted
- 1990-12-12 EP EP90480215A patent/EP0438960B1/de not_active Expired - Lifetime
- 1990-12-12 DE DE69030072T patent/DE69030072T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0438960A3 (en) | 1992-09-02 |
US5206941A (en) | 1993-04-27 |
JPH0532775B2 (de) | 1993-05-17 |
EP0438960A2 (de) | 1991-07-31 |
DE69030072T2 (de) | 1997-09-18 |
JPH03225542A (ja) | 1991-10-04 |
EP0438960B1 (de) | 1997-03-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |