SG45415A1 - A cache computer system that minimizes invalidation and copybac operations - Google Patents

A cache computer system that minimizes invalidation and copybac operations

Info

Publication number
SG45415A1
SG45415A1 SG1996006609A SG1996006609A SG45415A1 SG 45415 A1 SG45415 A1 SG 45415A1 SG 1996006609 A SG1996006609 A SG 1996006609A SG 1996006609 A SG1996006609 A SG 1996006609A SG 45415 A1 SG45415 A1 SG 45415A1
Authority
SG
Singapore
Prior art keywords
copybac
invalidation
minimizes
operations
computer system
Prior art date
Application number
SG1996006609A
Other languages
English (en)
Inventor
Satyanarayana Nishtala
Zahir Ebrahim
Van William C Loo
Kevin B Rmoyle
Leslie Kohn
Louis F Coffin
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of SG45415A1 publication Critical patent/SG45415A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0822—Copy directories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
SG1996006609A 1995-03-31 1996-03-29 A cache computer system that minimizes invalidation and copybac operations SG45415A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US42301695A 1995-03-31 1995-03-31

Publications (1)

Publication Number Publication Date
SG45415A1 true SG45415A1 (en) 1998-01-16

Family

ID=23677349

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1996006609A SG45415A1 (en) 1995-03-31 1996-03-29 A cache computer system that minimizes invalidation and copybac operations

Country Status (5)

Country Link
US (1) US5706463A (ja)
EP (1) EP0735480B1 (ja)
JP (1) JP3784101B2 (ja)
DE (1) DE69628493T2 (ja)
SG (1) SG45415A1 (ja)

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US6857051B2 (en) * 1998-12-23 2005-02-15 Intel Corporation Method and apparatus for maintaining cache coherence in a computer system
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US6345342B1 (en) * 1999-11-09 2002-02-05 International Business Machines Corporation Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line
US6519685B1 (en) * 1999-12-22 2003-02-11 Intel Corporation Cache states for multiprocessor cache coherency protocols
US6745297B2 (en) * 2000-10-06 2004-06-01 Broadcom Corporation Cache coherent protocol in which exclusive and modified data is transferred to requesting agent from snooping agent
US20030115402A1 (en) * 2001-11-16 2003-06-19 Fredrik Dahlgren Multiprocessor system
US20040117669A1 (en) * 2002-12-12 2004-06-17 Wilson Peter A. Method for controlling heat dissipation of a microprocessor
US20040199727A1 (en) * 2003-04-02 2004-10-07 Narad Charles E. Cache allocation
US7284097B2 (en) * 2003-09-30 2007-10-16 International Business Machines Corporation Modified-invalid cache state to reduce cache-to-cache data transfer operations for speculatively-issued full cache line writes
US8145847B2 (en) * 2004-01-20 2012-03-27 Hewlett-Packard Development Company, L.P. Cache coherency protocol with ordering points
US7395374B2 (en) * 2004-01-20 2008-07-01 Hewlett-Packard Company, L.P. System and method for conflict responses in a cache coherency protocol with ordering point migration
US8090914B2 (en) * 2004-01-20 2012-01-03 Hewlett-Packard Development Company, L.P. System and method for creating ordering points
US7769959B2 (en) 2004-01-20 2010-08-03 Hewlett-Packard Development Company, L.P. System and method to facilitate ordering point migration to memory
US7818391B2 (en) 2004-01-20 2010-10-19 Hewlett-Packard Development Company, L.P. System and method to facilitate ordering point migration
US20050160238A1 (en) * 2004-01-20 2005-07-21 Steely Simon C.Jr. System and method for conflict responses in a cache coherency protocol with ordering point migration
US7620696B2 (en) * 2004-01-20 2009-11-17 Hewlett-Packard Development Company, L.P. System and method for conflict responses in a cache coherency protocol
US8176259B2 (en) 2004-01-20 2012-05-08 Hewlett-Packard Development Company, L.P. System and method for resolving transactions in a cache coherency protocol
US8468308B2 (en) * 2004-01-20 2013-06-18 Hewlett-Packard Development Company, L.P. System and method for non-migratory requests in a cache coherency protocol
US8332592B2 (en) * 2004-10-08 2012-12-11 International Business Machines Corporation Graphics processor with snoop filter
WO2007094038A1 (ja) * 2006-02-13 2007-08-23 Fujitsu Limited システム制御装置、キャッシュ制御装置およびキャッシュ状態遷移制御方法
WO2007099583A1 (ja) 2006-02-28 2007-09-07 Fujitsu Limited システムコントローラおよびキャッシュ制御方法
US20070283095A1 (en) * 2006-06-06 2007-12-06 Alcor Micro, Corp. Method to access storage device through universal serial bus
JP4912790B2 (ja) * 2006-08-18 2012-04-11 富士通株式会社 システムコントローラ，スヌープタグ更新方法および情報処理装置
US7613882B1 (en) 2007-01-29 2009-11-03 3 Leaf Systems Fast invalidation for cache coherency in distributed shared memory system
JP5393964B2 (ja) * 2007-09-11 2014-01-22 中菱エンジニアリング株式会社 車両試験装置
JP5568939B2 (ja) 2009-10-08 2014-08-13 富士通株式会社 演算処理装置及び制御方法
US8904115B2 (en) * 2010-09-28 2014-12-02 Texas Instruments Incorporated Cache with multiple access pipelines
JP5974720B2 (ja) * 2012-08-09 2016-08-23 富士通株式会社 演算処理装置、情報処理装置および情報処理装置の制御方法
JP5971036B2 (ja) * 2012-08-30 2016-08-17 富士通株式会社 演算処理装置及び演算処理装置の制御方法
US9418035B2 (en) * 2012-10-22 2016-08-16 Intel Corporation High performance interconnect physical layer
US9584617B2 (en) * 2013-12-31 2017-02-28 Successfactors, Inc. Allocating cache request in distributed cache system based upon cache object and marker identifying mission critical data
US9823730B2 (en) * 2015-07-08 2017-11-21 Apple Inc. Power management of cache duplicate tags

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Also Published As

Publication number Publication date
DE69628493T2 (de) 2004-05-19
DE69628493D1 (de) 2003-07-10
US5706463A (en) 1998-01-06
JPH0922383A (ja) 1997-01-21
EP0735480B1 (en) 2003-06-04
JP3784101B2 (ja) 2006-06-07
EP0735480A1 (en) 1996-10-02

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