SG44432A1 - Bus interface logic for computer system having dual bus architecture - Google Patents

Bus interface logic for computer system having dual bus architecture

Info

Publication number
SG44432A1
SG44432A1 SG1996000366A SG1996000366A SG44432A1 SG 44432 A1 SG44432 A1 SG 44432A1 SG 1996000366 A SG1996000366 A SG 1996000366A SG 1996000366 A SG1996000366 A SG 1996000366A SG 44432 A1 SG44432 A1 SG 44432A1
Authority
SG
Singapore
Prior art keywords
computer system
interface logic
bus
dual
bus interface
Prior art date
Application number
SG1996000366A
Other languages
English (en)
Inventor
Alferdo Alderegula
Nader Amini
Richard Louis Horne
Terence Joseph Lohman
Cang Ngoc Tran
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of SG44432A1 publication Critical patent/SG44432A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
SG1996000366A 1992-01-02 1992-12-22 Bus interface logic for computer system having dual bus architecture SG44432A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/816,203 US5255374A (en) 1992-01-02 1992-01-02 Bus interface logic for computer system having dual bus architecture

Publications (1)

Publication Number Publication Date
SG44432A1 true SG44432A1 (en) 1997-12-19

Family

ID=25219957

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1996000366A SG44432A1 (en) 1992-01-02 1992-12-22 Bus interface logic for computer system having dual bus architecture

Country Status (10)

Country Link
US (1) US5255374A (zh)
EP (1) EP0553563A1 (zh)
JP (1) JPH05242015A (zh)
KR (1) KR960012356B1 (zh)
CN (1) CN1029169C (zh)
AU (1) AU652707B2 (zh)
MY (1) MY109414A (zh)
NZ (1) NZ245346A (zh)
SG (1) SG44432A1 (zh)
TW (1) TW243508B (zh)

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Also Published As

Publication number Publication date
KR930016886A (ko) 1993-08-30
AU652707B2 (en) 1994-09-01
NZ245346A (en) 1995-09-26
JPH05242015A (ja) 1993-09-21
TW243508B (zh) 1995-03-21
CN1029169C (zh) 1995-06-28
AU2979592A (en) 1993-07-08
EP0553563A1 (en) 1993-08-04
US5255374A (en) 1993-10-19
KR960012356B1 (ko) 1996-09-18
MY109414A (en) 1997-01-31
CN1074051A (zh) 1993-07-07

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