SG188195A1 - Methods of forming through wafer interconnects in semiconductor structures using sacrificial material, and semiconductor structures formed by such methods - Google Patents

Methods of forming through wafer interconnects in semiconductor structures using sacrificial material, and semiconductor structures formed by such methods Download PDF

Info

Publication number
SG188195A1
SG188195A1 SG2013008750A SG2013008750A SG188195A1 SG 188195 A1 SG188195 A1 SG 188195A1 SG 2013008750 A SG2013008750 A SG 2013008750A SG 2013008750 A SG2013008750 A SG 2013008750A SG 188195 A1 SG188195 A1 SG 188195A1
Authority
SG
Singapore
Prior art keywords
semiconductor structure
semiconductor
substrate
forming
thin layer
Prior art date
Application number
SG2013008750A
Other languages
English (en)
Inventor
Mariam Sadaka
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/879,637 external-priority patent/US20120061794A1/en
Priority claimed from FR1057676A external-priority patent/FR2965397A1/fr
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG188195A1 publication Critical patent/SG188195A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Element Separation (AREA)
SG2013008750A 2010-09-10 2011-09-12 Methods of forming through wafer interconnects in semiconductor structures using sacrificial material, and semiconductor structures formed by such methods SG188195A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/879,637 US20120061794A1 (en) 2010-09-10 2010-09-10 Methods of forming through wafer interconnects in semiconductor structures using sacrificial material, and semiconductor structures formed by such methods
FR1057676A FR2965397A1 (fr) 2010-09-23 2010-09-23 Procédés de formation de trous d'interconnexion a travers la tranche dans des structures semi-conductrices au moyen de matériau sacrificiel, et structures semi-conductrices formées par de tels procédés.
PCT/EP2011/065778 WO2012048973A1 (en) 2010-09-10 2011-09-12 Methods of forming through wafer interconnects in semiconductor structures using sacrificial material, and semiconductor structures formed by such methods

Publications (1)

Publication Number Publication Date
SG188195A1 true SG188195A1 (en) 2013-04-30

Family

ID=45937917

Family Applications (1)

Application Number Title Priority Date Filing Date
SG2013008750A SG188195A1 (en) 2010-09-10 2011-09-12 Methods of forming through wafer interconnects in semiconductor structures using sacrificial material, and semiconductor structures formed by such methods

Country Status (7)

Country Link
JP (1) JP2013537363A (zh)
KR (1) KR20130093627A (zh)
CN (1) CN103081090A (zh)
DE (1) DE112011103040T5 (zh)
SG (1) SG188195A1 (zh)
TW (1) TW201214627A (zh)
WO (1) WO2012048973A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8859425B2 (en) 2012-10-15 2014-10-14 Micron Technology, Inc. Devices, systems, and methods related to forming through-substrate vias with sacrificial plugs
CN105185738B (zh) * 2014-06-20 2018-10-23 中芯国际集成电路制造(上海)有限公司 一种半导体器件以及制备方法、电子装置
US9899260B2 (en) 2016-01-21 2018-02-20 Micron Technology, Inc. Method for fabricating a semiconductor device
DE112016006659T5 (de) * 2016-05-27 2018-12-13 Intel Corporation Damaszierte Stopfen- und Zungenstrukturbildung mittels Photobuckets für auf Abstandhalter basierende Back-End-of-Line (BEOL)-Verbindungen
US20230121210A1 (en) * 2021-10-12 2023-04-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor Device and Method

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US39484A (en) 1863-08-11 Improved smoothing-iron
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
FR2755537B1 (fr) 1996-11-05 1999-03-05 Commissariat Energie Atomique Procede de fabrication d'un film mince sur un support et structure ainsi obtenue
FR2767416B1 (fr) 1997-08-12 1999-10-01 Commissariat Energie Atomique Procede de fabrication d'un film mince de materiau solide
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
FR2795865B1 (fr) 1999-06-30 2001-08-17 Commissariat Energie Atomique Procede de realisation d'un film mince utilisant une mise sous pression
FR2818010B1 (fr) 2000-12-08 2003-09-05 Commissariat Energie Atomique Procede de realisation d'une couche mince impliquant l'introduction d'especes gazeuses
JP3535461B2 (ja) * 2001-01-10 2004-06-07 新光電気工業株式会社 半導体装置の製造方法及び半導体装置
US7960290B2 (en) * 2007-05-02 2011-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a semiconductor device
US7846837B2 (en) * 2008-10-09 2010-12-07 United Microelectronics Corp. Through substrate via process
US7923369B2 (en) * 2008-11-25 2011-04-12 Freescale Semiconductor, Inc. Through-via and method of forming

Also Published As

Publication number Publication date
WO2012048973A1 (en) 2012-04-19
DE112011103040T5 (de) 2013-07-04
KR20130093627A (ko) 2013-08-22
JP2013537363A (ja) 2013-09-30
TW201214627A (en) 2012-04-01
CN103081090A (zh) 2013-05-01

Similar Documents

Publication Publication Date Title
US20200168584A1 (en) Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods
US20120061794A1 (en) Methods of forming through wafer interconnects in semiconductor structures using sacrificial material, and semiconductor structures formed by such methods
US10163864B1 (en) Vertically stacked wafers and methods of forming same
US9391011B2 (en) Semiconductor structures including fluidic microchannels for cooling and related methods
US20180374751A1 (en) Novel 3D Integration Method Using SOI Substrates and Structures Produced Thereby
US8525343B2 (en) Device with through-silicon via (TSV) and method of forming the same
TW202331983A (zh) 擴散屏障及其形成方法
US8987137B2 (en) Method of fabrication of through-substrate vias
KR101426362B1 (ko) 접합 반도체 구조 형성 방법 및 그 방법에 의해 형성된 반도체 구조
TWI445101B (zh) 暫時性半導體結構接合方法及相關經接合的半導體結構
US20100090317A1 (en) Interconnect Structures and Methods
US11328927B2 (en) System for integration of elemental and compound semiconductors on a ceramic substrate
JP2010157741A (ja) スカロップ状側壁を有するシリコン貫通ビア
US10074567B2 (en) Method and system for vertical integration of elemental and compound semiconductors
US8853077B2 (en) Through silicon via packaging structures and fabrication method
SG188195A1 (en) Methods of forming through wafer interconnects in semiconductor structures using sacrificial material, and semiconductor structures formed by such methods
US8629061B2 (en) Method for three-dimensional packaging of electronic devices
CN114864545A (zh) 半导体装置的制造方法
FR2965397A1 (fr) Procédés de formation de trous d'interconnexion a travers la tranche dans des structures semi-conductrices au moyen de matériau sacrificiel, et structures semi-conductrices formées par de tels procédés.