SG151225A1 - Data storage and processing algorithm for placement of multi - level flash cell (mlc) vt - Google Patents

Data storage and processing algorithm for placement of multi - level flash cell (mlc) vt

Info

Publication number
SG151225A1
SG151225A1 SG200807085-6A SG2008070856A SG151225A1 SG 151225 A1 SG151225 A1 SG 151225A1 SG 2008070856 A SG2008070856 A SG 2008070856A SG 151225 A1 SG151225 A1 SG 151225A1
Authority
SG
Singapore
Prior art keywords
placement
mlc
data storage
processing algorithm
level flash
Prior art date
Application number
SG200807085-6A
Other languages
English (en)
Inventor
Rezaul Haque
Darshak A Udeshi
Karthi Ramamurthi
Nathan C Chrisman
Aliasgar S Madraswala
Kevin P Flanagan
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of SG151225A1 publication Critical patent/SG151225A1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
SG200807085-6A 2007-09-25 2008-09-23 Data storage and processing algorithm for placement of multi - level flash cell (mlc) vt SG151225A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/861,240 US7710781B2 (en) 2007-09-25 2007-09-25 Data storage and processing algorithm for placement of multi-level flash cell (MLC) VT

Publications (1)

Publication Number Publication Date
SG151225A1 true SG151225A1 (en) 2009-04-30

Family

ID=40471403

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200807085-6A SG151225A1 (en) 2007-09-25 2008-09-23 Data storage and processing algorithm for placement of multi - level flash cell (mlc) vt

Country Status (4)

Country Link
US (1) US7710781B2 (zh)
CN (1) CN101414486B (zh)
SG (1) SG151225A1 (zh)
TW (1) TWI396201B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8739010B2 (en) * 2010-11-19 2014-05-27 Altera Corporation Memory array with redundant bits and memory element voting circuits
US8670273B2 (en) 2011-08-05 2014-03-11 Micron Technology, Inc. Methods for program verifying a memory cell and memory devices configured to perform the same
US8923068B2 (en) 2012-10-30 2014-12-30 Micron Technology, Inc. Low margin read operation with CRC comparision
CN106953777A (zh) * 2016-01-06 2017-07-14 中兴通讯股份有限公司 一种实现报文检错的方法及装置
US10109361B1 (en) 2017-06-29 2018-10-23 Intel Corporation Coarse pass and fine pass multi-level NVM programming

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3090066B2 (ja) * 1996-10-29 2000-09-18 日本電気株式会社 多値不揮発性半導体メモリ
KR100255957B1 (ko) * 1997-07-29 2000-05-01 윤종용 전기적으로 소거 및 프로그램 가능한 메모리 셀들을 구비한반도체 메모리 장치
US6044019A (en) * 1998-10-23 2000-03-28 Sandisk Corporation Non-volatile memory with improved sensing and method therefor
JP3905990B2 (ja) * 1998-12-25 2007-04-18 株式会社東芝 記憶装置とその記憶方法
JP2001093288A (ja) * 1999-09-20 2001-04-06 Toshiba Corp 不揮発性半導体記憶装置
JP2002063793A (ja) * 2000-08-18 2002-02-28 Fujitsu Ltd 半導体記憶装置の読み出し装置および読み出し方法
KR100390959B1 (ko) * 2001-06-29 2003-07-12 주식회사 하이닉스반도체 센싱회로를 이용한 멀티레벨 플래시 메모리 프로그램/리드방법
JP3940570B2 (ja) * 2001-07-06 2007-07-04 株式会社東芝 半導体記憶装置
US6621739B2 (en) * 2002-01-18 2003-09-16 Sandisk Corporation Reducing the effects of noise in non-volatile memories through multiple reads
JP4260434B2 (ja) * 2002-07-16 2009-04-30 富士通マイクロエレクトロニクス株式会社 不揮発性半導体メモリ及びその動作方法
US6678197B1 (en) * 2002-10-18 2004-01-13 Hewlett-Packard Development Company, L.P. Systems and methods for reducing the effect of noise while reading data from memory
US7031192B1 (en) * 2002-11-08 2006-04-18 Halo Lsi, Inc. Non-volatile semiconductor memory and driving method
JP3920768B2 (ja) * 2002-12-26 2007-05-30 株式会社東芝 不揮発性半導体メモリ
WO2004097839A1 (ja) * 2003-04-28 2004-11-11 Fujitsu Limited 不揮発性半導体記憶装置及び不揮発性半導体記憶装置のプログラム方法
KR100624300B1 (ko) * 2005-06-29 2006-09-19 주식회사 하이닉스반도체 프로그램 시간을 감소시키는 플래시 메모리 장치의프로그램 동작 제어 방법

Also Published As

Publication number Publication date
CN101414486A (zh) 2009-04-22
TW200935430A (en) 2009-08-16
TWI396201B (zh) 2013-05-11
US20090080248A1 (en) 2009-03-26
CN101414486B (zh) 2013-05-01
US7710781B2 (en) 2010-05-04

Similar Documents

Publication Publication Date Title
EP1929482A4 (en) PORTABLE DATA STORAGE USING SLC AND MLC FLASH MEMORY
GB2473348A (en) Apparatus and method for multi-level cache utilization
TWI339841B (en) Nand flash memory device and method of improving characteristic of a cell in the same
TW200632626A (en) Peripheral devices for portable computer
SG151225A1 (en) Data storage and processing algorithm for placement of multi - level flash cell (mlc) vt
TW201614651A (en) Apparatuses and methods for performing an exclusive or operation using sensing circuitry
MX2009001345A (es) Elemento y metodo de almacenamiento de estado solido.
TW201612906A (en) Apparatuses and methods for parity determination using sensing circuitry
TW200703342A (en) Erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells
TW200707189A (en) Memory block erasing in a flash memory device
EP2398022A3 (en) Logic-based multiple time programming memory cell
IL185307A0 (en) Direct data file storage implementation techniques in flash memories
GB0510188D0 (en) Memory management in a computing device
WO2009072102A3 (en) System and methods employing mock thresholds to generate actual reading thresholds in flash memory devices
IL210397A0 (en) Methods and apparatus for read-side intercell interference mitigation in flash memories
TWI370459B (en) Method and system for adaptively finding reference voltages for reading data from a mlc flash memory
TW200703340A (en) Soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells
GB2498874B (en) Implementing enhanced data partial-erase for multi-level cell (MLC) memory using moving baseline memory data encoding
WO2010075174A3 (en) System and method for providing content to a mobile device
TW200731267A (en) Semiconductor memory device controlling program voltage according to the number of cells to be programmed and method of programming the same
WO2007143670A3 (en) Electronic card type media storage and player device
EP2779175A3 (en) Retention check logic for non-volatile memory
SG10201909143XA (en) Storage device using buffer memory in read reclaim operation
SG165253A1 (en) Portable electronic apparatus and portable terminal system
EP1967977A3 (en) Method and apparatus for protecting flash memory