SG122865A1 - A damascene interconnect structure with cap layer - Google Patents
A damascene interconnect structure with cap layerInfo
- Publication number
- SG122865A1 SG122865A1 SG200502032A SG200502032A SG122865A1 SG 122865 A1 SG122865 A1 SG 122865A1 SG 200502032 A SG200502032 A SG 200502032A SG 200502032 A SG200502032 A SG 200502032A SG 122865 A1 SG122865 A1 SG 122865A1
- Authority
- SG
- Singapore
- Prior art keywords
- cap layer
- interconnect structure
- damascene interconnect
- damascene
- cap
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/004,767 US7259463B2 (en) | 2004-12-03 | 2004-12-03 | Damascene interconnect structure with cap layer |
Publications (1)
Publication Number | Publication Date |
---|---|
SG122865A1 true SG122865A1 (en) | 2006-06-29 |
Family
ID=36573279
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG200502032A SG122865A1 (en) | 2004-12-03 | 2005-04-04 | A damascene interconnect structure with cap layer |
Country Status (4)
Country | Link |
---|---|
US (1) | US7259463B2 (zh) |
CN (1) | CN100424867C (zh) |
SG (1) | SG122865A1 (zh) |
TW (1) | TWI246741B (zh) |
Families Citing this family (46)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2006210508A (ja) * | 2005-01-26 | 2006-08-10 | Sony Corp | 半導体装置およびその製造方法 |
US7320934B2 (en) * | 2005-06-20 | 2008-01-22 | Infineon Technologies Ag | Method of forming a contact in a flash memory device |
US7727885B2 (en) * | 2006-08-29 | 2010-06-01 | Texas Instruments Incorporated | Reduction of punch-thru defects in damascene processing |
JP2008060243A (ja) * | 2006-08-30 | 2008-03-13 | Nec Electronics Corp | 半導体装置およびその製造方法 |
US20080054466A1 (en) * | 2006-08-31 | 2008-03-06 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing semiconductor device |
US7521358B2 (en) * | 2006-12-26 | 2009-04-21 | Lam Research Corporation | Process integration scheme to lower overall dielectric constant in BEoL interconnect structures |
DE102007004860B4 (de) * | 2007-01-31 | 2008-11-06 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer Kupfer-basierten Metallisierungsschicht mit einer leitenden Deckschicht durch ein verbessertes Integrationsschema |
US7655556B2 (en) * | 2007-03-23 | 2010-02-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures for semiconductor devices |
DE102007035834A1 (de) * | 2007-07-31 | 2009-02-05 | Advanced Micro Devices, Inc., Sunnyvale | Halbleiterbauelement mit lokal erhöhtem Elektromigrationswiderstand in einer Verbindungsstruktur |
DE102008021568B3 (de) | 2008-04-30 | 2010-02-04 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Reduzieren der Erosion einer Metalldeckschicht während einer Kontaktlochstrukturierung in Halbleiterbauelementen und Halbleiterbauelement mit einem schützenden Material zum Reduzieren der Erosion der Metalldeckschicht |
US8361237B2 (en) * | 2008-12-17 | 2013-01-29 | Air Products And Chemicals, Inc. | Wet clean compositions for CoWP and porous dielectrics |
US8095765B2 (en) * | 2009-03-04 | 2012-01-10 | Micron Technology, Inc. | Memory block management |
US7928570B2 (en) * | 2009-04-16 | 2011-04-19 | International Business Machines Corporation | Interconnect structure |
US20110081503A1 (en) * | 2009-10-06 | 2011-04-07 | Tokyo Electron Limited | Method of depositing stable and adhesive interface between fluorine-based low-k material and metal barrier layer |
US8664113B2 (en) * | 2011-04-28 | 2014-03-04 | GlobalFoundries, Inc. | Multilayer interconnect structure and method for integrated circuits |
US8716863B2 (en) * | 2011-07-13 | 2014-05-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for high performance interconnect |
JP6360276B2 (ja) * | 2012-03-08 | 2018-07-18 | 東京エレクトロン株式会社 | 半導体装置、半導体装置の製造方法、半導体製造装置 |
US8736056B2 (en) | 2012-07-31 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device for reducing contact resistance of a metal |
CN102915958A (zh) * | 2012-09-20 | 2013-02-06 | 上海集成电路研发中心有限公司 | 一种铜互连结构及其制造方法 |
US9293412B2 (en) | 2012-12-17 | 2016-03-22 | International Business Machines Corporation | Graphene and metal interconnects with reduced contact resistance |
US9202743B2 (en) | 2012-12-17 | 2015-12-01 | International Business Machines Corporation | Graphene and metal interconnects |
US10032712B2 (en) * | 2013-03-15 | 2018-07-24 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor structure |
DE102013104464B4 (de) * | 2013-03-15 | 2019-08-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Halbleiterstruktur |
US9431346B2 (en) * | 2013-04-30 | 2016-08-30 | GlobalFoundries, Inc. | Graphene-metal E-fuse |
US9257391B2 (en) | 2013-04-30 | 2016-02-09 | GlobalFoundries, Inc. | Hybrid graphene-metal interconnect structures |
US9171801B2 (en) | 2013-05-09 | 2015-10-27 | Globalfoundries U.S. 2 Llc | E-fuse with hybrid metallization |
US9536830B2 (en) | 2013-05-09 | 2017-01-03 | Globalfoundries Inc. | High performance refractory metal / copper interconnects to eliminate electromigration |
US9305879B2 (en) | 2013-05-09 | 2016-04-05 | Globalfoundries Inc. | E-fuse with hybrid metallization |
US20150013901A1 (en) * | 2013-07-11 | 2015-01-15 | Hsio Technologies, Llc | Matrix defined electrical circuit structure |
US9514986B2 (en) * | 2013-08-28 | 2016-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device with capped through-substrate via structure |
US9576892B2 (en) | 2013-09-09 | 2017-02-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of forming same |
US9040417B2 (en) * | 2013-10-04 | 2015-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
US9437540B2 (en) * | 2014-09-12 | 2016-09-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Additional etching to increase via contact area |
US9842765B2 (en) | 2015-03-16 | 2017-12-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method for forming the same |
US9659864B2 (en) * | 2015-10-20 | 2017-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for forming self-aligned via with selectively deposited etching stop layer |
US9679850B2 (en) * | 2015-10-30 | 2017-06-13 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of fabricating semiconductor structure |
US9780026B2 (en) * | 2016-01-29 | 2017-10-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnection structure and method of forming the same |
DE102018104644A1 (de) * | 2017-08-30 | 2019-02-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Halbleiterbauteil und sein herstellungsverfahren |
US11031287B2 (en) * | 2018-06-27 | 2021-06-08 | Tokyo Electron Limited | Fully self-aligned via with selective bilayer dielectric regrowth |
US11276637B2 (en) | 2019-09-17 | 2022-03-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Barrier-free interconnect structure and manufacturing method thereof |
CN110581117B (zh) * | 2019-09-18 | 2021-04-27 | 武汉新芯集成电路制造有限公司 | 一种半导体器件及其制造方法 |
CN110931373B (zh) * | 2019-12-11 | 2021-11-19 | 武汉新芯集成电路制造有限公司 | 一种半导体器件及其制造方法 |
US11515203B2 (en) * | 2020-02-05 | 2022-11-29 | Tokyo Electron Limited | Selective deposition of conductive cap for fully-aligned-via (FAV) |
US11923295B2 (en) * | 2020-02-19 | 2024-03-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect level with high resistance layer and method of forming the same |
US11251368B2 (en) | 2020-04-20 | 2022-02-15 | International Business Machines Corporation | Interconnect structures with selective capping layer |
CN113707641B (zh) * | 2021-08-25 | 2023-10-24 | 长鑫存储技术有限公司 | 半导体器件及其制作方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6197688B1 (en) * | 1998-02-12 | 2001-03-06 | Motorola Inc. | Interconnect structure in a semiconductor device and method of formation |
US6127258A (en) * | 1998-06-25 | 2000-10-03 | Motorola Inc. | Method for forming a semiconductor device |
US6130162A (en) * | 1999-01-04 | 2000-10-10 | Taiwan Semiconductor Manufacturing Company | Method of preparing passivated copper line and device manufactured thereby |
US6046108A (en) * | 1999-06-25 | 2000-04-04 | Taiwan Semiconductor Manufacturing Company | Method for selective growth of Cu3 Ge or Cu5 Si for passivation of damascene copper structures and device manufactured thereby |
US6130157A (en) * | 1999-07-16 | 2000-10-10 | Taiwan Semiconductor Manufacturing Company | Method to form an encapsulation layer over copper interconnects |
US7727892B2 (en) * | 2002-09-25 | 2010-06-01 | Intel Corporation | Method and apparatus for forming metal-metal oxide etch stop/barrier for integrated circuit interconnects |
JP2004207281A (ja) * | 2002-12-20 | 2004-07-22 | Fujitsu Ltd | 多層配線構造およびその形成方法、半導体装置 |
JP2004342632A (ja) * | 2003-05-13 | 2004-12-02 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
TWI227046B (en) * | 2003-11-11 | 2005-01-21 | United Microelectronics Corp | Process of metal interconnects |
-
2004
- 2004-12-03 US US11/004,767 patent/US7259463B2/en active Active
-
2005
- 2005-03-30 TW TW094109991A patent/TWI246741B/zh active
- 2005-04-04 SG SG200502032A patent/SG122865A1/en unknown
- 2005-05-13 CN CNB2005100695497A patent/CN100424867C/zh active Active
Also Published As
Publication number | Publication date |
---|---|
CN1783476A (zh) | 2006-06-07 |
US7259463B2 (en) | 2007-08-21 |
CN100424867C (zh) | 2008-10-08 |
US20060118962A1 (en) | 2006-06-08 |
TWI246741B (en) | 2006-01-01 |
TW200620544A (en) | 2006-06-16 |
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