SG11202109934RA - Process for fabricating a semiconductor-on-insulator substrate - Google Patents

Process for fabricating a semiconductor-on-insulator substrate

Info

Publication number
SG11202109934RA
SG11202109934RA SG11202109934RA SG11202109934RA SG 11202109934R A SG11202109934R A SG 11202109934RA SG 11202109934R A SG11202109934R A SG 11202109934RA SG 11202109934R A SG11202109934R A SG 11202109934RA
Authority
SG
Singapore
Prior art keywords
fabricating
semiconductor
insulator substrate
insulator
substrate
Prior art date
Application number
Other languages
English (en)
Inventor
Marcel Broekaart
Arnaud Castex
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11202109934RA publication Critical patent/SG11202109934RA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185Joining of semiconductor bodies for junction formation
    • H01L21/187Joining of semiconductor bodies for junction formation by direct bonding

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
SG11202109934R 2019-03-29 2020-03-26 Process for fabricating a semiconductor-on-insulator substrate SG11202109934RA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1903387A FR3094563A1 (fr) 2019-03-29 2019-03-29 Procede de fabrication d’un substrat de type semi-conducteur sur isolant
PCT/EP2020/058529 WO2020201003A1 (fr) 2019-03-29 2020-03-26 Procede de fabrication d'un substrat de type semi-conducteur sur isolant

Publications (1)

Publication Number Publication Date
SG11202109934RA true SG11202109934RA (en) 2021-10-28

Family

ID=67742638

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202109934R SG11202109934RA (en) 2019-03-29 2020-03-26 Process for fabricating a semiconductor-on-insulator substrate

Country Status (9)

Country Link
US (1) US20220139768A1 (fr)
EP (1) EP3948941B1 (fr)
JP (1) JP7535058B2 (fr)
KR (1) KR20210139456A (fr)
CN (1) CN113597668B (fr)
FR (1) FR3094563A1 (fr)
SG (1) SG11202109934RA (fr)
TW (1) TWI828893B (fr)
WO (1) WO2020201003A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3135820B1 (fr) * 2022-05-18 2024-04-26 Commissariat Energie Atomique Procédé de transfert d'une couche depuis un substrat source vers un substrat destination

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2839147B1 (fr) 2002-04-30 2004-07-09 Soitec Silicon On Insulator Dispositif et procede de controle automatique de l'etat de surface de plaque par mesure de vitesse de collage
WO2007047536A2 (fr) 2005-10-14 2007-04-26 Silicon Genesis Corporation Procede et appareil pour outil de liaison de plaquettes dite « flag-less »
FR2894067B1 (fr) * 2005-11-28 2008-02-15 Soitec Silicon On Insulator Procede de collage par adhesion moleculaire
US7601271B2 (en) 2005-11-28 2009-10-13 S.O.I.Tec Silicon On Insulator Technologies Process and equipment for bonding by molecular adhesion
FR2912839B1 (fr) 2007-02-16 2009-05-15 Soitec Silicon On Insulator Amelioration de la qualite de l'interface de collage par nettoyage froid et collage a chaud
JP2011029609A (ja) * 2009-06-26 2011-02-10 Semiconductor Energy Lab Co Ltd Soi基板の作製方法およびsoi基板
FR2963157B1 (fr) * 2010-07-22 2013-04-26 Soitec Silicon On Insulator Procede et appareil de collage par adhesion moleculaire de deux plaques
FR2990054B1 (fr) * 2012-04-27 2014-05-02 Commissariat Energie Atomique Procede de collage dans une atmosphere de gaz presentant un coefficient de joule-thomson negatif.
EP3404699A1 (fr) * 2013-05-29 2018-11-21 EV Group E. Thallner GmbH Dispositif et procédé de liaison des substrats
US9837291B2 (en) * 2014-01-24 2017-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer processing method and apparatus
FR3020175B1 (fr) * 2014-04-16 2016-05-13 Soitec Silicon On Insulator Procede de transfert d'une couche utile
TW201826333A (zh) * 2016-11-16 2018-07-16 日商尼康股份有限公司 保持構件、接合裝置、及接合方法

Also Published As

Publication number Publication date
CN113597668B (zh) 2024-09-13
JP2022526167A (ja) 2022-05-23
CN113597668A (zh) 2021-11-02
TWI828893B (zh) 2024-01-11
JP7535058B2 (ja) 2024-08-15
FR3094563A1 (fr) 2020-10-02
US20220139768A1 (en) 2022-05-05
EP3948941B1 (fr) 2023-03-22
WO2020201003A1 (fr) 2020-10-08
KR20210139456A (ko) 2021-11-22
EP3948941A1 (fr) 2022-02-09
TW202103263A (zh) 2021-01-16

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