SG11201910319YA - Layout technique for middle-end-of-line - Google Patents
Layout technique for middle-end-of-lineInfo
- Publication number
- SG11201910319YA SG11201910319YA SG11201910319YA SG11201910319YA SG11201910319YA SG 11201910319Y A SG11201910319Y A SG 11201910319YA SG 11201910319Y A SG11201910319Y A SG 11201910319YA SG 11201910319Y A SG11201910319Y A SG 11201910319YA SG 11201910319Y A SG11201910319Y A SG 11201910319YA
- Authority
- SG
- Singapore
- Prior art keywords
- line
- layout technique
- layout
- technique
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Details Of Aerials (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/628,909 US10325845B2 (en) | 2017-06-21 | 2017-06-21 | Layout technique for middle-end-of-line |
PCT/US2018/035033 WO2018236560A1 (en) | 2017-06-21 | 2018-05-30 | ARRANGEMENT TECHNIQUE FOR CENTRAL END OF LINE |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11201910319YA true SG11201910319YA (en) | 2020-01-30 |
Family
ID=62784220
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201910319YA SG11201910319YA (en) | 2017-06-21 | 2018-05-30 | Layout technique for middle-end-of-line |
Country Status (6)
Country | Link |
---|---|
US (3) | US10325845B2 (de) |
EP (1) | EP3642881B1 (de) |
CN (1) | CN110832642A (de) |
SG (1) | SG11201910319YA (de) |
TW (2) | TWI776630B (de) |
WO (1) | WO2018236560A1 (de) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10325845B2 (en) | 2017-06-21 | 2019-06-18 | Qualcomm Incorporated | Layout technique for middle-end-of-line |
US10756114B2 (en) * | 2017-12-28 | 2020-08-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor circuit with metal structure and manufacturing method |
US10867917B1 (en) * | 2019-06-14 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device, associated method and layout |
KR20210028398A (ko) | 2019-09-04 | 2021-03-12 | 삼성전자주식회사 | 재배선 패턴을 가지는 집적회로 소자 |
US11264486B2 (en) * | 2020-01-16 | 2022-03-01 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and method of fabricating the semiconductor structure |
US11569166B2 (en) * | 2020-08-31 | 2023-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and manufacturing method thereof |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8816444B2 (en) | 2011-04-29 | 2014-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and methods for converting planar design to FinFET design |
WO2015047315A1 (en) * | 2013-09-27 | 2015-04-02 | Intel Corporation | Low leakage non-planar access transistor for embedded dynamic random access memeory (edram) |
JP6333672B2 (ja) * | 2014-08-28 | 2018-05-30 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9793384B2 (en) * | 2014-10-01 | 2017-10-17 | Globalfoundries Inc. | Tunneling field effect transistor and methods of making such a transistor |
US9620510B2 (en) * | 2014-12-19 | 2017-04-11 | Taiwan Semiconductor Manufacturing Company Ltd. | Stacked metal layers with different thicknesses |
US9583438B2 (en) * | 2014-12-26 | 2017-02-28 | Taiwan Semiconductor Manufacturing Company Ltd. | Interconnect structure with misaligned metal lines coupled using different interconnect layer |
US10338474B2 (en) * | 2015-01-14 | 2019-07-02 | Intel Corporation | Underlying absorbing or conducting layer for Ebeam direct write (EBDW) lithography |
WO2016117288A1 (ja) * | 2015-01-19 | 2016-07-28 | 株式会社ソシオネクスト | 半導体集積回路装置 |
KR102310080B1 (ko) | 2015-03-02 | 2021-10-12 | 삼성전자주식회사 | 반도체 장치 및 반도체 장치의 제조 방법 |
JP6396834B2 (ja) | 2015-03-23 | 2018-09-26 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9653346B2 (en) * | 2015-05-07 | 2017-05-16 | United Microelectronics Corp. | Integrated FinFET structure having a contact plug pitch larger than fin and first metal pitch |
US9673145B2 (en) * | 2015-05-07 | 2017-06-06 | United Microelectronics Corp. | Semiconductor integrated circuit layout structure |
KR20160136715A (ko) * | 2015-05-20 | 2016-11-30 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US9647071B2 (en) * | 2015-06-15 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | FINFET structures and methods of forming the same |
WO2017044107A1 (en) * | 2015-09-10 | 2017-03-16 | Intel Corporation | Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device |
DE112015006962T5 (de) * | 2015-09-24 | 2018-06-07 | Intel Corporation | Hybride tri-gate- und nanodraht-cmos-vorrichtungsarchitektur |
WO2017052654A1 (en) * | 2015-09-25 | 2017-03-30 | Intel Corporation | Scaled interconnect via and transistor contact by adjusting scattering |
WO2017052638A1 (en) * | 2015-09-25 | 2017-03-30 | Intel Corporation | Backside contact structures and fabrication for metal on both sides of devices |
US9793211B2 (en) | 2015-10-20 | 2017-10-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual power structure with connection pins |
CN106952900B (zh) * | 2016-01-07 | 2021-07-27 | 联华电子股份有限公司 | 半导体布局结构 |
US10050042B2 (en) * | 2016-01-29 | 2018-08-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | SRAM cell and logic cell design |
US9837353B2 (en) * | 2016-03-01 | 2017-12-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Middle end-of-line strap for standard cell |
CN106611782B (zh) | 2016-12-27 | 2020-10-02 | 上海集成电路研发中心有限公司 | 一种降低FinFET寄生电阻的方法 |
US10325845B2 (en) | 2017-06-21 | 2019-06-18 | Qualcomm Incorporated | Layout technique for middle-end-of-line |
-
2017
- 2017-06-21 US US15/628,909 patent/US10325845B2/en active Active
-
2018
- 2018-05-30 TW TW110129193A patent/TWI776630B/zh active
- 2018-05-30 TW TW107118581A patent/TWI739006B/zh active
- 2018-05-30 EP EP18735439.4A patent/EP3642881B1/de active Active
- 2018-05-30 SG SG11201910319YA patent/SG11201910319YA/en unknown
- 2018-05-30 WO PCT/US2018/035033 patent/WO2018236560A1/en unknown
- 2018-05-30 CN CN201880041233.2A patent/CN110832642A/zh active Pending
- 2018-10-12 US US16/159,042 patent/US10410965B2/en active Active
-
2019
- 2019-08-30 US US16/557,728 patent/US20190385948A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
BR112019026589A2 (pt) | 2020-06-23 |
EP3642881B1 (de) | 2023-04-12 |
US20190067189A1 (en) | 2019-02-28 |
US10325845B2 (en) | 2019-06-18 |
TWI776630B (zh) | 2022-09-01 |
US10410965B2 (en) | 2019-09-10 |
US20180374792A1 (en) | 2018-12-27 |
TWI739006B (zh) | 2021-09-11 |
TW201911534A (zh) | 2019-03-16 |
WO2018236560A1 (en) | 2018-12-27 |
EP3642881A1 (de) | 2020-04-29 |
CN110832642A (zh) | 2020-02-21 |
US20190385948A1 (en) | 2019-12-19 |
TW202145501A (zh) | 2021-12-01 |
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