SG11201910319YA - Layout technique for middle-end-of-line - Google Patents

Layout technique for middle-end-of-line

Info

Publication number
SG11201910319YA
SG11201910319YA SG11201910319YA SG11201910319YA SG11201910319YA SG 11201910319Y A SG11201910319Y A SG 11201910319YA SG 11201910319Y A SG11201910319Y A SG 11201910319YA SG 11201910319Y A SG11201910319Y A SG 11201910319YA SG 11201910319Y A SG11201910319Y A SG 11201910319YA
Authority
SG
Singapore
Prior art keywords
line
layout technique
layout
technique
Prior art date
Application number
SG11201910319YA
Inventor
Tin Tin Wee
Trilochan Sahoo
Sunil Sukumarapillai
Arun Kumar Kodigenahalli Venkateswar
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of SG11201910319YA publication Critical patent/SG11201910319YA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41791Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Details Of Aerials (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
SG11201910319YA 2017-06-21 2018-05-30 Layout technique for middle-end-of-line SG11201910319YA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/628,909 US10325845B2 (en) 2017-06-21 2017-06-21 Layout technique for middle-end-of-line
PCT/US2018/035033 WO2018236560A1 (en) 2017-06-21 2018-05-30 Layout technique for middle-end-of-line

Publications (1)

Publication Number Publication Date
SG11201910319YA true SG11201910319YA (en) 2020-01-30

Family

ID=62784220

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201910319YA SG11201910319YA (en) 2017-06-21 2018-05-30 Layout technique for middle-end-of-line

Country Status (6)

Country Link
US (3) US10325845B2 (en)
EP (1) EP3642881B1 (en)
CN (1) CN110832642B (en)
SG (1) SG11201910319YA (en)
TW (2) TWI739006B (en)
WO (1) WO2018236560A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10325845B2 (en) 2017-06-21 2019-06-18 Qualcomm Incorporated Layout technique for middle-end-of-line
US10756114B2 (en) * 2017-12-28 2020-08-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor circuit with metal structure and manufacturing method
US10867917B1 (en) * 2019-06-14 2020-12-15 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device, associated method and layout
KR20210028398A (en) 2019-09-04 2021-03-12 삼성전자주식회사 Integrated circuit devices having redistribution patterns
US11264486B2 (en) * 2020-01-16 2022-03-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method of fabricating the semiconductor structure
US11569166B2 (en) * 2020-08-31 2023-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8816444B2 (en) 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
WO2015047315A1 (en) * 2013-09-27 2015-04-02 Intel Corporation Low leakage non-planar access transistor for embedded dynamic random access memeory (edram)
JP6333672B2 (en) * 2014-08-28 2018-05-30 ルネサスエレクトロニクス株式会社 Semiconductor device
US9793384B2 (en) * 2014-10-01 2017-10-17 Globalfoundries Inc. Tunneling field effect transistor and methods of making such a transistor
US9620510B2 (en) * 2014-12-19 2017-04-11 Taiwan Semiconductor Manufacturing Company Ltd. Stacked metal layers with different thicknesses
US9583438B2 (en) * 2014-12-26 2017-02-28 Taiwan Semiconductor Manufacturing Company Ltd. Interconnect structure with misaligned metal lines coupled using different interconnect layer
KR102385705B1 (en) * 2015-01-14 2022-04-12 인텔 코포레이션 Underlying absorbing or conducting layer for ebeam direct write(ebdw) lithography
WO2016117288A1 (en) * 2015-01-19 2016-07-28 株式会社ソシオネクスト Semiconductor integrated circuit device
KR102310080B1 (en) 2015-03-02 2021-10-12 삼성전자주식회사 Semiconductor devices and methods of manufacturing semiconductor devices
JP6396834B2 (en) 2015-03-23 2018-09-26 ルネサスエレクトロニクス株式会社 Semiconductor device
US9653346B2 (en) * 2015-05-07 2017-05-16 United Microelectronics Corp. Integrated FinFET structure having a contact plug pitch larger than fin and first metal pitch
US9673145B2 (en) * 2015-05-07 2017-06-06 United Microelectronics Corp. Semiconductor integrated circuit layout structure
KR20160136715A (en) * 2015-05-20 2016-11-30 삼성전자주식회사 Semiconductor devices and methods of manufacturing the same
US9647071B2 (en) * 2015-06-15 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. FINFET structures and methods of forming the same
US10453967B2 (en) * 2015-09-10 2019-10-22 Intel Corporation Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device
CN107924875B (en) * 2015-09-24 2022-11-01 英特尔公司 Hybrid tri-gate and nanowire CMOS device architectures
WO2017052654A1 (en) * 2015-09-25 2017-03-30 Intel Corporation Scaled interconnect via and transistor contact by adjusting scattering
US10784358B2 (en) * 2015-09-25 2020-09-22 Intel Corporation Backside contact structures and fabrication for metal on both sides of devices
US9793211B2 (en) 2015-10-20 2017-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Dual power structure with connection pins
CN106952900B (en) * 2016-01-07 2021-07-27 联华电子股份有限公司 Semiconductor layout structure
US10050042B2 (en) * 2016-01-29 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM cell and logic cell design
US9837353B2 (en) * 2016-03-01 2017-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Middle end-of-line strap for standard cell
CN106611782B (en) 2016-12-27 2020-10-02 上海集成电路研发中心有限公司 Method for reducing parasitic resistance of FinFET (Fin field Effect transistor)
US10325845B2 (en) 2017-06-21 2019-06-18 Qualcomm Incorporated Layout technique for middle-end-of-line

Also Published As

Publication number Publication date
EP3642881A1 (en) 2020-04-29
US20190385948A1 (en) 2019-12-19
CN110832642B (en) 2024-07-09
BR112019026589A2 (en) 2020-06-23
TWI776630B (en) 2022-09-01
TW201911534A (en) 2019-03-16
US10325845B2 (en) 2019-06-18
CN110832642A (en) 2020-02-21
US20180374792A1 (en) 2018-12-27
TWI739006B (en) 2021-09-11
WO2018236560A1 (en) 2018-12-27
EP3642881B1 (en) 2023-04-12
US20190067189A1 (en) 2019-02-28
US10410965B2 (en) 2019-09-10
TW202145501A (en) 2021-12-01

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