SG11201906694SA - Communication apparatus, communication method, program, and communication system - Google Patents
Communication apparatus, communication method, program, and communication systemInfo
- Publication number
- SG11201906694SA SG11201906694SA SG11201906694SA SG11201906694SA SG11201906694SA SG 11201906694S A SG11201906694S A SG 11201906694SA SG 11201906694S A SG11201906694S A SG 11201906694SA SG 11201906694S A SG11201906694S A SG 11201906694SA SG 11201906694S A SG11201906694S A SG 11201906694SA
- Authority
- SG
- Singapore
- Prior art keywords
- data
- communication
- length
- program
- max
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4009—Coupling between buses with data restructuring
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40032—Details regarding a bus interface enhancer
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/403—Bus networks with centralised control, e.g. polling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/14—Two-way operation using the same type of signal, i.e. duplex
- H04L5/1438—Negotiation of transmission parameters prior to communication
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
- H04L1/0063—Single parity check
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40143—Bus networks involving priority mechanisms
- H04L12/40156—Bus networks involving priority mechanisms by using dedicated slots associated with a priority level
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Quality & Reliability (AREA)
- Computer Hardware Design (AREA)
- Information Transfer Systems (AREA)
- Communication Control (AREA)
- Stereo-Broadcasting Methods (AREA)
- Bus Control (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017058247 | 2017-03-23 | ||
PCT/JP2018/009153 WO2018173796A1 (fr) | 2017-03-23 | 2018-03-09 | Dispositif de communication, procédé de communication, programme, et système de communication |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11201906694SA true SG11201906694SA (en) | 2019-08-27 |
Family
ID=63585444
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201906694SA SG11201906694SA (en) | 2017-03-23 | 2018-03-09 | Communication apparatus, communication method, program, and communication system |
Country Status (8)
Country | Link |
---|---|
US (2) | US11010328B2 (fr) |
EP (1) | EP3605348B1 (fr) |
JP (1) | JP7123905B2 (fr) |
KR (1) | KR102515186B1 (fr) |
CN (1) | CN110447020B (fr) |
SG (1) | SG11201906694SA (fr) |
TW (1) | TWI767997B (fr) |
WO (1) | WO2018173796A1 (fr) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI767997B (zh) * | 2017-03-23 | 2022-06-21 | 日商索尼半導體解決方案公司 | 通信裝置、通信方法、程式及通信系統 |
US11030142B2 (en) * | 2017-06-28 | 2021-06-08 | Intel Corporation | Method, apparatus and system for dynamic control of clock signaling on a bus |
JP2023089317A (ja) * | 2020-05-11 | 2023-06-28 | ソニーセミコンダクタソリューションズ株式会社 | 通信装置及び通信システム |
CN113031486B (zh) * | 2021-03-18 | 2022-12-02 | 深圳市度信科技有限公司 | 基于fpga的i3c逻辑控制器实现方法、i3c读写测试装置和系统 |
CN117435518B (zh) * | 2023-12-21 | 2024-03-22 | 沐曦集成电路(上海)有限公司 | 一种用于主从读写数据的保护方法 |
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JPS582496B2 (ja) * | 1978-04-28 | 1983-01-17 | 日本電信電話株式会社 | デ−タ転送方式 |
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JPH0522345A (ja) * | 1991-07-12 | 1993-01-29 | Hitachi Ltd | 最大転送単位の最適値管理決定方式 |
JPH07160628A (ja) * | 1993-12-09 | 1995-06-23 | Fujitsu Ltd | データ並列転送システム |
US7590133B2 (en) * | 1998-02-24 | 2009-09-15 | Canon Kabushiki Kaisha | Data communication system, data communication method, and data communication apparatus |
JP4046846B2 (ja) * | 1998-04-28 | 2008-02-13 | キヤノン株式会社 | データ通信システム及びデータ通信装置 |
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JP2002290459A (ja) * | 2001-03-27 | 2002-10-04 | Nec Corp | パケット転送装置および方法 |
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US7653773B2 (en) * | 2007-10-03 | 2010-01-26 | International Business Machines Corporation | Dynamically balancing bus bandwidth |
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TWI767997B (zh) * | 2017-03-23 | 2022-06-21 | 日商索尼半導體解決方案公司 | 通信裝置、通信方法、程式及通信系統 |
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-
2018
- 2018-03-01 TW TW107106711A patent/TWI767997B/zh active
- 2018-03-09 EP EP18772411.7A patent/EP3605348B1/fr active Active
- 2018-03-09 US US16/491,035 patent/US11010328B2/en active Active
- 2018-03-09 WO PCT/JP2018/009153 patent/WO2018173796A1/fr unknown
- 2018-03-09 SG SG11201906694SA patent/SG11201906694SA/en unknown
- 2018-03-09 JP JP2019507539A patent/JP7123905B2/ja active Active
- 2018-03-09 KR KR1020197022284A patent/KR102515186B1/ko active IP Right Grant
- 2018-03-09 CN CN201880018660.9A patent/CN110447020B/zh active Active
-
2021
- 2021-05-06 US US17/313,539 patent/US11714778B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20220058156A1 (en) | 2022-02-24 |
EP3605348A4 (fr) | 2020-03-11 |
CN110447020A (zh) | 2019-11-12 |
US11714778B2 (en) | 2023-08-01 |
JPWO2018173796A1 (ja) | 2020-01-23 |
WO2018173796A1 (fr) | 2018-09-27 |
EP3605348A1 (fr) | 2020-02-05 |
TW201837728A (zh) | 2018-10-16 |
KR20190131016A (ko) | 2019-11-25 |
US11010328B2 (en) | 2021-05-18 |
US20200012615A1 (en) | 2020-01-09 |
KR102515186B1 (ko) | 2023-03-29 |
TWI767997B (zh) | 2022-06-21 |
CN110447020B (zh) | 2024-03-26 |
EP3605348B1 (fr) | 2023-06-28 |
JP7123905B2 (ja) | 2022-08-23 |
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