SG11201805988VA - Providing scalable dynamic random access memory (dram) cache management using dram cache indicator caches - Google Patents

Providing scalable dynamic random access memory (dram) cache management using dram cache indicator caches

Info

Publication number
SG11201805988VA
SG11201805988VA SG11201805988VA SG11201805988VA SG11201805988VA SG 11201805988V A SG11201805988V A SG 11201805988VA SG 11201805988V A SG11201805988V A SG 11201805988VA SG 11201805988V A SG11201805988V A SG 11201805988VA SG 11201805988V A SG11201805988V A SG 11201805988VA
Authority
SG
Singapore
Prior art keywords
dram
cache
memory
dram cache
international
Prior art date
Application number
SG11201805988VA
Other languages
English (en)
Inventor
Natarajan Vaidhyanathan
Mattheus Heddes
Colin Verrilli
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of SG11201805988VA publication Critical patent/SG11201805988VA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1008—Correctness of operation, e.g. memory ordering
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/28—Using a specific disk cache architecture
    • G06F2212/281—Single cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/70—Details relating to dynamic memory management
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2245—Memory devices with an internal cache buffer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
SG11201805988VA 2016-02-22 2017-02-01 Providing scalable dynamic random access memory (dram) cache management using dram cache indicator caches SG11201805988VA (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662298088P 2016-02-22 2016-02-22
US15/228,320 US10176096B2 (en) 2016-02-22 2016-08-04 Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator caches
PCT/US2017/016005 WO2017146882A1 (en) 2016-02-22 2017-02-01 Providing scalable dynamic random access memory (dram) cache management using dram cache indicator caches

Publications (1)

Publication Number Publication Date
SG11201805988VA true SG11201805988VA (en) 2018-09-27

Family

ID=59629409

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201805988VA SG11201805988VA (en) 2016-02-22 2017-02-01 Providing scalable dynamic random access memory (dram) cache management using dram cache indicator caches

Country Status (10)

Country Link
US (1) US10176096B2 (enExample)
EP (1) EP3420460B1 (enExample)
JP (1) JP2019509557A (enExample)
KR (1) KR20180113536A (enExample)
CN (1) CN108701093A (enExample)
ES (1) ES2870516T3 (enExample)
HK (1) HK1256013A1 (enExample)
SG (1) SG11201805988VA (enExample)
TW (1) TW201732599A (enExample)
WO (1) WO2017146882A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10783083B2 (en) * 2018-02-12 2020-09-22 Stmicroelectronics (Beijing) Research & Development Co. Ltd Cache management device, system and method
CN109669882B (zh) * 2018-12-28 2021-03-09 贵州华芯通半导体技术有限公司 带宽感知的动态高速缓存替换方法、装置、系统和介质
KR20240040507A (ko) 2022-09-21 2024-03-28 삼성전자주식회사 스토리지 시스템 및 스토리지 시스템의 동작 방법
US20260211814A1 (en) * 2025-01-23 2026-07-23 Dell Products L.P. Operation based multi-level caching

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US7613870B2 (en) * 2004-11-18 2009-11-03 International Business Machines Corporation Efficient memory usage in systems including volatile and high-density memories
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US8593474B2 (en) * 2005-12-30 2013-11-26 Intel Corporation Method and system for symmetric allocation for a shared L2 mapping cache
GB2458295B (en) * 2008-03-12 2012-01-11 Advanced Risc Mach Ltd Cache accessing using a micro tag
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EP2405361A4 (en) * 2009-03-06 2012-12-19 Fujitsu Ltd COMPUTER SYSTEM, CONTROL PROCEDURE, RECORDING MEDIA AND CONTROL PROGRAM
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US8819342B2 (en) * 2012-09-26 2014-08-26 Qualcomm Incorporated Methods and apparatus for managing page crossing instructions with different cacheability
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Also Published As

Publication number Publication date
ES2870516T3 (es) 2021-10-27
WO2017146882A1 (en) 2017-08-31
EP3420460B1 (en) 2021-04-07
CN108701093A (zh) 2018-10-23
JP2019509557A (ja) 2019-04-04
US10176096B2 (en) 2019-01-08
HK1256013A1 (zh) 2019-09-13
TW201732599A (zh) 2017-09-16
EP3420460A1 (en) 2019-01-02
KR20180113536A (ko) 2018-10-16
US20170242793A1 (en) 2017-08-24
BR112018017135A2 (pt) 2019-01-02

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