HK1256013A1 - 使用动态随机存取存储器(dram)高速缓存指示符高速缓存存储器以提供可扩展dram高速缓存管理 - Google Patents

使用动态随机存取存储器(dram)高速缓存指示符高速缓存存储器以提供可扩展dram高速缓存管理 Download PDF

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Publication number
HK1256013A1
HK1256013A1 HK18115063.0A HK18115063A HK1256013A1 HK 1256013 A1 HK1256013 A1 HK 1256013A1 HK 18115063 A HK18115063 A HK 18115063A HK 1256013 A1 HK1256013 A1 HK 1256013A1
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HK
Hong Kong
Prior art keywords
memory
dram
cache
dram cache
address
Prior art date
Application number
HK18115063.0A
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English (en)
Chinese (zh)
Inventor
N‧瓦伊德亚纳坦
N‧瓦伊德亞納坦
M‧C‧A‧A‧黑德斯
C‧B‧韦里利
C‧B‧韋里利
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高通股份有限公司
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Application filed by 高通股份有限公司 filed Critical 高通股份有限公司
Publication of HK1256013A1 publication Critical patent/HK1256013A1/zh

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1008—Correctness of operation, e.g. memory ordering
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/28—Using a specific disk cache architecture
    • G06F2212/281—Single cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/70—Details relating to dynamic memory management
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2245—Memory devices with an internal cache buffer

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
HK18115063.0A 2016-02-22 2017-02-01 使用动态随机存取存储器(dram)高速缓存指示符高速缓存存储器以提供可扩展dram高速缓存管理 HK1256013A1 (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662298088P 2016-02-22 2016-02-22
US62/298,088 2016-02-22
US15/228,320 2016-08-04
US15/228,320 US10176096B2 (en) 2016-02-22 2016-08-04 Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator caches
PCT/US2017/016005 WO2017146882A1 (en) 2016-02-22 2017-02-01 Providing scalable dynamic random access memory (dram) cache management using dram cache indicator caches

Publications (1)

Publication Number Publication Date
HK1256013A1 true HK1256013A1 (zh) 2019-09-13

Family

ID=59629409

Family Applications (1)

Application Number Title Priority Date Filing Date
HK18115063.0A HK1256013A1 (zh) 2016-02-22 2017-02-01 使用动态随机存取存储器(dram)高速缓存指示符高速缓存存储器以提供可扩展dram高速缓存管理

Country Status (10)

Country Link
US (1) US10176096B2 (enExample)
EP (1) EP3420460B1 (enExample)
JP (1) JP2019509557A (enExample)
KR (1) KR20180113536A (enExample)
CN (1) CN108701093A (enExample)
ES (1) ES2870516T3 (enExample)
HK (1) HK1256013A1 (enExample)
SG (1) SG11201805988VA (enExample)
TW (1) TW201732599A (enExample)
WO (1) WO2017146882A1 (enExample)

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KR20240040507A (ko) 2022-09-21 2024-03-28 삼성전자주식회사 스토리지 시스템 및 스토리지 시스템의 동작 방법
US20260211814A1 (en) * 2025-01-23 2026-07-23 Dell Products L.P. Operation based multi-level caching

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Also Published As

Publication number Publication date
ES2870516T3 (es) 2021-10-27
WO2017146882A1 (en) 2017-08-31
EP3420460B1 (en) 2021-04-07
CN108701093A (zh) 2018-10-23
JP2019509557A (ja) 2019-04-04
US10176096B2 (en) 2019-01-08
TW201732599A (zh) 2017-09-16
EP3420460A1 (en) 2019-01-02
KR20180113536A (ko) 2018-10-16
US20170242793A1 (en) 2017-08-24
SG11201805988VA (en) 2018-09-27
BR112018017135A2 (pt) 2019-01-02

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