KR20180113536A - Dram(dynamic random access memory) 캐시 표시자 캐시들을 사용하는 스케일러블 dram 캐시 관리의 제공 - Google Patents

Dram(dynamic random access memory) 캐시 표시자 캐시들을 사용하는 스케일러블 dram 캐시 관리의 제공 Download PDF

Info

Publication number
KR20180113536A
KR20180113536A KR1020187023757A KR20187023757A KR20180113536A KR 20180113536 A KR20180113536 A KR 20180113536A KR 1020187023757 A KR1020187023757 A KR 1020187023757A KR 20187023757 A KR20187023757 A KR 20187023757A KR 20180113536 A KR20180113536 A KR 20180113536A
Authority
KR
South Korea
Prior art keywords
cache
dram
dram cache
address
indicator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020187023757A
Other languages
English (en)
Korean (ko)
Inventor
나타라잔 바이디야나단
마테우스 코르넬리스 안토니우스 아드리아누스 헤데스
콜린 비튼 베릴리
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20180113536A publication Critical patent/KR20180113536A/ko
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1008—Correctness of operation, e.g. memory ordering
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/28—Using a specific disk cache architecture
    • G06F2212/281—Single cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/70—Details relating to dynamic memory management
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2245—Memory devices with an internal cache buffer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020187023757A 2016-02-22 2017-02-01 Dram(dynamic random access memory) 캐시 표시자 캐시들을 사용하는 스케일러블 dram 캐시 관리의 제공 Withdrawn KR20180113536A (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662298088P 2016-02-22 2016-02-22
US62/298,088 2016-02-22
US15/228,320 2016-08-04
US15/228,320 US10176096B2 (en) 2016-02-22 2016-08-04 Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator caches
PCT/US2017/016005 WO2017146882A1 (en) 2016-02-22 2017-02-01 Providing scalable dynamic random access memory (dram) cache management using dram cache indicator caches

Publications (1)

Publication Number Publication Date
KR20180113536A true KR20180113536A (ko) 2018-10-16

Family

ID=59629409

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020187023757A Withdrawn KR20180113536A (ko) 2016-02-22 2017-02-01 Dram(dynamic random access memory) 캐시 표시자 캐시들을 사용하는 스케일러블 dram 캐시 관리의 제공

Country Status (10)

Country Link
US (1) US10176096B2 (enExample)
EP (1) EP3420460B1 (enExample)
JP (1) JP2019509557A (enExample)
KR (1) KR20180113536A (enExample)
CN (1) CN108701093A (enExample)
ES (1) ES2870516T3 (enExample)
HK (1) HK1256013A1 (enExample)
SG (1) SG11201805988VA (enExample)
TW (1) TW201732599A (enExample)
WO (1) WO2017146882A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10783083B2 (en) * 2018-02-12 2020-09-22 Stmicroelectronics (Beijing) Research & Development Co. Ltd Cache management device, system and method
CN109669882B (zh) * 2018-12-28 2021-03-09 贵州华芯通半导体技术有限公司 带宽感知的动态高速缓存替换方法、装置、系统和介质
KR20240040507A (ko) 2022-09-21 2024-03-28 삼성전자주식회사 스토리지 시스템 및 스토리지 시스템의 동작 방법
US20260211814A1 (en) * 2025-01-23 2026-07-23 Dell Products L.P. Operation based multi-level caching

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2256512B (en) 1991-06-04 1995-03-15 Intel Corp Second level cache controller unit and system
US5414827A (en) * 1991-12-19 1995-05-09 Opti, Inc. Automatic cache flush
US6029224A (en) * 1995-06-07 2000-02-22 Lucent Technologies Inc. Self-contained memory apparatus having diverse types of memory and distributed control
US6173368B1 (en) * 1995-12-18 2001-01-09 Texas Instruments Incorporated Class categorized storage circuit for storing non-cacheable data until receipt of a corresponding terminate signal
US5752262A (en) * 1996-07-25 1998-05-12 Vlsi Technology System and method for enabling and disabling writeback cache
US6092155A (en) * 1997-07-10 2000-07-18 International Business Machines Corporation Cache coherent network adapter for scalable shared memory processing systems
US6327645B1 (en) * 1999-11-08 2001-12-04 Silicon Integrated Systems Corp. Cache memory system with memory request address queue, cache write address queue, and cache read address queue
US7146454B1 (en) * 2002-04-16 2006-12-05 Cypress Semiconductor Corporation Hiding refresh in 1T-SRAM architecture
US20030204702A1 (en) * 2002-04-30 2003-10-30 Adc Dsl Systems, Inc. Flexible memory architecture for an embedded processor
JP3953903B2 (ja) * 2002-06-28 2007-08-08 富士通株式会社 キャッシュメモリ装置、及び、参照履歴のビット誤り検出方法
US20040201647A1 (en) 2002-12-02 2004-10-14 Mark Jackson Pulver Stitching of integrated circuit components
US6880047B2 (en) * 2003-03-28 2005-04-12 Emulex Design & Manufacturing Corporation Local emulation of data RAM utilizing write-through cache hardware within a CPU module
US7613870B2 (en) * 2004-11-18 2009-11-03 International Business Machines Corporation Efficient memory usage in systems including volatile and high-density memories
US7958312B2 (en) 2005-11-15 2011-06-07 Oracle America, Inc. Small and power-efficient cache that can provide data for background DMA devices while the processor is in a low-power state
US8593474B2 (en) * 2005-12-30 2013-11-26 Intel Corporation Method and system for symmetric allocation for a shared L2 mapping cache
GB2458295B (en) * 2008-03-12 2012-01-11 Advanced Risc Mach Ltd Cache accessing using a micro tag
US8799582B2 (en) * 2008-12-30 2014-08-05 Intel Corporation Extending cache coherency protocols to support locally buffered data
EP2405361A4 (en) * 2009-03-06 2012-12-19 Fujitsu Ltd COMPUTER SYSTEM, CONTROL PROCEDURE, RECORDING MEDIA AND CONTROL PROGRAM
US9086973B2 (en) 2009-06-09 2015-07-21 Hyperion Core, Inc. System and method for a cache in a multi-core processor
JP2011258073A (ja) * 2010-06-10 2011-12-22 Nec Corp 置換領域選択装置、置換領域選択システム、置換領域選択方法、および置換領域選択プログラム
US20130254491A1 (en) * 2011-12-22 2013-09-26 James A. Coleman Controlling a processor cache using a real-time attribute
US9075746B2 (en) 2011-12-23 2015-07-07 Intel Corporation Utility and lifetime based cache replacement policy
US9286221B1 (en) * 2012-06-06 2016-03-15 Reniac, Inc. Heterogeneous memory system
US20140047175A1 (en) * 2012-08-09 2014-02-13 International Business Machines Corporation Implementing efficient cache tag lookup in very large cache systems
US8819342B2 (en) * 2012-09-26 2014-08-26 Qualcomm Incorporated Methods and apparatus for managing page crossing instructions with different cacheability
US9348753B2 (en) * 2012-10-10 2016-05-24 Advanced Micro Devices, Inc. Controlling prefetch aggressiveness based on thrash events
US20150095582A1 (en) * 2013-09-30 2015-04-02 Avaya, Inc. Method for Specifying Packet Address Range Cacheability
CN106133700A (zh) 2014-03-29 2016-11-16 英派尔科技开发有限公司 节能的动态dram缓存调整
US20150293847A1 (en) * 2014-04-13 2015-10-15 Qualcomm Incorporated Method and apparatus for lowering bandwidth and power in a cache using read with invalidate
US9356602B1 (en) * 2015-05-14 2016-05-31 Xilinx, Inc. Management of memory resources in a programmable integrated circuit

Also Published As

Publication number Publication date
ES2870516T3 (es) 2021-10-27
WO2017146882A1 (en) 2017-08-31
EP3420460B1 (en) 2021-04-07
CN108701093A (zh) 2018-10-23
JP2019509557A (ja) 2019-04-04
US10176096B2 (en) 2019-01-08
HK1256013A1 (zh) 2019-09-13
TW201732599A (zh) 2017-09-16
EP3420460A1 (en) 2019-01-02
US20170242793A1 (en) 2017-08-24
SG11201805988VA (en) 2018-09-27
BR112018017135A2 (pt) 2019-01-02

Similar Documents

Publication Publication Date Title
US20170212840A1 (en) Providing scalable dynamic random access memory (dram) cache management using tag directory caches
AU2022203960B2 (en) Providing memory bandwidth compression using multiple last-level cache (llc) lines in a central processing unit (cpu)-based system
KR20190049742A (ko) 프로세서-기반 시스템들에서 공간 QoS(Quality of Service) 태깅을 사용한 이종 메모리 시스템들의 유연한 관리의 제공
US9317448B2 (en) Methods and apparatus related to data processors and caches incorporated in data processors
WO2018052653A1 (en) Providing memory bandwidth compression using adaptive compression in central processing unit (cpu)-based systems
EP3420460B1 (en) Providing scalable dynamic random access memory (dram) cache management using dram cache indicator caches
EP2959391A1 (en) Methods and apparatus for intra-set wear-leveling for memories with limited write endurance
US20170371783A1 (en) Self-aware, peer-to-peer cache transfers between local, shared cache memories in a multi-processor system
CN119768778A (zh) 在基于处理器的设备中提供自适应高速缓存旁通
US10152261B2 (en) Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system
CN120604223B (zh) 在基于处理器的设备中提供内容感知高速缓存替换和插入策略
US12493552B1 (en) Performing snoop filter replacement based on history-augmented victimization priority values of snoop filter entries in processor-based devices
US20240176742A1 (en) Providing memory region prefetching in processor-based devices
BR112018017135B1 (pt) Circuito de gerenciamento em cache de memória de acesso aleatório dinâmica (dram), método para fornecer gerenciamento em cache dram e memória legível por computador
CN120359505A (zh) 用于将高速缓存行分配给较高级高速缓存存储器的基于处理器的系统
BR112018069720B1 (pt) Provisão de compactação de largura de banda de memória utilizando múltiplas linhas de cache de último nível (llc) em um sistema baseado em unidade central de processamento (cpu)

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20180817

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid