SG11201600820PA - Methods and structures to prevent sidewall defects during selective epitaxy - Google Patents
Methods and structures to prevent sidewall defects during selective epitaxyInfo
- Publication number
- SG11201600820PA SG11201600820PA SG11201600820PA SG11201600820PA SG11201600820PA SG 11201600820P A SG11201600820P A SG 11201600820PA SG 11201600820P A SG11201600820P A SG 11201600820PA SG 11201600820P A SG11201600820P A SG 11201600820PA SG 11201600820P A SG11201600820P A SG 11201600820PA
- Authority
- SG
- Singapore
- Prior art keywords
- structures
- methods
- defects during
- selective epitaxy
- during selective
- Prior art date
Links
- 230000007547 defect Effects 0.000 title 1
- 238000000407 epitaxy Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
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- H01L21/02656—Special treatments
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- H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
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Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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PCT/US2013/058084 WO2015034492A1 (en) | 2013-09-04 | 2013-09-04 | Methods and structures to prevent sidewall defects during selective epitaxy |
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Publication Number | Publication Date |
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SG11201600820PA true SG11201600820PA (en) | 2016-03-30 |
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Application Number | Title | Priority Date | Filing Date |
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SG11201600820PA SG11201600820PA (en) | 2013-09-04 | 2013-09-04 | Methods and structures to prevent sidewall defects during selective epitaxy |
Country Status (7)
Country | Link |
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US (1) | US9698013B2 (ko) |
EP (1) | EP3042390A4 (ko) |
KR (1) | KR102245485B1 (ko) |
CN (1) | CN105874564A (ko) |
SG (1) | SG11201600820PA (ko) |
TW (1) | TWI564939B (ko) |
WO (1) | WO2015034492A1 (ko) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
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US10177143B2 (en) * | 2015-10-28 | 2019-01-08 | Taiwan Semiconductor Manufacturing Company Limited | FinFET device and method for fabricating the same |
US9570297B1 (en) * | 2015-12-09 | 2017-02-14 | International Business Machines Corporation | Elimination of defects in long aspect ratio trapping trench structures |
JP6584348B2 (ja) * | 2016-03-07 | 2019-10-02 | 東京エレクトロン株式会社 | 凹部の埋め込み方法および処理装置 |
US9735010B1 (en) | 2016-05-27 | 2017-08-15 | International Business Machines Corporation | Fabrication of semiconductor fin structures |
US10249492B2 (en) * | 2016-05-27 | 2019-04-02 | International Business Machines Corporation | Fabrication of compound semiconductor structures |
US10453943B2 (en) * | 2016-11-29 | 2019-10-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | FETS and methods of forming FETS |
US10163628B1 (en) | 2017-05-31 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Lattice-mismatched semiconductor substrates with defect reduction |
WO2019059920A1 (en) * | 2017-09-22 | 2019-03-28 | Intel Corporation | SUBSTRATE DEFECT BLOCKING LAYERS FOR CONCEALED CHANNEL SEMICONDUCTOR DEVICES |
KR102651721B1 (ko) | 2019-01-09 | 2024-03-26 | 삼성전자주식회사 | 이미지 센서 |
KR20200141142A (ko) * | 2019-06-10 | 2020-12-18 | 삼성전자주식회사 | 반도체 장치 |
KR102644454B1 (ko) * | 2021-11-05 | 2024-03-08 | 한국과학기술연구원 | 언더컷 구조의 트렌치를 포함하는 반도체 소자 및 이를 제조하는 방법 |
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US6888214B2 (en) * | 2002-11-12 | 2005-05-03 | Micron Technology, Inc. | Isolation techniques for reducing dark current in CMOS image sensors |
WO2004044989A1 (en) * | 2002-11-12 | 2004-05-27 | Micron Technology, Inc. | Grounded gate and isolation techniques for reducing dark current in cmos image sensors |
US7012314B2 (en) | 2002-12-18 | 2006-03-14 | Agere Systems Inc. | Semiconductor devices with reduced active region defects and unique contacting schemes |
KR20040105980A (ko) * | 2003-06-10 | 2004-12-17 | 매그나칩 반도체 유한회사 | 반도체 소자의 얕은 트랜치 소자분리막 형성방법 |
JP5063594B2 (ja) * | 2005-05-17 | 2012-10-31 | 台湾積體電路製造股▲ふん▼有限公司 | 転位欠陥密度の低い格子不整合半導体構造およびこれに関連するデバイス製造方法 |
US20070066074A1 (en) * | 2005-09-19 | 2007-03-22 | Nace Rossi | Shallow trench isolation structures and a method for forming shallow trench isolation structures |
WO2007112066A2 (en) * | 2006-03-24 | 2007-10-04 | Amberwave Systems Corporation | Lattice-mismatched semiconductor structures and related methods for device fabrication |
US8338884B2 (en) * | 2009-05-12 | 2012-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Selective epitaxial growth of semiconductor materials with reduced defects |
US8334184B2 (en) * | 2009-12-23 | 2012-12-18 | Intel Corporation | Polish to remove topography in sacrificial gate layer prior to gate patterning |
EP2423951B1 (en) * | 2010-08-05 | 2016-07-20 | Imec | Antiphase domain boundary-free III-V compound semiconductor material on semiconductor substrate and method for manufacturing thereof |
CN102592966B (zh) * | 2011-01-12 | 2015-07-15 | 中国科学院微电子研究所 | 半导体器件及其制作方法 |
-
2013
- 2013-09-04 KR KR1020167003011A patent/KR102245485B1/ko active IP Right Grant
- 2013-09-04 SG SG11201600820PA patent/SG11201600820PA/en unknown
- 2013-09-04 WO PCT/US2013/058084 patent/WO2015034492A1/en active Application Filing
- 2013-09-04 EP EP13892844.5A patent/EP3042390A4/en not_active Withdrawn
- 2013-09-04 CN CN201380078661.XA patent/CN105874564A/zh active Pending
- 2013-09-04 US US14/908,987 patent/US9698013B2/en active Active
-
2014
- 2014-09-01 TW TW103130107A patent/TWI564939B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR20160051732A (ko) | 2016-05-11 |
US20160181099A1 (en) | 2016-06-23 |
US9698013B2 (en) | 2017-07-04 |
WO2015034492A1 (en) | 2015-03-12 |
EP3042390A4 (en) | 2017-04-12 |
TWI564939B (zh) | 2017-01-01 |
CN105874564A (zh) | 2016-08-17 |
TW201523702A (zh) | 2015-06-16 |
EP3042390A1 (en) | 2016-07-13 |
KR102245485B1 (ko) | 2021-04-29 |
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