SG11201503975VA - Process for fabricating a semiconductor-on-insulator substrate - Google Patents

Process for fabricating a semiconductor-on-insulator substrate

Info

Publication number
SG11201503975VA
SG11201503975VA SG11201503975VA SG11201503975VA SG11201503975VA SG 11201503975V A SG11201503975V A SG 11201503975VA SG 11201503975V A SG11201503975V A SG 11201503975VA SG 11201503975V A SG11201503975V A SG 11201503975VA SG 11201503975V A SG11201503975V A SG 11201503975VA
Authority
SG
Singapore
Prior art keywords
fabricating
semiconductor
insulator substrate
insulator
substrate
Prior art date
Application number
SG11201503975VA
Other languages
English (en)
Inventor
Christophe Gourdel
Oleg Kononchuk
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11201503975VA publication Critical patent/SG11201503975VA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
SG11201503975VA 2012-11-20 2013-09-25 Process for fabricating a semiconductor-on-insulator substrate SG11201503975VA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1203106A FR2998418B1 (fr) 2012-11-20 2012-11-20 Procede de fabrication d'un substrat de type semi-conducteur sur isolant
PCT/IB2013/002146 WO2014080256A1 (en) 2012-11-20 2013-09-25 Process for fabricating a semiconductor-on-insulator substrate

Publications (1)

Publication Number Publication Date
SG11201503975VA true SG11201503975VA (en) 2015-06-29

Family

ID=48128353

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201503975VA SG11201503975VA (en) 2012-11-20 2013-09-25 Process for fabricating a semiconductor-on-insulator substrate

Country Status (7)

Country Link
US (1) US9679799B2 (de)
KR (1) KR20150087244A (de)
CN (1) CN104798192B (de)
DE (1) DE112013005536T5 (de)
FR (1) FR2998418B1 (de)
SG (1) SG11201503975VA (de)
WO (1) WO2014080256A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3034565B1 (fr) 2015-03-30 2017-03-31 Soitec Silicon On Insulator Procede de fabrication d'une structure presentant une couche dielectrique enterree d'epaisseur uniforme

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4598241B2 (ja) * 2000-06-19 2010-12-15 新日本製鐵株式会社 Simox基板の製造方法
JP4407127B2 (ja) * 2003-01-10 2010-02-03 信越半導体株式会社 Soiウエーハの製造方法
US7524744B2 (en) * 2003-02-19 2009-04-28 Shin-Etsu Handotai Co., Ltd. Method of producing SOI wafer and SOI wafer
JP2011504655A (ja) * 2007-11-23 2011-02-10 エス. オー. アイ. テック シリコン オン インシュレーター テクノロジーズ 精密な酸化物の溶解
WO2009104060A1 (en) * 2008-02-20 2009-08-27 S.O.I.Tec Silicon On Insulator Technologies Oxidation after oxide dissolution
KR101596698B1 (ko) * 2008-04-25 2016-02-24 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치 제조 방법
JP5493345B2 (ja) * 2008-12-11 2014-05-14 信越半導体株式会社 Soiウェーハの製造方法
CN101587902B (zh) * 2009-06-23 2011-12-07 吉林大学 一种纳米绝缘体上硅结构材料及其制作方法

Also Published As

Publication number Publication date
DE112013005536T5 (de) 2015-07-30
FR2998418B1 (fr) 2014-11-21
FR2998418A1 (fr) 2014-05-23
US9679799B2 (en) 2017-06-13
CN104798192B (zh) 2017-08-25
CN104798192A (zh) 2015-07-22
KR20150087244A (ko) 2015-07-29
WO2014080256A1 (en) 2014-05-30
US20150311110A1 (en) 2015-10-29

Similar Documents

Publication Publication Date Title
EP2921202A4 (de) Verfahren zur herstellung einer folie für transdermale absorption
EP2891672A4 (de) Verfahren zur herstellung eines optischen materials auf thiourethanbasis
EP2865807A4 (de) Verfahren zur herstellung von pappe
EP2682217A4 (de) Verfahren zur herstellung eines gleitelements
SG11201502119TA (en) Method for manufacturing soi wafer
EP2894032A4 (de) Verfahren zur herstellung eines laminats
IL232838A0 (en) Process for the production of triazinon-benzoxazinones
SG11201501873QA (en) Method for manufacturing soi wafer
EP2894659A4 (de) Herstellungsverfahren für eine vorrichtung
SG10201602816XA (en) B2f4 manufacturing process
EP2763517A4 (de) Substratherstellungsverfahren
GB201219704D0 (en) A process for manufacturing a fixing device
IL219622A0 (en) A process for obtaining microcapsules
PL2476684T3 (pl) Sposób wytwarzania alkilofosforanów
IL237007A0 (en) Semiconductor component and process for manufacturing a semiconductor component
IL232840A (en) Process for the production of aryloxyacetamides
SG11201500870YA (en) Soi wafer manufacturing method
EP2858092A4 (de) Verfahren zur herstellung eines soi-wafers
LT2824070T (lt) Didelio grynumo silicio gamybos būdas
HK1200429A1 (zh) 製造封裝裝置的方法
LU91987B1 (en) Method for manufacturing a semiconductor thin film
LU91986B1 (en) Method for manufacturing a semiconductor thin film
PL2872305T3 (pl) Sposób wytwarzania folii
SG11201503975VA (en) Process for fabricating a semiconductor-on-insulator substrate
GB2517891B (en) Manufacturing process