SG10201908165TA - Three-dimensional semiconductor memory devices - Google Patents

Three-dimensional semiconductor memory devices

Info

Publication number
SG10201908165TA
SG10201908165TA SG10201908165TA SG10201908165TA SG10201908165TA SG 10201908165T A SG10201908165T A SG 10201908165TA SG 10201908165T A SG10201908165T A SG 10201908165TA SG 10201908165T A SG10201908165T A SG 10201908165TA SG 10201908165T A SG10201908165T A SG 10201908165TA
Authority
SG
Singapore
Prior art keywords
semiconductor memory
memory devices
dimensional semiconductor
dimensional
devices
Prior art date
Application number
SG10201908165TA
Inventor
Kang Joo-Heon
Park Bongtae
Shim Jae-Joo
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10201908165TA publication Critical patent/SG10201908165TA/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
SG10201908165TA 2018-10-26 2019-09-04 Three-dimensional semiconductor memory devices SG10201908165TA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020180128922A KR102670089B1 (en) 2018-10-26 2018-10-26 Three-dimensional semiconductor memory devices

Publications (1)

Publication Number Publication Date
SG10201908165TA true SG10201908165TA (en) 2020-05-28

Family

ID=70325418

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201908165TA SG10201908165TA (en) 2018-10-26 2019-09-04 Three-dimensional semiconductor memory devices

Country Status (4)

Country Link
US (1) US10784281B2 (en)
KR (1) KR102670089B1 (en)
CN (1) CN111106127B (en)
SG (1) SG10201908165TA (en)

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9536970B2 (en) 2010-03-26 2017-01-03 Samsung Electronics Co., Ltd. Three-dimensional semiconductor memory devices and methods of fabricating the same
KR101800438B1 (en) * 2010-11-05 2017-11-23 삼성전자주식회사 Three Dimensional Semiconductor Memory Device And Method Of Fabricating The Same
KR20130116607A (en) * 2012-04-16 2013-10-24 삼성전자주식회사 Three dimensional semiconductor memory device and method of fabricating the same
US9230980B2 (en) 2013-09-15 2016-01-05 Sandisk Technologies Inc. Single-semiconductor-layer channel in a memory opening for a three-dimensional non-volatile memory device
US10685972B2 (en) * 2014-09-26 2020-06-16 Samsung Electronics Co., Ltd. Semiconductor memory devices and methods for fabricating the same
US9305937B1 (en) * 2014-10-21 2016-04-05 Sandisk Technologies Inc. Bottom recess process for an outer blocking dielectric layer inside a memory opening
US9379132B2 (en) * 2014-10-24 2016-06-28 Sandisk Technologies Inc. NAND memory strings and methods of fabrication thereof
US9627402B2 (en) * 2015-02-11 2017-04-18 Kabushiki Kaisha Toshiba Semiconductor memory device and method for manufacturing the same
KR102400184B1 (en) * 2015-03-17 2022-05-20 삼성전자주식회사 Three dimension semiconductor device and method of fabricating the same
US9524977B2 (en) 2015-04-15 2016-12-20 Sandisk Technologies Llc Metal-semiconductor alloy region for enhancing on current in a three-dimensional memory structure
US9941295B2 (en) 2015-06-08 2018-04-10 Sandisk Technologies Llc Method of making a three-dimensional memory device having a heterostructure quantum well channel
US9613977B2 (en) * 2015-06-24 2017-04-04 Sandisk Technologies Llc Differential etch of metal oxide blocking dielectric layer for three-dimensional memory devices
US10020317B2 (en) * 2015-08-31 2018-07-10 Cypress Semiconductor Corporation Memory device with multi-layer channel and charge trapping layer
KR102440221B1 (en) * 2015-09-09 2022-09-05 삼성전자주식회사 Semiconductor devices and methods of manufacturing the same
KR20170036878A (en) * 2015-09-18 2017-04-03 삼성전자주식회사 Three dimensional semiconductor device
US9842651B2 (en) 2015-11-25 2017-12-12 Sunrise Memory Corporation Three-dimensional vertical NOR flash thin film transistor strings
KR102532490B1 (en) * 2015-10-08 2023-05-17 삼성전자주식회사 Semiconductor device and method for manufacturing the same
US9876025B2 (en) 2015-10-19 2018-01-23 Sandisk Technologies Llc Methods for manufacturing ultrathin semiconductor channel three-dimensional memory devices
US10181477B2 (en) 2016-03-11 2019-01-15 Toshiba Memory Corporation Semiconductor device and method for manufacturing same
US10121794B2 (en) 2016-06-20 2018-11-06 Sandisk Technologies Llc Three-dimensional memory device having epitaxial germanium-containing vertical channel and method of making thereof
KR102566770B1 (en) 2016-07-27 2023-08-16 삼성전자주식회사 Method of manufacturing a semiconductor device
KR102636463B1 (en) * 2016-10-05 2024-02-14 삼성전자주식회사 Semiconductor memory device
KR102607595B1 (en) * 2016-10-13 2023-11-30 삼성전자주식회사 Semiconducto device including a dielectric layer
KR102658193B1 (en) * 2016-11-07 2024-04-17 삼성전자주식회사 Semiconductor device including a channel structure
KR102627897B1 (en) * 2018-09-18 2024-01-23 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
CN111106127A (en) 2020-05-05
US20200135756A1 (en) 2020-04-30
KR20200047909A (en) 2020-05-08
KR102670089B1 (en) 2024-05-28
US10784281B2 (en) 2020-09-22
CN111106127B (en) 2024-04-05

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