SG10201504476WA - Semiconductor packages and methods of packaging semiconductor devices - Google Patents

Semiconductor packages and methods of packaging semiconductor devices

Info

Publication number
SG10201504476WA
SG10201504476WA SG10201504476WA SG10201504476WA SG10201504476WA SG 10201504476W A SG10201504476W A SG 10201504476WA SG 10201504476W A SG10201504476W A SG 10201504476WA SG 10201504476W A SG10201504476W A SG 10201504476WA SG 10201504476W A SG10201504476W A SG 10201504476WA
Authority
SG
Singapore
Prior art keywords
methods
semiconductor
packaging
packages
semiconductor devices
Prior art date
Application number
SG10201504476WA
Inventor
Suthiwongsunthorn Nathapong
Jr Bambalan Dimaano Antonio
Huang Rui
Hong Tan Hua
Sae Le Kriangsak
Yeung Ho Beng
Agbisit De Vera Nelson
Adeva Robles Roel
Linsangan Micla Wedanni
Original Assignee
Utac Headquarters Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Utac Headquarters Pte Ltd filed Critical Utac Headquarters Pte Ltd
Publication of SG10201504476WA publication Critical patent/SG10201504476WA/en

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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
SG10201504476WA 2014-06-08 2015-06-08 Semiconductor packages and methods of packaging semiconductor devices SG10201504476WA (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201462009309P 2014-06-08 2014-06-08
US201462037128P 2014-08-14 2014-08-14
US201462081541P 2014-11-18 2014-11-18
US14/731,484 US9508623B2 (en) 2014-06-08 2015-06-05 Semiconductor packages and methods of packaging semiconductor devices

Publications (1)

Publication Number Publication Date
SG10201504476WA true SG10201504476WA (en) 2016-01-28

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