SG10201506143RA - Semiconductor device and method of forming double-sidedfan-out wafer level package - Google Patents

Semiconductor device and method of forming double-sidedfan-out wafer level package

Info

Publication number
SG10201506143RA
SG10201506143RA SG10201506143RA SG10201506143RA SG10201506143RA SG 10201506143R A SG10201506143R A SG 10201506143RA SG 10201506143R A SG10201506143R A SG 10201506143RA SG 10201506143R A SG10201506143R A SG 10201506143RA SG 10201506143R A SG10201506143R A SG 10201506143RA
Authority
SG
Singapore
Prior art keywords
sidedfan
semiconductor device
wafer level
level package
out wafer
Prior art date
Application number
SG10201506143RA
Inventor
Il Kwon Shim
Pandi C Marimuthu
Won Kyoung Choi
Sze Ping Goh
Jose A Caparas
Original Assignee
Stats Chippac Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Ltd filed Critical Stats Chippac Ltd
Publication of SG10201506143RA publication Critical patent/SG10201506143RA/en

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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
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    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L23/3178Coating or filling in grooves made in the semiconductor body
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
SG10201506143RA 2014-08-07 2015-08-05 Semiconductor device and method of forming double-sidedfan-out wafer level package SG10201506143RA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201462034354P 2014-08-07 2014-08-07
US14/814,906 US10453785B2 (en) 2014-08-07 2015-07-31 Semiconductor device and method of forming double-sided fan-out wafer level package

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SG10201506143RA true SG10201506143RA (en) 2016-03-30

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