KR102029544B1 - Fan-out semiconductor package - Google Patents

Abstract

The present disclosure discloses a semiconductor chip having a core member having a through hole, an active surface disposed in the through hole, and an inactive surface disposed opposite to the active surface, the at least a portion of the core member and the semiconductor chip being sealed. An encapsulant, and a connecting member disposed on the core member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad, wherein the core member surrounds a side of the semiconductor chip. Wherein the core member includes a plurality of wiring layers disposed at different levels, a dielectric is disposed between the plurality of wiring layers of the core member, and one of the plurality of wiring layers includes an antenna pattern. The other one of the wiring layers includes a ground pattern, and the antenna pattern is in signal with the connection pad via the redistribution layer. To a fan-out semiconductor package.

Description

Fan-Out Semiconductor Packages {FAN-OUT SEMICONDUCTOR PACKAGE}

The present disclosure relates to a fan-out semiconductor package in which an antenna pattern and a ground pattern are formed inside a package.

Applications using mm-Wave more than 10GHz are not only mobile 5G communication or 60GHz communication, but also motion sensor products that detect movement and increase user's I / F convenience, and security motion monitoring sensor to check intruders within a certain space. It is widely used in products, 24GHz and 77GHz Radar systems for near-field and far-field detection for automobiles. In the case of a product using such a mm-Wave, when transmitting a signal from a radio frequency integrated circuit (RFIC) to an antenna or from an antenna to an RFIC, a signal loss must be transmitted so as to prevent loss of the signal as much as possible. In the past, signal attenuation was minimized by connecting the distance between the RFIC and the antenna with a coaxial cable, but this is inefficient in terms of space and cost.

Recently, 60 GHz antennas were designed using low temperature co-fired ceramic (LTCC) materials in 60 GHz communication systems, and then applied to RFICs to minimize the distance between components. In addition, RFIC is mounted on the Main PCB (Printed Circuit Board) board in the automotive Radar system, and the antenna is formed by connecting the antenna in a pattern on the PCB board, or a separate antenna module is mounted on the Main PCB. Doing. However, this too is difficult to prevent the occurrence of the line loss between parts.

Recently, with the development of the package technology, a method of forming an antenna in an RFIC package is being developed. In some cases, an antenna pattern is formed in the RDL (Re-Distribution Layer) of the package. There are some design constraints or performance errors to ensure this. Therefore, there is a need for a reliable RFIC and antenna integrated package design technology that can minimize flexible design design and minimize design errors.

One of several objects of the present disclosure is to minimize the distance between the semiconductor chip and the antenna pattern to prevent loss of signal transmission, to ensure stable antenna performance in a single package, and to reduce the size of the entire package Furthermore, it provides a new type of fan-out semiconductor package structure that can simplify the process.

One of the various solutions proposed through the present disclosure is to introduce a core member having a through hole in the area for sealing the semiconductor chip, to place the semiconductor chip in the through hole of the core member, the core member including a dielectric To form antenna patterns and ground patterns on different levels of.

For example, a fan-out semiconductor package according to an example may include a core member having a through hole, a semiconductor chip having an active surface disposed in the through hole and having a connection pad disposed thereon, and an inactive surface opposite to the active surface. And a connecting member including an encapsulant for sealing at least a portion of the semiconductor chip and a redistribution layer disposed on the core member and an active surface of the semiconductor chip and connected to the connection pad, wherein the core member includes the semiconductor member. A single member surrounding the side of the chip, wherein the core member includes a plurality of wiring layers disposed at different levels, a dielectric is disposed between the plurality of wiring layers of the core member, and one of the plurality of wiring layers An antenna pattern, another one of the plurality of wiring layers includes a ground pattern, and the antenna pattern passes through the redistribution layer The connection pad may be connected to a signal.

One of the effects of the present disclosure is to minimize the distance between the semiconductor chip and the antenna to prevent loss of signal transmission, to ensure stable antenna performance in a single package, and to reduce the size of the entire package Furthermore, a new type of fan-out semiconductor package structure can be provided to simplify the process.

1 is a block diagram schematically illustrating an example of an electronic device system.
2 is a perspective view schematically showing an example of an electronic device.
3 is a cross-sectional view schematically showing before and after packaging of a fan-in semiconductor package.
4 is a cross-sectional view schematically illustrating a packaging process of a fan-in semiconductor package.
5 is a cross-sectional view schematically illustrating a case where a fan-in semiconductor package is mounted on a BGA substrate and finally mounted on a main board of an electronic device.
6 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is embedded in a BGA substrate and finally mounted on a main board of an electronic device.
7 is a cross-sectional view illustrating a schematic view of a fan-out semiconductor package.
8 is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a main board of an electronic device.
9 is a sectional view schematically showing an example of a fan-out semiconductor package.
FIG. 10 is a schematic plan view of the fan-out semiconductor package of FIG. 9 as viewed from above. FIG.
FIG. 11 is a schematic plan view of the fan-out semiconductor package of FIG. 9 as viewed from below. FIG.
FIG. 12 schematically illustrates types of antenna patterns that may be applied to the fan-out semiconductor package of FIG. 9.
FIG. 13 schematically illustrates a modification of an antenna pattern that may be applied to the fan-out semiconductor package of FIG. 9.
14A to 14F are process diagrams schematically illustrating an example of manufacturing the fan-out semiconductor package of FIG. 9.
15 is a schematic cross-sectional view of another example of a fan-out semiconductor package.
FIG. 16 is a schematic plan view of the fan-out semiconductor package of FIG. 15 as viewed from above. FIG.
17 is a schematic cross-sectional view of another example of a fan-out semiconductor package.
FIG. 18 is a schematic plan view of the fan-out semiconductor package of FIG. 17 as viewed from above. FIG.
19 is a schematic cross-sectional view of another example of a fan-out semiconductor package.
20 is a schematic plan view of various examples when the fan-out semiconductor package of FIG. 19 is viewed from above.
21 is a schematic cross-sectional view of another example of a fan-out semiconductor package.
FIG. 22 is a schematic plan view of the fan-out semiconductor package of FIG. 21 as viewed from above.
FIG. 23 is a schematic plan view of the fan-out semiconductor package of FIG. 21 as viewed from below.
24 is a sectional view schematically showing another example of a fan-out semiconductor package.
25 is a schematic cross-sectional view of another example of a fan-out semiconductor package.
26 is a schematic cross-sectional view of another example of a fan-out semiconductor package.
27 is a sectional view schematically showing another example of a fan-out semiconductor package.
28 is a sectional view schematically showing another example of a fan-out semiconductor package.
29 is a sectional view schematically showing another example of a fan-out semiconductor package.
30 is a schematic cross-sectional view of another example of a fan-out semiconductor package.
31 is a sectional view schematically showing another example of a fan-out semiconductor package.
32 is a schematic cross-sectional view illustrating an example in which a conventional fan-out semiconductor package is applied to a main board.
33 is a cross-sectional view schematically illustrating an example in which the fan-out semiconductor package of the present disclosure is applied to a main board.

Hereinafter, the present disclosure will be described with reference to the accompanying drawings. Shape and size of the elements in the drawings may be exaggerated or reduced for more clear description.

Electronics

1 is a block diagram schematically illustrating an example of an electronic device system.

Referring to the drawings, the electronic apparatus 1000 accommodates the main board 1010. The chip-related component 1020, the network-related component 1030, and the other component 1040 are physically and / or electrically connected to the main board 1010. These are also combined with other electronic components described later to form various signal lines 1090.

The chip related component 1020 may include a memory chip such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory; Application processor chips such as central processors (eg, CPUs), graphics processors (eg, GPUs), digital signal processors, cryptographic processors, microprocessors, microcontrollers; Logic chips, such as analog-to-digital converters and application-specific ICs (ASICs), are included, but are not limited thereto. In addition, other types of chip-related electronic components may be included. In addition, of course, these electronic components 1020 may be combined with each other.

Network-related components 1030 include Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM And any other wireless and wired protocols designated as GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and beyond. Any of the standards or protocols may be included. In addition, of course, the network related component 1030 may be combined with the chip related electronic component 1020.

Other components 1040 include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), electro magnetic interference (EMI) filters, multi-layer ceramic condenser (MLCC), and the like. However, the present invention is not limited thereto, and may include passive components used for various other purposes. In addition, the other components 1040 may be combined with each other along with the chip-related electronic component 1020 and / or the network-related electronic component 1030.

Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically connected to the main board 1010. Examples of other electronic components include camera 1050, antenna 1060, display 1070, battery 1080, audio codec (not shown), video codec (not shown), power amplifier (not shown), compass (Not shown), accelerometers (not shown), gyroscopes (not shown), speakers (not shown), mass storage devices (eg, hard disk drives) (not shown), compact disks (not shown), and DVD (digital versatile disk) (not shown) and the like, but is not limited to this, in addition to this may also include other electronic components used for various purposes, depending on the type of electronic device (1000). .

The electronic device 1000 may include a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer ( computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive, and the like. However, the present invention is not limited thereto, and may be any other electronic device that processes data.

2 is a perspective view schematically showing an example of an electronic device.

Referring to the drawings, the semiconductor package is applied to various electronic devices as described above for various uses. For example, a motherboard 1110 is accommodated in the body 1101 of the smartphone 1100, and various electronic components 1120 are physically and / or electrically connected to the motherboard 1110. In addition, other electronic components, such as the camera 1130, may or may not be physically and / or electrically connected to the motherboard 1110, are housed in the body 1101. A part of the electronic component 1120 may be a chip related component, for example, the semiconductor package 1121, but is not limited thereto. The electronic device is not necessarily limited to the smartphone 1100, and may be other electronic devices as described above.

Semiconductor package

Generally, a semiconductor chip is integrated with a large number of fine electric circuits, but it cannot function as a finished semiconductor by itself, and there is a possibility of being damaged by an external physical or chemical impact. Therefore, instead of using the semiconductor chip itself, the semiconductor chip is packaged and used for electronic devices in a packaged state.

The need for semiconductor packaging is due to the difference in circuit width between the semiconductor chip and the mainboard of the electronics, in terms of electrical connections. Specifically, in the case of a semiconductor chip, the size of the connection pad and the spacing between the connection pads are very small, whereas in the case of a main board used in electronic equipment, the size of the electronic component mounting pad and the spacing of the electronic component mounting pad are larger than the scale of the semiconductor chip. Much bigger. Therefore, it is difficult to directly mount a semiconductor chip on such a main board and a packaging technology that can buffer a difference in circuit width between each other is required.

The semiconductor package manufactured by the packaging technology may be classified into a fan-in semiconductor package and a fan-out semiconductor package according to structure and use.

Hereinafter, a fan-in semiconductor package and a fan-out semiconductor package will be described in more detail with reference to the accompanying drawings.

(Fan-in Semiconductor Package)

3 is a cross-sectional view schematically showing before and after packaging of a fan-in semiconductor package.

4 is a cross-sectional view schematically illustrating a packaging process of a fan-in semiconductor package.

Referring to the drawing, the semiconductor chip 2220 may include a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs), and the like, such as aluminum (Al) formed on one surface of the body 2221. For example, including a connection pad 2222 including a conductive material, and a passivation film 2223 formed on one surface of the body 2221 and covering at least a portion of the connection pad 2222, such as an oxide film or a nitride film. It may be an integrated circuit (IC) in a bare state. At this time, since the connection pad 2222 is very small, the integrated circuit IC may be hardly mounted on a middle level printed circuit board (PCB) as well as a main board of an electronic device.

Accordingly, in order to redistribute the connection pads 2222, the connection members 2240 are formed on the semiconductor chips 2220 in accordance with the size of the semiconductor chips 2220. The connection member 2240 forms an insulating layer 2241 on the semiconductor chip 2220 with an insulating material such as photosensitive insulating resin (PID), and forms a via hole 2243h for opening the connection pad 2222. The wiring patterns 2242 and the vias 2243 may be formed and formed. Thereafter, a passivation layer 2250 is formed to protect the connecting member 2240, an opening 2251 is formed, and an under bump metal layer 2260 is formed. That is, through a series of processes, for example, the fan-in semiconductor package 2200 including the semiconductor chip 2220, the connection member 2240, the passivation layer 2250, and the under bump metal layer 2260 is manufactured. do.

As described above, the fan-in semiconductor package is a package in which all connection pads of semiconductor chips, for example, I / O (Input / Output) terminals are arranged inside the device, and the fan-in semiconductor package has good electrical characteristics and can be produced at low cost. have. Therefore, many devices in a smart phone are manufactured in the form of a fan-in semiconductor package, and in particular, developments have been made to realize a small and fast signal transmission.

However, in the fan-in semiconductor package, all the I / O terminals must be disposed inside the semiconductor chip. Therefore, such a structure is difficult to apply to a semiconductor chip having a large number of I / O terminals or a small semiconductor chip. In addition, due to this vulnerability, a fan-in semiconductor package cannot be directly mounted and used on the main board of the electronic device. Even if the size and spacing of the I / O terminals of the semiconductor chip are enlarged by the rewiring process, they do not have the size and spacing enough to be directly mounted on the main board of the electronic device.

5 is a cross-sectional view schematically illustrating a case where a fan-in semiconductor package is mounted on a BGA substrate and finally mounted on a main board of an electronic device.

6 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is embedded in a BGA substrate and finally mounted on a main board of an electronic device.

Referring to the drawing, in the fan-in semiconductor package 2200, the connection pads 2222, that is, the I / O terminals of the semiconductor chip 2220 are redistributed once again through the BGA substrate 2301. The fan-in semiconductor package 2200 may be mounted on the BGA substrate 2301 on the main board 2500 of the electronic device. In this case, the solder ball 2270 may be fixed with the underfill resin 2280, etc., and the outside may be covered with the molding material 2290. Alternatively, the fan-in semiconductor package 2200 may be embedded in a separate BGA substrate 2302, and the connection pads 2222 of the semiconductor chip 2220 may be embedded by the BGA substrate 2302 in the embedded state. ), Ie, the I / O terminals may be redistributed once again and finally mounted on the motherboard 2500 of the electronic device.

As such, since the fan-in semiconductor package is difficult to be mounted directly on the main board of the electronic device, the fan-in semiconductor package is mounted on a separate BGA board and then again packaged and mounted on the main board of the electronic device or in the BGA board. It is mounted on the mainboard of the electronic device while being used.

(Fan-Out Semiconductor Package)

7 is a cross-sectional view illustrating a schematic view of a fan-out semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 2100, for example, the outside of the semiconductor chip 2120 is protected by the encapsulant 2130, and the connection pad 2122 of the semiconductor chip 2120 is connected to the connection member. By 2140, the semiconductor chip 2120 is rearranged to the outside of the semiconductor chip 2120. In this case, the passivation layer 2150 may be further formed on the connection member 2140, and the under bump metal layer 2160 may be further formed in the opening of the passivation layer 2150. The solder ball 2170 may be further formed on the under bump metal layer 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121, a connection pad 2122, a passivation layer (not shown), and the like. The connection member 2140 may include an insulating layer 2141, a redistribution layer 2142 formed on the insulating layer 2241, and a via 2143 for electrically connecting the connection pad 2122 and the redistribution layer 2142. Can be.

As described above, the fan-out semiconductor package is a form in which I / O terminals are rearranged to the outside of the semiconductor chip through a connection member formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all the I / O terminals of the semiconductor chip must be disposed inside the semiconductor chip, and as the device size becomes smaller, the ball size and pitch must be reduced, so that a standardized ball layout cannot be used. On the other hand, the fan-out semiconductor package is a type in which I / O terminals are rearranged to the outside of the semiconductor chip through a connection member formed on the semiconductor chip. Can be used as it is, as described below can be mounted on the main board of the electronic device without a separate BGA substrate.

8 is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a main board of an electronic device.

Referring to the drawing, the fan-out semiconductor package 2100 may be mounted on the main board 2500 of the electronic device through the solder ball 2170. That is, as described above, the fan-out semiconductor package 2100 may connect the connection pads 2122 on the semiconductor chip 2120 to a fan-out area beyond the size of the semiconductor chip 2120. Since 2140 is formed, a standardized ball layout may be used as it is, and as a result, it may be mounted on the main board 2500 of the electronic device without a separate BGA substrate.

As such, since the fan-out semiconductor package can be mounted on the main board of the electronic device without a separate BGA substrate, the fan-out semiconductor package can be made thinner and thinner than the fan-in semiconductor package using the BGA substrate. Its excellent thermal and electrical properties make it particularly suitable for mobile products. In addition, the present invention can be more compactly implemented than a typical package on package (POP) type using a printed circuit board (PCB), and solves a problem due to warpage.

Meanwhile, the fan-out semiconductor package refers to a package technology for mounting a semiconductor chip on a main board of an electronic device and the like, and protecting the semiconductor chip from external shocks. The concept is different from printed circuit boards (PCBs) such as BGA substrates in which fan-in semiconductor packages are embedded.

Hereinafter, a fan-out semiconductor package in which a core member having an antenna pattern and a ground pattern are formed in the semiconductor package will be described with reference to the drawings.

Fan-Out Semiconductor Packages

9 is a sectional view schematically showing an example of a fan-out semiconductor package.

FIG. 10 is a schematic plan view of the fan-out semiconductor package of FIG. 9 as viewed from above. FIG.

FIG. 11 is a schematic plan view of the fan-out semiconductor package of FIG. 9 as viewed from below. FIG.

Referring to the drawings, the fan-out semiconductor package 100A according to an example is disposed in the core member 110 having the through hole 110H, the active surface on which the connection pad 120P is disposed, and the active surface. The semiconductor chip 120, the core member 110, and the encapsulant 130 sealing at least a portion of the semiconductor chip 120 having an inactive surface opposite to the surface, and the core member 110 and the semiconductor chip 120 It includes a connecting member 140 disposed on the active surface. The semiconductor chip 120 is disposed in a so-called face-up form, with the active surface facing upwards based on the drawing. The core member 110 includes an insulating layer 111, and wiring layers 112a and 112b are formed at both sides of the insulating layer 111, and the wiring layers 112a and 112b are connected through the vias 113. The first wiring layer 112a of the core member 110 includes the antenna pattern 112aA, and the second wiring layer 112b includes the ground pattern 112bG. The first wiring layer 112a includes an antenna pattern 112aA. The antenna pattern 112aA is signally connected to the redistribution layer 142 via a feeding line 112aF, and is thereby signally connected to the connection pad 120P of the semiconductor chip 120. The under bump metal layer 160 and the electrical connection structure 170 are disposed below the core member 110, and thus the package 100A may be mounted on a main board or the like.

On the other hand, when the antenna is formed in one package together with the RFIC, it is necessary to consider how to implement the antenna, ground plane, dielectric material, feeding line, etc. to determine the resonance frequency and bandwidth of the antenna. For example, the distance between the antenna and the ground plane, which are sensitive to the antenna characteristics, that is, the thickness of the air layer or the thickness of the dielectric material must be maintained and managed to ensure stable radiation characteristics of the antenna. 32, the antenna 242A is formed on the redistribution layer 240 of the package 200A, but the ground surface 302G is formed on the main board 300. use. In this case, the thickness or distance (d) between the antenna 242A and the ground surface 302G should be secured to the height of the solder ball 270 of the package 200A. Thus, the package 200A may be placed on the main board 300. When mounted, thickness difference may occur depending on the height of the solder ball does not hesitate. In addition, in this case, since the air layer is used as the dielectric material, the size of the antenna 242A is increased. In this case, a flux or a foreign substance may be inserted into a space between the antenna 242A and the ground surface 302G, and as a result, characteristics of the antenna 242A may be greatly affected. In this case, when heat is generated in the RFIC 220, since it is difficult to secure a sufficient heat dissipation path, there is a limit to application to a product using a lot of power.

On the other hand, in the case of the fan-out semiconductor package 100A according to an example, as illustrated in FIG. 33, the antenna pattern 112aA is disposed on the upper and lower portions of the core member 110 while introducing the core member 110. ) And the ground pattern 112bG, even when mounted on the main board 300, a stable antenna pattern 112aA design structure, that is, the antenna pattern 112aA and the ground pattern ( The distance d1 between 112bG) may be stably secured to maintain the radiation characteristics of the antenna 112aG. In addition, by using the dielectric constant ε ₁ of the insulating layer 111 of the core member 110 to reduce the size of the antenna pattern 112aA to reduce the size of the entire package (100A), while increasing the spatial efficiency Cost reduction is also possible. In addition, performance degradation of the antenna pattern 112aA due to the influence of foreign matter on the antenna pattern 112aA and the ground pattern 112bG space can also be prevented. In addition, the solder ball is not forced to the electrical connection structure 170, it is possible to implement the electrical connection structure 170 in a very thin thickness.

In particular, in the case of the fan-out semiconductor package 100A according to an example, as illustrated in FIGS. 10 and 11, one unseparated substrate having a large area on the upper and lower surfaces of the core member 110 is illustrated. The antenna pattern 112aA and the ground pattern 112bG are first formed in the core member 110, and then the semiconductor chip 120 such as RFIC is formed in the through hole 110H of the core member 110. ) Is placed. That is, the core member 110 is a member having one large area, but is not composed of a plurality of unit members. Therefore, the manufacturing process is simple and the cost is reduced, such that the ground surface for the antenna pattern 112aA of the first wiring layer 112a or other various signal patterns can be solved with one ground pattern 112bG of the second wiring layer 112b. This is possible. In addition, when the semiconductor chip 120 is surrounded by the core member 110 formed as a base as described above, it may be more effective for warpage control of the package 100A, and as described later, the core member ( When the metal layer is formed on the wall surface of the through hole 110H of the 110, the metal layer may surround the semiconductor chip 120 without disconnection, and thus the heat dissipation effect or the electromagnetic shielding effect may be excellent.

On the other hand, the connection is used in the present disclosure is a concept that includes both the case of being electrically connected as well as the case of physically connected. In addition, the concept includes not only being directly connected but also indirectly connected. In addition, electrically or signally connected means a concept including both physically connected and unconnected.

Hereinafter, the components of the fan-out semiconductor package 100A according to an example will be described in more detail with reference to the accompanying drawings.

The core member 110 includes wiring layers 112a and 112b for redistributing the connection pads 120P of the semiconductor chip 120, thereby reducing the number of layers of the connection member 140. If necessary, the rigidity of the package 100A can be improved according to the material of the insulating layer 111 constituting the core member 110, and the thickness uniformity of the encapsulant 130 can be ensured. The fan-out semiconductor package 100A according to an example may be utilized as a package on package (PoP) type by the core member 110. That is, the core member 110 may be used as a connecting member. The core member 110 has a through hole 110H. In the through hole 110H, the semiconductor chip 120 is disposed to be spaced apart from the core member 110 by a predetermined distance. The side of the semiconductor chip 120 is surrounded by the core member 110.

The core member 110 includes an insulating layer 111, a first wiring layer 112a disposed above the insulating layer 111, a second wiring layer 112b disposed below the insulating layer 111, and an insulating layer ( And a via 113 penetrating through the 111 and connecting the first and second wiring layers 112a and 112b. The wiring layers 112a and 112b of the core member 110 may be thicker than the redistribution layer 142 of the connection member 140. The core member 110 may have a thickness similar to or greater than that of the semiconductor chip 120, and the wiring layers 112a and 112b may also be formed in a larger size through a substrate process according to the scale. On the other hand, the redistribution layer 142 of the connection member 140 may be formed in a smaller size through a semiconductor process for thinning.

The material of the insulating layer 111 is not specifically limited. For example, an insulating material may be used, wherein the insulating material is a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or these resins together with an inorganic filler and glass fiber (Glass Fiber, Glass Cloth, Glass Fabric). Resin impregnated with a core material such as, for example, prepreg, Ajinomoto Build-up Film (ABF), FR-4, Bisaleimide Triazine (BT) and the like can be used.

The wiring layers 112a and 112b may redistribute the connection pads 120P of the semiconductor chip 120. It may also include a specific pattern, such as antenna pattern 112aA. The materials for forming the wiring layers 112a and 112b include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti). Or conductive materials such as alloys thereof can be used. The wiring layers 112a and 112b may perform various functions according to the design design of the layer. For example, it may include a ground (GrouND) pattern, a power (PoWeR: PWR) pattern, a signal (S) pattern, and the like. Here, the signal S pattern includes various signals except for a ground GND pattern, a power PWR pattern, and the like, for example, a data signal and a frequency signal. In addition, various pad patterns may be included.

The first wiring layer 112a includes a feeding line 112aF for connecting the antenna pattern 112aA and the antenna pattern 112aA to the connection pad 120P of the semiconductor chip 120. The antenna pattern 112aA is connected to the signal connection pad 120PS of the connection pad 120P via the signal pattern 142S of the redistribution layer 142. The first wiring layer 112a may further include a plate-shaped ground pattern 112bG, a pad 112bPG for ground connection, a pad 112bPS for signal connection, and the like. The second wiring layer 112b includes a ground pattern 112bG. The ground pattern 112bG is connected to the ground connection pad 120PG among the connection pads 120P through the ground pattern 142G of the redistribution layer 142. The ground pattern 112bG may be formed in a plate shape to occupy most of the lower surface of the insulating layer 111. The ground pattern 112bG may serve as a ground of the antenna pattern 112aA, the semiconductor chip 120, and various signal patterns. In addition to the ground pattern 112bG, the second wiring layer 112b may include an electrical connection structure pad 112aPS for signal connection or an electrical connection structure pad 112aPG for ground connection.

As such, the fan-out semiconductor package 100A according to an example has an antenna pattern 112aA and a ground pattern 112bG on both sides of the core member 110, and between the antenna pattern 112aA and the ground pattern 112bG. It is possible to secure the distance to maintain the radiation characteristics of the antenna (112aG), and by using the dielectric constant in the core member 110, that is, the dielectric constant of the insulating layer 111 to reduce the size of the antenna pattern (112aA) the entire package By reducing the size of the 100A, it is possible to increase the space efficiency and reduce the cost. In addition, the performance of the antenna pattern 112aA due to the effect of foreign matter on the antenna pattern 112aA and the ground pattern 112bG space can be prevented, and the solder ball may not be forced to the electrical connection structure 170, and the thinness is also reduced. It is possible.

The vias 113 connect the wiring layers 112a and 112b formed on different layers, thereby forming an electrical path in the core member 110. The via 113 may include a via 113S for signal connection, a via 113G for ground connection, and the like. The vias 113 may also be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or Conductive materials, such as these alloys, can be used. Via 113 may be completely filled with a conductive material, or the conductive material may be formed along the wall of the via hole. In addition, all known shapes such as an hourglass shape or a cylindrical shape can be applied.

The semiconductor chip 120 may be a bare integrated circuit (IC) in which hundreds to millions of devices are integrated in one chip. The integrated circuit (IC) may be, for example, a radio-frequency integrated circuit (RFIC). That is, the fan-out semiconductor package 100A according to an example may be a package in which an RFIC and an mmWave / 5G antenna are integrated. The semiconductor chip 120 may include a body on which various circuits are formed, and a connection pad 120P may be formed on an active surface of the body. The body may be formed based on, for example, an active wafer, and in this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like may be used as the base material. The connection pad 120P is used to connect the semiconductor chip 120 to other components, and a conductive material, preferably aluminum (Al), may be used as the forming material, but is not limited thereto.

In the semiconductor chip 120, the surface on which the connection pad 120P is disposed is the active surface, and the opposite side is the inactive surface. In one example, the active surface of the semiconductor chip 120 is disposed in a face-up form to face upward. At this time, the connecting member 140 is also disposed above the core member 110. In addition, the first wiring layer 112a is disposed above the second wiring layer 112b. Accordingly, the feeding line 112aF of the antenna pattern 112aA is connected to the signal connection pad 120PS of the connection pad 120P of the semiconductor chip 120 through the signal redistribution layer 142S and the via 143S of the connection member 140. ), So that the length up to the feeding line 112aF of the antenna pattern 112aA can be minimized. Therefore, low insertion loss can be implemented.

The encapsulant 130 is a component for protecting the semiconductor chip 120 and providing an insulation region. The encapsulation form is not particularly limited, and may be a form enclosing at least a portion of the semiconductor chip 120. For example, the encapsulant 130 may cover the bottom surface of the core member 110 and may cover the side surface and the inactive surface of the semiconductor chip 120. In addition, at least a portion of the through hole 110H may be filled. The specific material of the encapsulant 130 is not particularly limited, and for example, an insulating material such as ABF may be used. If necessary, PIE (Photo Imageable Encapsulant) may be used as the material of the encapsulant 130.

The connection member 140 serves to connect the fan-out semiconductor package 100A with other external components. In addition, the connection pad 120P of the semiconductor chip 120 is redistributed. The connection member 140 is formed on the first insulating layer 141a, the redistribution layer 142 formed on the first insulating layer 141a, and the first insulating layer 141a to form the redistribution layer 142 on another layer. And a second insulating layer 141b disposed on the via 143 and the first insulating layer 141a to cover the redistribution layer 142.

An insulating material may be used as a material of the first insulating layer 141a. In this case, a photosensitive insulating material such as PID resin may be used as the insulating material. In this case, the first insulating layer 141a may be formed thinner, and the fine pitch of the via 143 may be more easily achieved. When the first insulating layer 141a is multi-layered, these materials may be identical to each other, and may be different from each other as necessary. In the case where the first insulating layer 141a is a multilayer, it may be integrated according to a process and the boundary may be unclear. An insulating material may also be used as the material of the second insulating layer 141b. In this case, ABF may be used as the insulating material. That is, the outermost layer of the connection member 140 may be a passivation layer.

The redistribution layer 142 may redistribute the connection pads 120P of the semiconductor chip 120, and the forming materials may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), and gold ( Conductive materials such as Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof may be used. The redistribution layer 142 may perform various functions according to the design design of the layer. For example, it may include a ground line 142G, a signal line 142S, and the like. In addition, it may include a pad 142PG for ground, a pad 142PS for a signal, and the like.

The via 143 connects the redistribution layer 142, the wiring layer 132, and the like formed on the different layers, and as a result, forms an electrical path in the connection member 140. The via 143 may also be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or Conductive materials, such as these alloys, can be used. Via 143 may also be completely filled with a conductive material, or the conductive material may be formed only along the walls of the via. In addition, all known shapes, such as taper shape and cylindrical shape, can be applied. Via 143 may also include via 143G for ground, via 143S for signal, and the like.

The under bump metal layer 160 improves the connection reliability of the electrical connection structure 170, and as a result, is an additional configuration for improving the board level reliability of the package 100A. The under bump metal layer 160 is connected to various pads 112aPG and 112aPS for the electrical connection structure of the first wiring layer 112a of the supporting member 140 exposed through the opening of the encapsulant 130. The under bump metal layer 160 may be formed in the opening of the encapsulant 130 by a known metallization method using a known conductive material, that is, a metal, but is not limited thereto.

The electrical connection structure 170 is an additional configuration for physically and / or electrically connecting the fan-out semiconductor package 100A to the outside. For example, the fan-out semiconductor package 100A may be mounted on the main board of the electronic device through the electrical connection structure 170. The electrical connection structure 170 may be formed of a solder made of a low melting point metal, for example, a tin (Sn) -aluminum (Al) -copper (Cu) alloy or the like, but this is only an example. The material is not particularly limited thereto. The electrical connection structure 170 may be a land, a ball, a pin, or the like. The electrical connection structure 170 may be formed of multiple layers or a single layer. If formed in a multi-layer may include a copper pillar (pillar) and solder, when formed in a single layer may include tin-silver solder or copper, but this is also merely an example and not limited thereto. . The number, spacing, arrangement, etc. of the electrical connection structure 170 is not particularly limited, and can be sufficiently modified according to design matters by those skilled in the art. For example, the number of the electrical connection structure 170 may be several tens to millions of pieces, depending on the number of connection pads 120P, may have a number more or less.

At least one of the electrical connection structures 170 is disposed in the fan-out area. The fan-out area refers to an area outside the area where the semiconductor chip 120 is disposed. Fan-out packages are more reliable than fan-in packages, enable multiple I / O terminals, and facilitate 3D interconnection. In addition, compared to a ball grid array (BGA) package and a land grid array (LGA) package, the package thickness can be manufactured thinner, and the price is excellent.

FIG. 12 schematically illustrates types of antenna patterns that may be applied to the fan-out semiconductor package of FIG. 9.

Referring to the drawings, the antenna pattern 112aA may be a dipole antenna as shown in (A), a folded dipole antenna as shown in (B), or (C) It may be a patch antenna as shown in the figure, or may be a coplanar patch antenna as shown in (D). However, the present invention is not limited thereto, and may be a ring antenna or a loop antenna, and the shape of each antenna may be various shapes such as square, square, circular, and radial. That is, the antenna pattern 112aA may be any type or form as long as it can implement mmWave / 5G.

FIG. 13 schematically illustrates a modification of an antenna pattern that may be applied to the fan-out semiconductor package of FIG. 9.

Referring to the drawings, the antenna pattern 112aA may include a plurality of patch antennas 112aA1, 112aA2, 112aA3, and 112aA4. Each of the patch antennas 112bA1 to 112bA4 may be connected to the signal connection pads 120PS through the respective feeding lines 112aF1, 112aF2, 112aF3, and 112aF4. Each patch antenna 112bA1, 112aA2, 112aA3, 112aA4 may include a transmit (Tx) antenna and a receive (Rx) antenna, and the number is not particularly limited.

14A to 14F are process diagrams schematically illustrating an example of manufacturing the fan-out semiconductor package of FIG. 9.

Referring to FIG. 14A, the core member 110 is prepared. The core member 110 may be prepared using one large area substrate such as copper clad laminate (CCL). That is, the first wiring layer 112a and the second wiring layer 112b are formed on both sides of the insulating layer 111 by using the copper clad laminate CCL, and the vias 113 penetrating the insulating layer 111 are formed. The core member 110 may be prepared. An antenna pattern 112aA, a feeding line 112aF, various pads 112aPS, 112aPG, and the like are formed as the first wiring layer 112a. A ground pattern 112bG, various pads 112bPS, 112bPG, and the like are formed as the second wiring layer 112b. The vias 113 form vias 113G for ground connection, vias 113S for signal connection, and the like. In addition, patterns, pads, vias, and the like for other powers can be formed. The wiring layers 112a and 112b may be formed by a known plating process, and the vias 113 may be formed by forming a via hole by a laser drill or the like and then filling the plating layer.

Referring to FIG. 14B, a through hole 110H is formed in the core member 110. The through hole 110H may be formed using a mechanical drill and / or a laser drill, and in this case, the desmear treatment may be performed in a subsequent process. Alternatively, the through hole 110H may be formed using sand blast or the like. The through hole 110H penetrates between an upper surface and a lower surface of the insulating layer 111. The size of the through hole 110H may be appropriately designed according to the size of the semiconductor chip 120. If necessary, after the through hole 110H is formed, a metal layer may be formed on the wall surface of the through hole 110H and then connected to the ground, as described later. In this case, the metal layer may also be used as the ground.

Referring to FIG. 14C, the semiconductor chip 120 is disposed using the adhesive film 190, and the semiconductor chip 120 is sealed with the encapsulant 130. Specifically, the core member 110 having the through hole 110H formed on the adhesive film 190 such as a tape is attached so that the first wiring layer 112a faces the adhesive film 190, and the through hole 110H is attached. The semiconductor chip 120 is attached onto the adhesive film 190 exposed through the active surface facing the adhesive film 190, and then sealed with the encapsulant 130. The encapsulant 130 may be formed by laminating an uncured film and curing the film, or may be formed by applying a liquid encapsulant 130 forming material by a known coating method and then curing the film. have.

Referring to FIG. 14D, the adhesive film 190 is removed, and the first insulating layer 141a is formed on the side where the first wiring layer 112a of the core member 110 is formed and on the active surface of the semiconductor chip 120. ). The first insulating layer 141a may be formed by laminating and curing an uncured PID, by applying and curing a PID forming material, or the like. This process may be performed with the encapsulant 130 attached to a carrier film 195 such as DCF.

Referring to FIG. 14E, the redistribution layer 142 and the via 143 are formed on the first insulating layer 141a, and the second insulating layer 141b is formed thereon to form the connection member 140. The redistribution layer 142 may include a signal line 142S, a ground line 142G, a pad 142PS for a signal, a pad 142PG for ground, and the like. Vias may also include vias 143S for signals, vias 143G for ground, and the like. Meanwhile, the redistribution layer 142 may be formed by a known plating process, and the via 143 may be formed by forming a via hole by a photolithography method and then filling it with plating.

Referring to FIG. 14F, the carrier film 195 is removed to form the under bump metal layer 160 and the electrical connection structure 170. Specifically, after the carrier film 195 is removed, the encapsulant 130 is opened with a laser or the like to open various pads 112aPG and 112aPS among the second wiring layers 112 ′ of the core member 110, and under bumps. The metal layer 160 and the electrical connection structure 170 are sequentially formed. Through a series of processes, a plurality of fan-out semiconductor packages 100A may be formed through one large area substrate, and each of them may be separated by each sawing through a dicing process, and a plurality of fan-outs may be performed in one process. The semiconductor package 100A may be manufactured.

15 is a schematic cross-sectional view of another example of a fan-out semiconductor package.

FIG. 16 is a schematic plan view of the fan-out semiconductor package of FIG. 15 as viewed from above. FIG.

Referring to the drawings, the fan-out semiconductor package 100B according to another example may further include a metal layer 115 disposed on the wall surface of the through hole 110H. The metal layer 115 may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, or the like. It may include a conductive material of. The metal layer 115 may be connected to the ground pattern 112bG of the second wiring layer 112b and used as the ground. When the first wiring layer 112a has the ground pattern 112aG, it may be connected thereto. The metal layer 115 is formed on the wall surface of the through hole 110H of the core member 110 using one large-area substrate, and may surround the side of the semiconductor chip 120 without disconnection, resulting in excellent heat dissipation. It can have an effect and excellent electromagnetic shielding effect.

Other components are substantially the same as described above, so detailed description thereof will be omitted. In addition, except that the metal layer 115 is formed on the wall surface of the through-hole 110H through plating, the manufacturing process is substantially the same as the fan-out semiconductor package 100A according to the above-described example, and thus a detailed description thereof will be omitted. .

17 is a schematic cross-sectional view of another example of a fan-out semiconductor package.

FIG. 18 is a schematic plan view of the fan-out semiconductor package of FIG. 17 as viewed from above. FIG.

Referring to the drawing, in the fan-out semiconductor package 100C according to another example, the first wiring layer 112a of the core member 110 includes a filter pattern 112aR. The filter pattern 112aR may be a strip type or a microstrip type, but is not limited thereto. One end of the filter pattern 112aR may be connected to the signal connection pad 120PS of the connection pad 120P of the semiconductor chip 120, and the other end thereof may be connected to the feeding line 112aF of the antenna pattern 112aA. The signal connection pad 120PS and the feeding line 112aF may be signaledly connected through the filter pattern 112aR, and as a result, various noises may be removed. On the other hand, the core member 110 is formed with a single large-area substrate as a base bar filter pattern (112aR) and the feeding line (112aF) is present on the same surface can be connected in a pattern only without a separate via. The ground pattern 112bG of the second wiring layer 112b may also serve as a ground for the filter pattern 112aR.

Other components are substantially the same as described above, so detailed description thereof will be omitted. In addition, except that the filter pattern 112aR is formed when the first wiring layer 112a is formed, the manufacturing process is substantially the same as the fan-out semiconductor package 100A according to the above-described example, and thus a detailed description thereof will be omitted. . Meanwhile, the metal layer 115 described in the fan-out semiconductor package 100B according to another example may be applied to the fan-out semiconductor package 100C according to another example.

19 is a schematic cross-sectional view of another example of a fan-out semiconductor package.

20 is a schematic plan view of various examples when the fan-out semiconductor package of FIG. 19 is viewed from above.

Referring to the drawings, the fan-out semiconductor package 100D according to another example includes an antenna pattern including a receive (Rx) antenna and a transmit (Tx) antenna, and the receive (Rx) antenna and transmit (Tx) antenna are separated. have. For example, as shown in (A), the transmitting antenna 112aA-1 is disposed on the left side and the receiving antenna 112aA-2 is disposed on the right side of the semiconductor chip 120, respectively. Signals may be connected to the semiconductor chip 120 through 112aF-2. Alternatively, as shown in (B), the receiving antennas 112aA-1 are disposed on the right side with respect to the semiconductor chip 120, and the transmitting antennas 112aA-2a and 112aA-2b are disposed above and below, respectively. Signals may be connected to the semiconductor chip 120 through 112aF-1, 112aF-2a, and 112aF-2b. Alternatively, as shown in (C), the transmitting antennas 112aA-1a and 112aA-1b are disposed on the left and right sides of the semiconductor chip 120, and the receiving antennas 112aA-2a and 112aA-2b are disposed above and below, respectively. The semiconductor chip 120 may be connected to the semiconductor chip 120 through the feeding lines 112aF-1a, 112aF-1b, 112aF-2a, and 112aF-2b. Alternatively, as shown in (D), the transmission antennas 112aA-1a and 112aA-1b are disposed at the upper left corner and the upper right corner of the semiconductor chip 120, and the lower left corner and the lower right corner. Receive antennas 112aA-2a and 112aA-2b may be disposed in the signal antennas and connected to the semiconductor chip 120 through feeding lines 112aF-1a, 112aF-1b, 112aF-2a and 112aF-2b, respectively. That is, the transmit (Tx) antenna and the receive (Rx) antenna may be arranged in various forms.

Other components are substantially the same as described above, so detailed description thereof will be omitted. In addition, except that the antenna pattern is formed in various forms when the first wiring layer 112a is formed, the manufacturing process is substantially the same as the fan-out semiconductor package 100A according to the above-described example, and thus a detailed description thereof will be omitted. . Meanwhile, the fan-out semiconductor package according to another example may include the metal layer 115 described in the fan-out semiconductor package 100B according to another example or the filter pattern 112aR described in the fan-out semiconductor package 100C according to another example. Of course, it can also be applied to (100D).

21 is a schematic cross-sectional view of another example of a fan-out semiconductor package.

FIG. 22 is a schematic plan view of the fan-out semiconductor package of FIG. 21 as viewed from above.

FIG. 23 is a schematic plan view of the fan-out semiconductor package of FIG. 21 as viewed from below.

Referring to the drawing, in the fan-out semiconductor package 100E according to another example, the semiconductor chip 120 is disposed in a so-called face-down form. In this case, the connection member 140 is disposed below the core member 110, and the under bump metal layer 160 and the electrical connection structure 170 are connected to the redistribution layer 142 of the connection member 140. 140 is formed below. On the other hand, the second wiring layer 112b of the core member 110 is disposed above the first wiring layer 112a, the first wiring layer 112a includes the ground pattern 112aG, and the second wiring layer 112b is An antenna pattern 112bA and a feeding line 112aF are included, and the via 113 includes a feeding line 113F. In this arrangement, the signal connection pad 120PS and the antenna pattern 112aA of the semiconductor chip 120 may be connected to the signal redistribution layer 142S and the signal via 143S of the connection member 140 and the core member 110. Although the path is lengthened by a signal connection through the via pad 112bPS for the signal of the second wiring layer 112b and the feeding line 113F of the via 113, the active surface of the semiconductor chip 120 Through the heat through the connection member 140 can be easily transferred to the main board and the like may be superior to the heat dissipation characteristics.

Other components are substantially the same as described above, so detailed description thereof will be omitted. Also, except that the under bump metal layer 160 and the electrical connection structure 170 are formed on the opposite side of the fan-out semiconductor package 100A according to an example so that the semiconductor chip 120 is disposed in a face-down manner. Since the manufacturing process is substantially the same as the fan-out semiconductor package 100A according to the above-described example, a detailed description thereof will be omitted.

24 is a sectional view schematically showing another example of a fan-out semiconductor package.

Referring to the drawings, the fan-out semiconductor package 100F according to another example may further include a metal layer 115 disposed on the wall surface of the through-hole 110H in the fan-out semiconductor package 100E according to another example described above. Include. The metal layer 115 may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, or the like. It may include a conductive material of. The metal layer 115 may be connected to the ground pattern 112aG of the first wiring layer 112a and used as the ground. When the second wiring layer 112b has the ground pattern 112bG, the second wiring layer 112b may be connected thereto. The metal layer 115 is formed on the wall surface of the through hole 110H of the core member 110 using one large-area substrate, and may surround the side of the semiconductor chip 120 without disconnection, resulting in excellent heat dissipation. It can have an effect and excellent electromagnetic shielding effect.

Other components are substantially the same as described above, so detailed description thereof will be omitted. In addition, the under bump metal layer 160 and the electrical connection structure 170 are formed to form the metal layer 115 on the wall surface of the through hole 110H through plating, and the semiconductor chip 120 is disposed in a face-down manner. Except for forming on the opposite side of the along-fan-out semiconductor package 100A, the manufacturing process is substantially the same as that of the fan-out semiconductor package 100A according to the above-described example, and thus a detailed description thereof will be omitted.

25 is a schematic cross-sectional view of another example of a fan-out semiconductor package.

Referring to the drawing, in the fan-out semiconductor package 100G according to another example, in the fan-out semiconductor package 100E according to the above-described another example, the first wiring layer 112a of the core member 110 may include a filter pattern ( 112aR). In addition, the metal layer 115 is further disposed. The filter pattern 112aR may be a strip type or a microstrip type, but is not limited thereto. One end of the filter pattern 112aR may be connected to the signal connection pad 120PS of the connection pad 120P of the semiconductor chip 120, and the other end thereof may be connected to the feeding line 112bF of the antenna pattern 112bA. The signal connection pad 120PS and the feeding line 112bF may be signaledly connected through the filter pattern 112aR, and as a result, various noises may be removed. Via 113 likewise includes feeding line 113F. The second wiring layer 112b includes a ground pattern 112bG for the filter pattern 112aR.

Other components are substantially the same as described above, so detailed description thereof will be omitted. In addition, the metal layer 115 is formed on the wall surface of the through hole 110H through plating, the filter pattern 112aR is formed when the first wiring layer 112a is formed, and the semiconductor chip 120 is face-down. The fan-out semiconductor package according to the above-described example is formed except that the under bump metal layer 160 and the electrical connection structure 170 are formed on the opposite side from the fan-out semiconductor package 100A according to the example. 100A) and the manufacturing process is substantially the same, detailed description thereof will be omitted.

26 is a schematic cross-sectional view of another example of a fan-out semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 100H according to another example, in the fan-out semiconductor package 100E according to the above-described another example, the second wiring layer 112b of the core member 110 may include a filter pattern ( 112bR). In addition, the metal layer 115 is further disposed. The filter pattern 112bR may be a strip type or a microstrip type, but is not limited thereto. One end of the filter pattern 112bR may be connected to the signal connection pad 120PS of the connection pad 120P of the semiconductor chip 120, and the other end thereof may be connected to the feeding line 112bF of the antenna pattern 112bA. The signal connection pad 120PS and the feeding line 112bF may be signaledly connected through the filter pattern 112bR, and as a result, various noises may be removed. Via 113 likewise includes feeding line 113F. On the other hand, the core member 110 is formed with a large area substrate as a base bar filter pattern (112bR) and the feeding line (112bF) is present on the same surface can be connected by a pattern only without a separate via. Ground pattern 112aG also provides ground for filter pattern 112bR.

Other components are substantially the same as described above, so detailed description thereof will be omitted. In addition, when the metal layer 115 is formed on the wall surface of the through hole 110H through plating, and when the second wiring layer 112b is formed, the filter pattern 112bR is formed and the semiconductor chip 120 is face-down. The fan-out semiconductor package according to the above-described example is formed except that the under bump metal layer 160 and the electrical connection structure 170 are formed on the opposite side from the fan-out semiconductor package 100A according to the example. 100A) and the manufacturing process is substantially the same, detailed description thereof will be omitted.

27 is a sectional view schematically showing another example of a fan-out semiconductor package.

Referring to the drawings, the fan-out semiconductor package 100I according to another example includes an antenna pattern including a receive (Rx) antenna and a transmit (Tx) antenna in the fan-out semiconductor package 100E according to another example. The receive (Rx) antenna and the transmit (Tx) antenna are separated. For example, as described above, the transmitting antennas 112bA-1 are disposed on the left side and the receiving antennas 112bA-2 are disposed on the right side of the semiconductor chip 120, respectively, to feed lines 112bF-1 and 112bF-, respectively. 2, 113bF-1, and 113bF-2 may be connected to the semiconductor chip 120. In addition, it may be disposed in the same form as in the fan-out semiconductor package 100D according to another example described above. That is, the transmit (Tx) antenna and the receive (Rx) antenna may be arranged in various forms.

Other components are substantially the same as described above, so detailed description thereof will be omitted. In addition, when the second wiring layer 112b is formed, the antenna patterns 112bA-1 and 112bA-2 are formed in various forms, and the under bump metal layer 160 and the semiconductor chip 120 are disposed in a face-down manner. The manufacturing process is substantially the same as the fan-out semiconductor package 100A according to the above-described example except that the electrical connection structure 170 is formed on the opposite side of the fan-out semiconductor package 100A according to the example. Detailed description will be omitted. Meanwhile, a fan according to another example may include the metal layers 115 described in the fan-out semiconductor package 100F according to another example or the filter patterns 112aR and 112bR described in the fan-out semiconductor packages 100G and 100H according to another example. Of course, it can be applied to the out-out semiconductor package 100I.

28 is a sectional view schematically showing another example of a fan-out semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 100J according to another example, the core member 110 may include the first insulating layer 111a and the first in the fan-out semiconductor package 100E according to another example. A first wiring layer 112a buried so as to expose a lower surface of the insulating layer 111a, a second wiring layer 112b disposed on an opposite side of the side on which the first wiring layer 112a of the first insulating layer 111a is disposed, The second insulating layer 111b is disposed on the first insulating layer 111a and covers the second wiring layer 112b, and the third wiring layer 112c is disposed on the second insulating layer 111b. The first to third wiring layers 112a, 112b and 112c are electrically connected to each other through the first and second vias 113a and 113b passing through the first and second insulating layers 111a and 111b, respectively. The lower surface of the first wiring layer 112a may have a step with the lower surface of the first insulating layer 111a. In this case, the insulating distance of the connecting member 140 may be more constant, and bleeding of the encapsulant 130 may be performed. This can be prevented to some extent. The first to third wiring layers 112a, 112b and 112c may be thicker than the redistribution layer 142.

The first wiring layer 112a includes the filter pattern 112aR, the second wiring layer 112b includes the ground pattern 112bG, and the third wiring layer 112c includes the antenna pattern 112cA. First and second vias 113a and 113b provide feeding lines 113aF and 113bF, respectively. The ground pattern 112bG may be ground for the antenna pattern 112cA and the filter pattern 112aR. As described above, when the core member 110 includes a larger number of wiring layers 112a, 112b, and 112c, the antenna pattern 112cA, the ground pattern 112bG, and the filter pattern 112aR may be arranged in various forms. Can be. Meanwhile, the first and second insulating layers 111a and 111b may be appropriately combined with materials having a high dielectric constant (Er1) to reduce the size of the antenna and materials having a low dielectric constant (Er2) to reduce the loss of the filter. Can be used.

Other components are substantially the same as described above, so detailed description thereof will be omitted. In addition, the under-bump metal layer 160 and the electrical connection structure 170 according to an example are manufactured by manufacturing the core member 110 using the coreless method and the semiconductor chip 120 is disposed in a face-down manner. The fan-out semiconductor package 100A and the manufacturing process according to the above-described example except that the opposite side of the out semiconductor package 100A and the other metal layer 115, the filter pattern 112bR, and the like are further formed. It is substantially the same, detailed description thereof will be omitted. The metal layer 115 described in the fan-out semiconductor package 100F according to another example may be applied to the fan-out semiconductor package 100J according to another example.

29 is a sectional view schematically showing another example of a fan-out semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 100K according to another example, the core member 110 may include the first insulating layer 111a and the first in the fan-out semiconductor package 100E according to another example. The first wiring layer 112a disposed below the insulating layer 111a, the second wiring layer 112b disposed above the first insulating layer 111a, and the first insulating layer 111a and disposed on the first wiring layer 112a. The second insulating layer 111b covering the 112a, the third wiring layer 112c disposed on the second insulating layer 111b, and the second insulating layer 111b disposed on the first insulating layer 111a and covering the second wiring layer 112b. The third insulating layer 111c and the fourth wiring layer 112d disposed on the third insulating layer 111c are included. The first through fourth wiring layers 112a, 112b, 112c, and 112d are electrically connected to the first through third vias 113a, 113b, and 113c passing through the first through third insulating layers 111a, 111b, and 111c, respectively. Is connected. The thickness of the first insulating layer 111a is thicker than the thickness of the second and third insulating layers 111b and 111c. The first insulating layer 111a may have a larger elastic modulus than the second and third insulating layers 111b and 111c. For example, the first insulating layer 111a may include a prepreg, and the second and third insulating layers 111b and 111c may include an ABF, but is not limited thereto. The first to fourth wiring layers 112a, 112b, 112c, and 112d may be thicker than the redistribution layer 142.

The first wiring layer 112a includes the filter pattern 112aR, the second wiring layer 112b includes the ground pattern 112bG, the third wiring layer 112c includes the ground pattern 112cG, and the fourth The wiring layer 112d includes the antenna pattern 112dA. First and third vias 113a and 113c provide feeding lines 113aF and 113cF, respectively. The ground pattern 112bG may be the ground of the antenna pattern 112dA and the filter pattern 112aR. The ground pattern 112cG may be the ground of the filter pattern 112aR. As described above, when the core member 110 includes a larger number of wiring layers 112a, 112b, 112c, and 112d, the antenna patterns 112dA, the ground patterns 112bG, 112cG, and the filter patterns 112aR may be more varied. Can be placed in the form. Meanwhile, the first to third insulating layers 111a, 111b, and 111c may be formed of a material having a high dielectric constant (Er1) to reduce the size of the antenna and a material having a low dielectric constant (Er2) to reduce the loss of the filter. It can use in combination suitably.

Other components are substantially the same as described above, so detailed description thereof will be omitted. In addition, when the core member 110 is formed, the under bump metal layer 160 is formed so that the wiring layers 112c and 112d are formed using the ABF as the build-up layer and the semiconductor chip 120 is disposed in the face-down form. ) And the electrical connection structure 170 are formed on the opposite side of the fan-out semiconductor package 100A according to an example, and other metal layers 115 or filter patterns 112aR, etc., are described above. Since the fan-out semiconductor package 100A and the manufacturing process of the example are substantially the same, detailed descriptions thereof will be omitted. The metal layer 115 described in the fan-out semiconductor package 100F according to another example may be applied to the fan-out semiconductor package 100K according to another example.

30 is a schematic cross-sectional view of another example of a fan-out semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 100L according to another example, the core member 110 may include the first to third insulating layers 111a, like the fan-out semiconductor package 100K according to the other example described above. 111b and 111c, first to fourth wiring layers 112a, 112b, 112c and 112d, and first to third vias 113a, 113b and 113c. At this time, filter patterns 112aR and 112cR are formed in different wiring layers 112a and 112c. That is, the filter patterns 112aR and 112cR are disposed at different levels and connected in an interlayer coupling manner.

Other components are substantially the same as described above, so detailed description thereof will be omitted. In addition, when the core member 110 is formed, the under bump metal layer 160 is formed so that the wiring layers 112c and 112d are formed using the ABF as the build-up layer and the semiconductor chip 120 is disposed in the face-down form. ) And the electrical connection structure 170 on the opposite side of the fan-out semiconductor package 100A according to an example, and further forming other metal layers 115 or filter patterns 112aR, 112cR, etc. Since the manufacturing process is substantially the same as the fan-out semiconductor package 100A according to the above-described example, a detailed description thereof will be omitted. The metal layer 115 described in the fan-out semiconductor package 100F according to another example may be applied to the fan-out semiconductor package 100L according to another example.

31 is a sectional view schematically showing another example of a fan-out semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 100M according to another example, the core member 110 may include the first to third insulating layers 111a, like the fan-out semiconductor package 100L according to the other example described above. 111b and 111c, the first through fourth wiring layers 112a, 112b, 112c and 112d, and the first through third vias 113a, 113b and 113c, wherein the filter patterns 112aR and 112cR are each other. It is formed in the other wiring layers 112a and 112c. That is, the filter patterns 112aR and 112aR are disposed at different levels and connected in an interlayer coupling manner. However, an insulating layer between the ground pattern 112cG and the antenna pattern 112dA so that the ground pattern 112cG of the third wiring layer 112c can be used as the ground of the antenna pattern 112dA of the fourth wiring layer 112d. Only the dielectrics 111a, 111b, and 111c are disposed, but the first wiring layer 112a and the second wiring layer 112b are not disposed. In this case, a distance filled with a dielectric between the ground pattern 112cG and the antenna pattern 112dA is increased to implement better antenna characteristics.

Other components are substantially the same as described above, so detailed description thereof will be omitted. In addition, when the core member 110 is formed, the under bump metal layer 160 is formed so that the wiring layers 112c and 112d are formed using the ABF as the build-up layer and the semiconductor chip 120 is disposed in the face-down form. ) And the electrical connection structure 170 on the opposite side of the fan-out semiconductor package 100A according to an example, and further forming other metal layers 115 or filter patterns 112aR, 112cR, etc. Since the manufacturing process is substantially the same as the fan-out semiconductor package 100A according to the above-described example, a detailed description thereof will be omitted. The metal layer 115 described in the fan-out semiconductor package 100F according to another example may be applied to the fan-out semiconductor package 100M according to another example.

The expression example used in the present disclosure does not mean the same embodiment, but is provided to emphasize different unique features. However, the examples presented above do not exclude implementations in combination with the features of other examples. For example, although a matter described in one particular example is not described in another example, it may be understood as a description related to another example unless otherwise described or contradicted with the matter in another example.

In the present disclosure, connected means a concept including not only directly connected but also indirectly connected. In addition, electrically or signally connected means a concept including both physically connected and unconnected. Also, the first and second expressions are used to distinguish one component from another, and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the right, the first component may be referred to as the second component, and similarly, the second component may be referred to as the first component.

In the present disclosure, the top, bottom, top, bottom, top, bottom, and the like are determined based on the accompanying drawings. For example, the first connection member is located above the redistribution layer. However, the claims are not limited thereto. In addition, the vertical direction refers to the above-mentioned upper and lower directions, and the horizontal direction refers to the direction perpendicular to this. In this case, the vertical cross section means a case cut in a plane in the vertical direction, and the cross-sectional view shown in the drawing may be exemplified. In addition, a horizontal cross section means the case cut | disconnected to the plane of a horizontal direction, for example, the top view shown by drawing is mentioned.

1000: electronic device 1010: mainboard
1020: chip-related parts 1030: network-related parts
1040: other components 1050: camera
1060: antenna 1070: display
1080: battery 1090: signal line
1100: smartphone 1101: smartphone body
1110: smartphone motherboard 1111: motherboard insulation layer
1112: motherboard wiring 1120: components
1121: semiconductor package 1130: smartphone camera
2200: fan-in semiconductor package
2220: semiconductor chip 2221: body
2222: connection pad 2223: passivation film
2240: connecting member 2241: insulating layer
2242: circuit layer 2243: via
2250: passivation layer 2260: under bump metal layer
2270: solder ball 2280: underfill resin
2290: molding material 2500: main board
2301: BGA substrate 2302: BGA substrate
2100: fan-out semiconductor package
2120: semiconductor chip 2170: solder ball
2121: body 2122: connection pad
2140: connecting member 2141: insulating layer
2142: circuit layer 2143: via
2150: passivation layer 2160: under bump metal layer
100A to 100M: Fan-Out Semiconductor Package
110: core member 110H: through hole
111, 111a to 111c: insulation layer 112a to 112d: wiring layer
113, 113a--113c: Via
120: semiconductor chip 120P: connection pad
130: suture
140: connecting member 141: insulating layer
142: redistribution layer 143: via
150: passivation layer 160: under bump metal layer
170: electrical connection structure 180: cover layer

Claims (15)

A core member having a through hole;
A semiconductor chip disposed in the through-hole in a face-up shape and having an active surface on which a connection pad is disposed and an inactive surface opposite to the active surface;
An encapsulant sealing the core member and at least a portion of the semiconductor chip; And
A connection member disposed on an upper side of the core member and an active surface of the semiconductor chip and including a redistribution layer connected to the connection pad; Including;
The core member is one member surrounding the side of the semiconductor chip,
The core member includes a plurality of wiring layers disposed at different levels,
A dielectric is disposed between the plurality of wiring layers of the core member.
The wiring layer disposed on the upper surface of the core member of the plurality of wiring layers includes an antenna pattern,
The wiring layer disposed on the lower surface of the core member of the plurality of wiring layers includes a ground pattern,
One surface of the connection member contacts the wiring layer disposed on the upper surface of the core member and the active surface of the semiconductor chip.
The antenna pattern is connected to the connection pad via the redistribution layer of the connection member,
Fan-out semiconductor package.
The method of claim 1,
At least one of the plurality of wiring layers includes a filter pattern,
The antenna pattern is signal connected to the connection pad via the filter pattern and the redistribution layer,
Fan-out semiconductor package.
The method of claim 2,
The antenna pattern and the filter pattern is formed on the same wiring layer,
Fan-out semiconductor package.
The method of claim 1,
The core member includes a first insulating layer, a first wiring layer disposed on a first side of the first insulating layer, and a second wiring layer disposed on a second side of the first insulating layer,
The first wiring layer includes the antenna pattern,
The second wiring layer includes the ground pattern,
Fan-out semiconductor package.
The method of claim 4, wherein
At least one of the first and second wiring layers includes a filter pattern,
The antenna pattern is signal connected to the connection pad via the filter pattern and the redistribution layer,
Fan-out semiconductor package.
The method of claim 1,
The core member may include a first insulating layer, a first wiring layer disposed to expose one surface of the first insulating layer, a second wiring layer disposed on an opposite side of the side on which the first wiring layer of the first insulating layer is disposed, A second insulating layer disposed on the first insulating layer and covering the second wiring layer, and a third wiring layer disposed on the second insulating layer,
At least one of the first and second wiring layers includes the ground pattern,
The third wiring layer includes the antenna pattern,
Fan-out semiconductor package.
The method of claim 6,
At least one of the first to third wiring layers includes a filter pattern,
The antenna pattern is signal connected to the connection pad via the filter pattern and the redistribution layer,
Fan-out semiconductor package.
The method of claim 1,
The core member may include a first insulating layer, a first wiring layer disposed on a first side of the first insulating layer, a second wiring layer disposed on a second side of the first insulating layer, and a first side of the first insulating layer. A second insulating layer disposed on the second insulating layer and covering the first wiring layer, a third wiring layer disposed on the second insulating layer, a third insulating layer disposed on a second side of the first insulating layer and covering the second wiring layer; And a fourth wiring layer disposed on the third insulating layer,
At least one of the first to third wiring layers includes the ground pattern,
The fourth wiring layer includes the antenna pattern,
Fan-out semiconductor package.
The method of claim 8,
At least one of the first to fourth wiring layers includes a filter pattern,
The antenna pattern is signal connected to the connection pad via the filter pattern and the redistribution layer,
Fan-out semiconductor package.
The method of claim 1,
The ground pattern is formed in one plate shape,
Fan-out semiconductor package.
The method of claim 1,
An electrical connection structure disposed below the core member; Further comprising,
Fan-out semiconductor package.
delete The method of claim 1,
A metal layer disposed on a wall surface of the through hole; More,
The metal layer is electrically connected to the ground pattern,
Fan-out semiconductor package.
The method of claim 1,
The antenna pattern includes a transmitting antenna pattern and a receiving antenna pattern,
Fan-out semiconductor package.
The method of claim 14,
The transmitting antenna pattern and the receiving antenna pattern are each plural,
Fan-out semiconductor package.

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