SE9602564L - Kretskortstest - Google Patents

Kretskortstest

Info

Publication number
SE9602564L
SE9602564L SE9602564A SE9602564A SE9602564L SE 9602564 L SE9602564 L SE 9602564L SE 9602564 A SE9602564 A SE 9602564A SE 9602564 A SE9602564 A SE 9602564A SE 9602564 L SE9602564 L SE 9602564L
Authority
SE
Sweden
Prior art keywords
test
signal
arrangement
circuit board
pattern
Prior art date
Application number
SE9602564A
Other languages
Unknown language ( )
English (en)
Other versions
SE9602564D0 (sv
SE515553C2 (sv
Inventor
Mikael Hedlund
Hans Hoegberg
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE9602564A priority Critical patent/SE515553C2/sv
Publication of SE9602564D0 publication Critical patent/SE9602564D0/sv
Priority to AU34708/97A priority patent/AU3470897A/en
Priority to PCT/SE1997/001148 priority patent/WO1998000724A1/en
Priority to US08/883,904 priority patent/US5812563A/en
Publication of SE9602564L publication Critical patent/SE9602564L/sv
Publication of SE515553C2 publication Critical patent/SE515553C2/sv

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2803—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] by means of functional tests, e.g. logic-circuit-simulation or algorithms therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
SE9602564A 1996-06-28 1996-06-28 Kretskortstest SE515553C2 (sv)

Priority Applications (4)

Application Number Priority Date Filing Date Title
SE9602564A SE515553C2 (sv) 1996-06-28 1996-06-28 Kretskortstest
AU34708/97A AU3470897A (en) 1996-06-28 1997-06-26 Circuit board test
PCT/SE1997/001148 WO1998000724A1 (en) 1996-06-28 1997-06-26 Circuit board test
US08/883,904 US5812563A (en) 1996-06-28 1997-06-27 Circuit board testing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9602564A SE515553C2 (sv) 1996-06-28 1996-06-28 Kretskortstest

Publications (3)

Publication Number Publication Date
SE9602564D0 SE9602564D0 (sv) 1996-06-28
SE9602564L true SE9602564L (sv) 1997-12-29
SE515553C2 SE515553C2 (sv) 2001-08-27

Family

ID=20403202

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9602564A SE515553C2 (sv) 1996-06-28 1996-06-28 Kretskortstest

Country Status (4)

Country Link
US (1) US5812563A (sv)
AU (1) AU3470897A (sv)
SE (1) SE515553C2 (sv)
WO (1) WO1998000724A1 (sv)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6092224A (en) * 1998-05-27 2000-07-18 Compaq Computer Corporation Logic analyzer probe assembly with probe and interface boards
KR100334660B1 (ko) * 2000-12-19 2002-04-27 우상엽 반도체 메모리 테스트 장치의 타이밍 클럭 제어기
US6685498B1 (en) 2002-09-27 2004-02-03 Ronald Jones Logic analyzer testing method and configuration and interface assembly for use therewith
US7307712B2 (en) * 2002-10-28 2007-12-11 Asml Netherlands B.V. Method of detecting mask defects, a computer program and reference substrate
EP1416326B1 (en) * 2002-10-28 2008-06-11 ASML Netherlands B.V. Method, inspection system, computer program and reference substrate for detecting mask defects
CN100383542C (zh) * 2003-11-07 2008-04-23 深圳创维－Rgb电子有限公司 检测电路板的方法及装置
US7188037B2 (en) * 2004-08-20 2007-03-06 Microcraft Method and apparatus for testing circuit boards
US8269505B2 (en) * 2009-12-15 2012-09-18 International Business Machines Corporation Locating short circuits in printed circuit boards
US8860448B2 (en) * 2011-07-15 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Test schemes and apparatus for passive interposers
US10520542B2 (en) * 2016-05-25 2019-12-31 Huntron, Inc. System for fault determination for electronic circuits
WO2022019814A1 (en) * 2020-07-22 2022-01-27 Telefonaktiebolaget Lm Ericsson (Publ) Method and system for testing a printed circuit board
TWI742865B (zh) * 2020-09-28 2021-10-11 蔚華科技股份有限公司 具數據處理功能的自動化測試機及其資訊處理方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4176780A (en) * 1977-12-06 1979-12-04 Ncr Corporation Method and apparatus for testing printed circuit boards
US4194113A (en) * 1978-04-13 1980-03-18 Ncr Corporation Method and apparatus for isolating faults in a logic circuit
CA1286724C (en) * 1986-03-27 1991-07-23 Richard Ralph Goulette Method and apparatus for monitoring electromagnetic emission levels
EP0527321A1 (de) * 1991-08-05 1993-02-17 Siemens Aktiengesellschaft Verfahren zur automatischen Fehlerdiagnose von elektrischen Baugruppen

Also Published As

Publication number Publication date
SE9602564D0 (sv) 1996-06-28
AU3470897A (en) 1998-01-21
US5812563A (en) 1998-09-22
WO1998000724A1 (en) 1998-01-08
SE515553C2 (sv) 2001-08-27

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Legal Events

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NUG Patent has lapsed