SE9203016L - Signalbehandlingssystem med delat dataminne - Google Patents

Signalbehandlingssystem med delat dataminne

Info

Publication number
SE9203016L
SE9203016L SE9203016A SE9203016A SE9203016L SE 9203016 L SE9203016 L SE 9203016L SE 9203016 A SE9203016 A SE 9203016A SE 9203016 A SE9203016 A SE 9203016A SE 9203016 L SE9203016 L SE 9203016L
Authority
SE
Sweden
Prior art keywords
data memory
shared data
processing system
signal processing
control processor
Prior art date
Application number
SE9203016A
Other languages
Unknown language ( )
English (en)
Swedish (sv)
Other versions
SE9203016D0 (sv
Inventor
L Svensson
J Zeberg
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE9203016A priority Critical patent/SE9203016L/
Publication of SE9203016D0 publication Critical patent/SE9203016D0/xx
Priority to PCT/SE1993/000840 priority patent/WO1994009437A1/fr
Priority to EP93923104A priority patent/EP0616710A1/fr
Priority to AU52900/93A priority patent/AU5290093A/en
Publication of SE9203016L publication Critical patent/SE9203016L/

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
SE9203016A 1992-10-14 1992-10-14 Signalbehandlingssystem med delat dataminne SE9203016L (sv)

Priority Applications (4)

Application Number Priority Date Filing Date Title
SE9203016A SE9203016L (sv) 1992-10-14 1992-10-14 Signalbehandlingssystem med delat dataminne
PCT/SE1993/000840 WO1994009437A1 (fr) 1992-10-14 1993-10-14 Systeme de traitement de signaux a memoire de donnees partagee
EP93923104A EP0616710A1 (fr) 1992-10-14 1993-10-14 Systeme de traitement de signaux a memoire de donnees partagee
AU52900/93A AU5290093A (en) 1992-10-14 1993-10-14 Signal handling system with a shared data memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9203016A SE9203016L (sv) 1992-10-14 1992-10-14 Signalbehandlingssystem med delat dataminne

Publications (2)

Publication Number Publication Date
SE9203016D0 SE9203016D0 (sv) 1992-10-14
SE9203016L true SE9203016L (sv) 1994-04-15

Family

ID=20387474

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9203016A SE9203016L (sv) 1992-10-14 1992-10-14 Signalbehandlingssystem med delat dataminne

Country Status (4)

Country Link
EP (1) EP0616710A1 (fr)
AU (1) AU5290093A (fr)
SE (1) SE9203016L (fr)
WO (1) WO1994009437A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2283596B (en) * 1993-11-01 1998-07-01 Ericsson Ge Mobile Communicat Multiprocessor data memory sharing
GB9418753D0 (en) * 1994-09-16 1994-11-02 Ionica L3 Limited Process circuitry
US6691216B2 (en) * 2000-11-08 2004-02-10 Texas Instruments Incorporated Shared program memory for use in multicore DSP devices
GB0031763D0 (en) * 2000-12-29 2001-02-07 Mitel Semiconductor Ltd Arbiter for a queue management system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2462745B1 (fr) * 1979-07-30 1986-01-03 Jeumont Schneider Dispositif de partage temporel de l'acces a une memoire connectee a un bus unique entre un calculateur central et une pluralite de calculateurs peripheriques
JPS56140459A (en) * 1980-04-04 1981-11-02 Hitachi Ltd Data processing system
US4504906A (en) * 1982-11-30 1985-03-12 Anritsu Electric Company Limited Multiprocessor system
US5067071A (en) * 1985-02-27 1991-11-19 Encore Computer Corporation Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus

Also Published As

Publication number Publication date
SE9203016D0 (sv) 1992-10-14
EP0616710A1 (fr) 1994-09-28
WO1994009437A1 (fr) 1994-04-28
AU5290093A (en) 1994-05-09

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