SE9200553D0 - PROCEDURE MAKES PREPARATION OF TWO BACKGROUNDING AREAS OF SINELY DIFFERENT DOPPING ON THE SURFACE OF A SEMICONDUCTOR BODY - Google Patents

PROCEDURE MAKES PREPARATION OF TWO BACKGROUNDING AREAS OF SINELY DIFFERENT DOPPING ON THE SURFACE OF A SEMICONDUCTOR BODY

Info

Publication number
SE9200553D0
SE9200553D0 SE9200553A SE9200553A SE9200553D0 SE 9200553 D0 SE9200553 D0 SE 9200553D0 SE 9200553 A SE9200553 A SE 9200553A SE 9200553 A SE9200553 A SE 9200553A SE 9200553 D0 SE9200553 D0 SE 9200553D0
Authority
SE
Sweden
Prior art keywords
semiconductor body
sinely
backgrounding
dopping
areas
Prior art date
Application number
SE9200553A
Other languages
Swedish (sv)
Other versions
SE9200553L (en
SE469916B (en
Inventor
K Bohlin
Original Assignee
Asea Brown Boveri
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asea Brown Boveri filed Critical Asea Brown Boveri
Priority to SE9200553A priority Critical patent/SE469916B/en
Publication of SE9200553D0 publication Critical patent/SE9200553D0/en
Priority to PCT/SE1993/000095 priority patent/WO1993017450A1/en
Publication of SE9200553L publication Critical patent/SE9200553L/en
Publication of SE469916B publication Critical patent/SE469916B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)

Abstract

Two self-aligned and contiguous regions (5, 7) of mutually different dopings can be generated at the surface (11) of a semiconductor body (1) by generating a first layer on the surface of the semiconductor body, selectively introducing a dopant through this layer within a defined portion of the semiconductor body at the surface thereof, changing the etching properties of the layer within said defined portion, removing the layer outside this portion by etching and, finally, doping the semiconductor body with the remaining part (21) of the layer as mask.
SE9200553A 1992-02-25 1992-02-25 Process for producing two adjacent regions of mutually different dopings at the surface of a semiconductor body SE469916B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
SE9200553A SE469916B (en) 1992-02-25 1992-02-25 Process for producing two adjacent regions of mutually different dopings at the surface of a semiconductor body
PCT/SE1993/000095 WO1993017450A1 (en) 1992-02-25 1993-02-03 Method for manufacturing two contiguous regions of mutually different dopings at the surface of a semiconductor body

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9200553A SE469916B (en) 1992-02-25 1992-02-25 Process for producing two adjacent regions of mutually different dopings at the surface of a semiconductor body

Publications (3)

Publication Number Publication Date
SE9200553D0 true SE9200553D0 (en) 1992-02-25
SE9200553L SE9200553L (en) 1993-08-26
SE469916B SE469916B (en) 1993-10-04

Family

ID=20385420

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9200553A SE469916B (en) 1992-02-25 1992-02-25 Process for producing two adjacent regions of mutually different dopings at the surface of a semiconductor body

Country Status (2)

Country Link
SE (1) SE469916B (en)
WO (1) WO1993017450A1 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4435896A (en) * 1981-12-07 1984-03-13 Bell Telephone Laboratories, Incorporated Method for fabricating complementary field effect transistor devices

Also Published As

Publication number Publication date
WO1993017450A1 (en) 1993-09-02
SE9200553L (en) 1993-08-26
SE469916B (en) 1993-10-04

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