WO1993017450A1 - Method for manufacturing two contiguous regions of mutually different dopings at the surface of a semiconductor body - Google Patents

Method for manufacturing two contiguous regions of mutually different dopings at the surface of a semiconductor body Download PDF

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Publication number
WO1993017450A1
WO1993017450A1 PCT/SE1993/000095 SE9300095W WO9317450A1 WO 1993017450 A1 WO1993017450 A1 WO 1993017450A1 SE 9300095 W SE9300095 W SE 9300095W WO 9317450 A1 WO9317450 A1 WO 9317450A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
semiconductor body
silicon
regions
nitrogen
Prior art date
Application number
PCT/SE1993/000095
Other languages
French (fr)
Inventor
Kjell Bohlin
Original Assignee
Asea Brown Boveri Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asea Brown Boveri Ab filed Critical Asea Brown Boveri Ab
Publication of WO1993017450A1 publication Critical patent/WO1993017450A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Abstract

Two self-aligned and contiguous regions (5, 7) of mutually different dopings can be generated at the surface (11) of a semiconductor body (1) by generating a first layer on the surface of the semiconductor body, selectively introducing a dopant through this layer within a defined portion of the semiconductor body at the surface thereof, changing the etching properties of the layer within said defined portion, removing the layer outside this portion by etching and, finally, doping the semiconductor body with the remaining part (21) of the layer as mask.

Description

Method for manufacturing two contiguous regions of mutually different dopinσs at the surface of a semiconductor body
TECHNICAL FIELD
The present invention relates to a method for manufacturing two contiguous regions of mutually different dopings at the surface of a semiconductor body.
BACKGROUND ART
In certain types of semiconductor devices it is desired to arrange two immediately adjacently located regions of different dopings at the surface of a semiconductor sub- strate. One typical example of such components are inte¬ grated circuits which comprise CMOS circuits. For each CMOS circuit there are arranged a p-doped region (p-pocket) and an n-doped region (n-pocket) adjacent to each other at the surface of a weakly doped silicon substrate. In that connec- tion it is known to form each type of pocket separately. With the aid of a first pattern there is formed a mask on the surface of the substrate with openings corresponding to the first type of pockets, whereupon the doping of these pockets takes place through the openings in the mask. After removal of this mask there is then generated, with the aid of a second pattern, a new mask with openings for the second type of pockets, which in their turn are produced by means of doping through the openings of this second mask. This known method requires two different patterns and two conse- cutive masking processes. This makes the manufacture com¬ plicated. Further, it is difficult to obtain an accurate fit of the two patterns to each other, which results in the packing density of the CMOS circuits becoming lower than desirable.
From US-A-4 435 896 a method for manufacturing CMOS circuits is previously known, in which only one masking step is required and in which the two regions of different doping types will automatically immediately adjoin each other. In this method a layer of silicon nitride is applied to the whole surface of the substrate. After masking, the silicon nitride layer is removed selectively by etching over a first of the two regions, after which this region is doped through the opening in the silicon nitride layer thus formed. With the remaining part of the silicon nitride layer as mask, a thick silicon oxide layer is then generated over this region, whereupon the silicon nitride layer is removed by etching. With this thick oxide layer as mask, the second of the two regions is then doped. With the aid of this known method, the two regions of different doping types will, as mentioned, immediately automatically adjoin each other, the regions become self-aligned. However, the method requires a relatively large number of process steps, among them two etching operations with intermediate oxidation steps prior to the doping of the second of the two regions. Therefore, the process will be relatively complicated and resource- demanding.
SUMMARY OF THE INVENTION
The invention aims to provide a method of the kind stated in the introductory part of the description, which can be carried out with a smaller number of process steps than what has previously been possible.
What characterizes a method according to the invention will become clear from the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will be explained in greater detail with reference to the accompanying Figures la-le and 2a-2e.
Figures la-le show successive steps in a method according to the invention, where a layer of silicon dioxide is selecti¬ vely transformed into a region of oxynitride, which is used as mask during the subsequent etching and doping. Figures 2a-2e show another method according to the invention, where a layer of polycrystalline silicon on the surface of the substrate is selectively transformed into a region of sili- con nitride, which is used as mask during the subsequent etching and doping.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Figure la shows the region nearest the surface of a sub¬ strate 1. This consists of a thin silicon wafer with a thickness of, for example, 500 μm. The substrate is weakly doped, for example weakly p-doped with a doping concentra¬ tion of, for example, 5 • 1014 at/cm3. The dopant may, for example, be boron. On the surface 11 of the substrate there is generated a silicon dioxide layer 2 in a manner known per se by thermal oxidation, that is, heating of the substrate in the presence of hydrogen and oxygen (oxidizing atmos¬ phere) . The oxide layer has a thickness of 2000 A.
As shown in Figure lb, there is applied, on top of the silicon dioxide layer 2, layer 3 of photoresist which is patterned by photolithographic methods in such a way that the layer is given an opening 31 for each one of the p-doped pockets which are to be formed. Thereafter, boron (4) is ion implanted into the substrate 1 through the opening 31 and the oxide layer 2. The energy of the implanted boron atoms is selected such that a concentration peak is obtained in the prospective p-pocket 5. The implanted boron dose may be 101 -1013 at/en*2.
After this, nitrogen is implanted through the opening 31 with an energy so chosen that a maximum concentration of the implanted nitrogen is obtained in the silicon dioxide layer. This is shown in Figure lc, where the designation 6 indi¬ cates the inflow of nitrogen ions during the ion implanta¬ tion. The implanted nitrogen dose may, for example, be 1016- 1017 at/cm2. After the nitrogen implantation and the removal of the mask layer 3, a heat treatment at a temperature of 800-1000°C is performed, the implanted nitrogen thus reacting with the silicon dioxide. That part of the layer 2 where nitrogen has been implanted, that is, the part of the layer located below the opening 31, is then transformed into an oxynitride (SixNyOz) . The above-mentioned heat treatment is preferably carried out in a saturated nitrogen atmosphere to prevent the out-diffusion of nitrogen during the heat treatment.
Thereafter, the non-transformed parts of the silicon dioxide layer 2 are removed by selective etching, whereas that part 21 of the oxide layer 2 which is transformed into oxynitride is substantially left untouched by the etching. As shown in Figure Id, an ion implantation of phosphorus (7) is then carried out. The remaining oxynitride layer 21 thereby serves as mask, that is, the phosphorus ions adhere to this layer whereas those parts of the substrate located outside the layer become n-doped, that is, form an n-pocket 8. Because of the chosen process, this n-pocket 8 will be automatically self-aligned to the p-pocket 5, that is, will immediately adjoin this pocket.
Finally, the oxynitride layer 21 is removed by an etching method and, if desired, the implanted dopants may be driven in by heat treatment.
Figure le shows the semiconductor body 1 with the contiguous regions, p-pocket 5 and n-pocket 8, manufactured with the aid of the method according to the invention. The thickness (depth below surface 11) of the regions is, for example, 2-4 μm and their doping concentrations about 1016 at/cm3.
Figures 2a-2e illustrate successive steps in an alternative method according to the invention. As shown in Figure 2a there is generated on the surface 11 of a semiconductor substrate 1 a thin silicon dioxide layer 12 with a thickness of, for example, 400 A. On this surface there is then deposited a layer 2 of polycrystalline silicon and with a thickness of, for example, 1000 A. The silicon dioxide layer 11 is suitably generated by thermal oxidation, and the silicon layer 2 with the aid of so-called LPCVD (Low Pressure Chemical Vapour Deposition) . In the same way as described with reference to Figure 1, there is then genera¬ ted, with the aid of photolithographic methods, a mask 3 with an opening 31 above each desired p-pocket. As shown in Figure 2b, an implantation of boron (4) is then carried out through the opening 31 and with energy so chosen that a maximum concentration is obtained in the desired p-pocket 5. As shown in Figure 2c, an ion implantation of nitrogen (6) is then carried out with energy so chosen that the nitrogen is deposited in the polycrystalline silicon layer 2. Because of the mask 3, nitrogen will be introduced into the layer 2 only within the region below the opening 31. The mask 3 is removed, and a heat treatment is carried out, for example in the same way as described with reference to Figure 1, where¬ by that part of the layer 2 which is located below the opening 31 will be transformed into silicon nitride - SixNy.
Those parts of the layer 2 which have not been transformed into silicon nitride, as well as the corresponding parts of the silicon dioxide layer 12, are removed by selective etching. As shown in Figure 2d, an ion implantation of phosphorus (7) , with the silicon nitride layer 21 as mask, is then carried out. In this process, the n-doped regions 8 in the figure are generated. Finally, the silicon nitride layer 21 and the part 121 located below the silicon dioxide layer 12 are removed by selective etching, a heat treatment is carried out to drive in the dopants further, and the semiconductor body is given the appearance shown in Figure 2e.
By a method according to the invention, self-aligned regions of different doping types can thus be generated at the sur¬ face of a semiconductor body in the simplest possible way, that is, with a minimum of process steps. These regions can then be used for forming CMOS circuits, in which case, for example, the p-pockets are used for forming n-channel tran¬ sistors and the n-pockets are used for forming p-channel transistors. The regions generated according to the inven- tion can, however, be used also for forming other types of semiconductor circuits or semiconductor devices, such as JFET or MESFET transistors or bipolar transistors.
In the embodiments of the invention described above, the layer whose etching properties have been selectively trans¬ formed has consisted of silicon dioxide or of polycrys¬ talline silicon. However, the inventive concept is not limited to these types of layers and in a method according to the invention also other types of layers can be used, the etching properties of which can be selectively changed. The inventive concept is also applicable to other types of semi¬ conductor materials than silicon. Nor, of course, is the invention limited to the dopants (boron and phosphorus) or doping methods (ion implantation) described above but can be applied in connection with other dopants and other doping methods, for example diffusion. Thus, for example, the p- pocket can be doped by ion implantation and thereafter the n-pocket be doped by diffusion.
In the embodiments described above, the two contiguous regions generated with the aid of the method according to the invention consist of regions with opposite doping types (p-conducting and n-conducting, respectively) . However, the invention can be generally used for generation of two con- tiguous regions of different dopings, for example two regions of the same doping type but with different doping concentrations, or different dopants.
Further, in the examples described above the first doping has been carried out prior to the nitrogen implantation, but the order between these steps may be the opposite. In simi¬ lar manner, of course, the n-pocket may be doped before the p-pocket, if desired. It has been described above how the nitrogen dose has been supplied to the layer 2 by means of ion implantation. Alternatively, the nitrogen dose may be supplied by ion irradiation from a high-frequency gas plasma (RF plasma) , which preferably or substantially consists of nitrogen gas.

Claims

1. A method for manufacturing two contiguous regions (5, 8) of mutually different dopings (P, N) at the surface (11) of a semiconductor body (1) , characterized in that
a first layer (2) is generated on the surface of the semiconductor body,
a dopant (4) is introduced selectively through said first layer in a defined portion of the semiconductor body at the surface thereof,
a change of the etching properties of said first layer (2) is made within said defined portion (31) ,
said first layer (2) is removed by etching outside said defined portion (31) ,
the semiconductor body is doped with the remaining part (21) of said first layer (2) as mask.
2. A method according to claim 1, characterized in that said first layer (2) consists of an oxide of .the material in the semiconductor body.
3. A method according to claim 2 in which the material in the semiconductor body consists of silicon, characterized in that said first layer (2) consists of a silicon oxide.
4. A method according to any of the preceding claims, characterized in that the change of the etching properties of said first layer (2) takes place by transformation of the layer into a nitrogen compound.
5. A method according to claim 4, characterized in that the transformation of said first layer (2) is made by introducing nitrogen into the layer, whereupon a heat treatment is carried out.
6. A method according to claim 5, characterized in that nitrogen is introduced by ion implantation.
7. A method according to any of the preceding claims, characterized in that the introduction of the dopants into said regions is made by ion implantation.
8. A method according to any of claims 1, 4-7, characterized in that said first layer (2) consists of a polycrystalline layer of the material in the semiconductor body.
9. A method according to claim 8 in which the material in the semiconductor body is silicon, characterized in that said first layer (2) consists of a layer of polycrystalline silicon, and in that a layer of a silicon oxide (12) is arranged between the surface (11) of the semiconductor body and said first layer (2) .
PCT/SE1993/000095 1992-02-25 1993-02-03 Method for manufacturing two contiguous regions of mutually different dopings at the surface of a semiconductor body WO1993017450A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9200553A SE469916B (en) 1992-02-25 1992-02-25 Process for producing two adjacent regions of mutually different dopings at the surface of a semiconductor body
SE9200553-7 1992-02-25

Publications (1)

Publication Number Publication Date
WO1993017450A1 true WO1993017450A1 (en) 1993-09-02

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4435896A (en) * 1981-12-07 1984-03-13 Bell Telephone Laboratories, Incorporated Method for fabricating complementary field effect transistor devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4435896A (en) * 1981-12-07 1984-03-13 Bell Telephone Laboratories, Incorporated Method for fabricating complementary field effect transistor devices

Also Published As

Publication number Publication date
SE9200553D0 (en) 1992-02-25
SE469916B (en) 1993-10-04
SE9200553L (en) 1993-08-26

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