SE449141B - Databehandlingsanleggning med ett minne der bitarna fornyas periodiskt - Google Patents

Databehandlingsanleggning med ett minne der bitarna fornyas periodiskt

Info

Publication number
SE449141B
SE449141B SE8102507A SE8102507A SE449141B SE 449141 B SE449141 B SE 449141B SE 8102507 A SE8102507 A SE 8102507A SE 8102507 A SE8102507 A SE 8102507A SE 449141 B SE449141 B SE 449141B
Authority
SE
Sweden
Prior art keywords
word
memory
module
error
address
Prior art date
Application number
SE8102507A
Other languages
English (en)
Swedish (sv)
Other versions
SE8102507L (sv
Inventor
M L Ziegler
M B Druke
Roekel J R Van
Ii W Baxter
Original Assignee
Data General Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Data General Corp filed Critical Data General Corp
Publication of SE8102507L publication Critical patent/SE8102507L/xx
Publication of SE449141B publication Critical patent/SE449141B/sv

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/106—Correcting systematically all correctable errors, i.e. scrubbing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
SE8102507A 1980-04-25 1981-04-21 Databehandlingsanleggning med ett minne der bitarna fornyas periodiskt SE449141B (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/143,675 US4380812A (en) 1980-04-25 1980-04-25 Refresh and error detection and correction technique for a data processing system

Publications (2)

Publication Number Publication Date
SE8102507L SE8102507L (sv) 1981-10-26
SE449141B true SE449141B (sv) 1987-04-06

Family

ID=22505098

Family Applications (1)

Application Number Title Priority Date Filing Date
SE8102507A SE449141B (sv) 1980-04-25 1981-04-21 Databehandlingsanleggning med ett minne der bitarna fornyas periodiskt

Country Status (9)

Country Link
US (1) US4380812A (cs)
JP (1) JPS56169300A (cs)
AU (1) AU544356B2 (cs)
CA (1) CA1165451A (cs)
DE (1) DE3115541A1 (cs)
FR (1) FR2481487B1 (cs)
GB (1) GB2075730B (cs)
NL (1) NL8102030A (cs)
SE (1) SE449141B (cs)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4493081A (en) * 1981-06-26 1985-01-08 Computer Automation, Inc. Dynamic memory with error correction on refresh
JPS59117800A (ja) * 1982-12-25 1984-07-07 Fujitsu Ltd バツフア・ストレ−ジの１ビツトエラ−処理方式
US4532628A (en) * 1983-02-28 1985-07-30 The Perkin-Elmer Corporation System for periodically reading all memory locations to detect errors
JPS59165300A (ja) * 1983-03-10 1984-09-18 Fujitsu Ltd メモリ障害訂正方式
US4535455A (en) * 1983-03-11 1985-08-13 At&T Bell Laboratories Correction and monitoring of transient errors in a memory system
US4542454A (en) * 1983-03-30 1985-09-17 Advanced Micro Devices, Inc. Apparatus for controlling access to a memory
JPS60229592A (ja) * 1984-04-27 1985-11-14 Mitsubishi Electric Corp 符号化伝送方式文字放送受信装置
EP0162936B1 (en) * 1984-05-26 1988-08-10 HONEYWELL BULL ITALIA S.p.A. Single error correction circuit for system memory
CA1234222A (en) * 1984-09-26 1988-03-15 Akira Matsushita Method and apparatus for error correction
US4899275A (en) * 1985-02-22 1990-02-06 Intergraph Corporation Cache-MMU system
JPS61214298A (ja) * 1985-03-20 1986-09-24 Toshiba Corp 誤り訂正機能を備えた半導体記憶装置
CA1240066A (en) * 1985-08-15 1988-08-02 John R. Ramsay Dynamic memory refresh and parity checking circuit
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
JPH01171199A (ja) * 1987-12-25 1989-07-06 Mitsubishi Electric Corp 半導体メモリ
EP0424301A3 (en) * 1989-10-18 1992-09-16 International Business Machines Corporation Overlapped data scrubbing with data refreshing
GB2239539B (en) * 1989-11-18 1994-05-18 Active Book Co Ltd Method of refreshing memory devices
US5127014A (en) * 1990-02-13 1992-06-30 Hewlett-Packard Company Dram on-chip error correction/detection
JP3146075B2 (ja) * 1992-10-14 2001-03-12 三菱電機株式会社 多重化メモリ装置
EP0600137A1 (en) * 1992-11-30 1994-06-08 International Business Machines Corporation Method and apparatus for correcting errors in a memory
JPH10177800A (ja) * 1996-10-21 1998-06-30 Texas Instr Inc <Ti> エラー訂正ダイナミック・メモリ及びそのエラー訂正方法
JP3177207B2 (ja) * 1998-01-27 2001-06-18 インターナショナル・ビジネス・マシーンズ・コーポレ−ション リフレッシュ間隔制御装置及び方法、並びにコンピュータ
US6701480B1 (en) * 2000-03-08 2004-03-02 Rockwell Automation Technologies, Inc. System and method for providing error check and correction in memory systems
US20020199153A1 (en) * 2001-06-22 2002-12-26 Fall Thomas G. Sampling method for use with bursty communication channels
US20030046630A1 (en) * 2001-09-05 2003-03-06 Mark Hilbert Memory using error-correcting codes to correct stored data in background
US7051264B2 (en) * 2001-11-14 2006-05-23 Monolithic System Technology, Inc. Error correcting memory and method of operating same
US7320100B2 (en) * 2003-05-20 2008-01-15 Cray Inc. Apparatus and method for memory with bit swapping on the fly and testing
US7099221B2 (en) * 2004-05-06 2006-08-29 Micron Technology, Inc. Memory controller method and system compensating for memory cell data losses
US7116602B2 (en) * 2004-07-15 2006-10-03 Micron Technology, Inc. Method and system for controlling refresh to avoid memory cell data losses
US7392456B2 (en) * 2004-11-23 2008-06-24 Mosys, Inc. Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory
US7894289B2 (en) 2006-10-11 2011-02-22 Micron Technology, Inc. Memory system and method using partial ECC to achieve low power refresh and fast access to data
US7900120B2 (en) 2006-10-18 2011-03-01 Micron Technology, Inc. Memory system and method using ECC with flag bit to identify modified data
US8245087B2 (en) * 2007-03-26 2012-08-14 Cray Inc. Multi-bit memory error management
KR20150018091A (ko) * 2013-08-09 2015-02-23 에스케이하이닉스 주식회사 오류 검출 회로 및 이를 이용한 데이터 처리 장치
WO2015152857A1 (en) * 2014-03-29 2015-10-08 Empire Technology Development Llc Energy-efficient dynamic dram cache sizing
US9990293B2 (en) 2014-08-12 2018-06-05 Empire Technology Development Llc Energy-efficient dynamic dram cache sizing via selective refresh of a cache in a dram
US9823964B2 (en) 2015-12-08 2017-11-21 Nvidia Corporation Method for memory scrub of DRAM with internal error correcting code (ECC) bits during either memory activate and/or precharge operation
US9880900B2 (en) 2015-12-08 2018-01-30 Nvidia Corporation Method for scrubbing and correcting DRAM memory data with internal error-correcting code (ECC) bits contemporaneously during self-refresh state
US10049006B2 (en) 2015-12-08 2018-08-14 Nvidia Corporation Controller-based memory scrub for DRAMs with internal error-correcting code (ECC) bits contemporaneously during auto refresh or by using masked write commands
US9934841B1 (en) 2016-10-21 2018-04-03 Altera Corporation Systems and methods for refreshing data in memory circuits
CN113223603B (zh) * 2021-05-31 2022-12-06 西安紫光国芯半导体有限公司 存储器刷新控制方法、装置、控制电路及存储器件

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2247835C3 (de) * 1972-09-29 1978-10-05 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zum Regenerieren der Speicherinhalte von MOS-Speichern und MOS-Speicher zur Durchführung dieses Verfahrens
US4005405A (en) * 1975-05-07 1977-01-25 Data General Corporation Error detection and correction in data processing systems
DE2549392C3 (de) * 1975-11-04 1978-07-27 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Erhöhung der Zuverlässigkeit von integrierten Speicherbausteinen und zur Verbesserung der Ausbeute von nach außen hin fehlerfrei erscheinenden Speicherbausteinen bei ihrer Herstellung
JPS5381036A (en) * 1976-12-27 1978-07-18 Hitachi Ltd Error correction-detection system
US4183096A (en) * 1978-05-25 1980-01-08 Bell Telephone Laboratories, Incorporated Self checking dynamic memory system
US4216541A (en) * 1978-10-05 1980-08-05 Intel Magnetics Inc. Error repairing method and apparatus for bubble memories
US4251863A (en) * 1979-03-15 1981-02-17 Sperry Corporation Apparatus for correction of memory errors
US4255808A (en) * 1979-04-19 1981-03-10 Sperry Corporation Hard or soft cell failure differentiator
US4319356A (en) * 1979-12-19 1982-03-09 Ncr Corporation Self-correcting memory system

Also Published As

Publication number Publication date
AU544356B2 (en) 1985-05-23
CA1165451A (en) 1984-04-10
FR2481487A1 (fr) 1981-10-30
DE3115541C2 (cs) 1990-05-17
JPS56169300A (en) 1981-12-25
SE8102507L (sv) 1981-10-26
NL8102030A (nl) 1981-11-16
JPH0118459B2 (cs) 1989-04-05
AU6760081A (en) 1981-10-29
DE3115541A1 (de) 1982-03-25
FR2481487B1 (fr) 1987-06-12
US4380812A (en) 1983-04-19
GB2075730B (en) 1984-09-19
GB2075730A (en) 1981-11-18

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