SE445176B - IMPLANTABLE HEART STIMULATOR - Google Patents

Abstract

A multi-mode pacemaker includes a microprocessor 100 and a memory 102 programmable with a variety of processes for stimulating a heart and/or a sensing and transmitting to an external device conditions of the heart or pacemaker. The microprocessor controls a multiplexer 106 to input via a scaling amplifier and a/d converter 108 signals from atrial and ventricular leads 17, 19, the power source 126, a reed switch 23 operable by an external magnet, or redundant leads on lines 138d,e. The output comprises latch drivers 134 a-d with respective output select switches 130 a-d selectively operable to supply stimulation pulses to the leads or allow sensing. External apparatus 104 may transmit coded information to change the stored program or operation of the reed switch may select a different program starting address. Pulse width, rate and amplitude may be controlled in response to sensed heart activity or power source level and different pacing modes (demand, asynchronous, etc.) or multi-site pacing to disrupt arrhythmias may be selected automatically or externally. In an aid converter 308 (Figure 8), counter 400 counts up the output of VCO 402 controlled by unknown signal V(X) and then counts down to zero the output of VCO 402 then controlled by reference EREF and during such countdown a counter 412 counts clock pulses so that when counter 400 reaches zero the output of counter 412 depends on V(X) but not on the scale factor of VCO 402.

Description

A problem with such implantable pacemakers of the prior art type is that there was no way to temporarily increase or decrease the rate or other operating parameter by which these pacing pulses are generated without surgery. Yet another problem is the great difficulty in determining the remaining life of the battery, in detecting and correcting a faulty electrode, and in establishing an adequate safety margin in terms of R-wave sensitivity in an implanted type-type stimulator.

Some currently designed implantable cardiac stimulators have a rate-enhancing ability but do not sufficiently control the ability of the need function. Other devices are provided with a magnetic heavy-duty switch device, which can deactivate the demand amplifier in order to control the demand function, but lacks a rate-increasing ability.

Another improvement, which has occurred since Greatbatch first described the implantable cardiac stimulator, is means for allowing reprogramming of the stimulator after its implantation. U.S. Pat. No. 3,805,796 discloses circuits which allow the rate of the stimulator to be changed after its implantation without any intervention. The rate varies in response to the number of times a magnetically actuated heavy switch is closed. The device according to this patent operates by counting the number of times the heavy switch is closed and by storing that number in a binary counter. Each step in the counter is connected to either connect or bypass a resistor in a series-connected resistor chain, which forms part of the RC time constant, which controls the pacemaker's rate.

The idea of the latter patent has been improved by the device of U.S. Patent 4,066,086, which discloses a programmable pacemaker which responds to the supply of radio frequency pulse bundles while a magnetic field maintained in immediate connection with a magnetically actuated pacemaker pacemaker switch capsule , keeps the heavy switch 10 15 20 25 30 35 7906205-5 3 closed. In the circuit described in this patent specification, again only the rate is programmable in response to the number of applied RF pulse bundles. The use of radio frequency signals to program pacemakers was previously disclosed in U.S. Patent 3,933,005. The device of this patent could be programmed in both rate and pulse width. However, no stimulator has ever been described, which can be programmed with respect to more than two parameters or have selected features or samples programmed according to instructions. Such a stimulator could be called a universally programmable stimulator.

One area where cardiac pacing technology has lagged behind the general state of electronics technology involves the use of digital electrical circuits. One reason for this has been the high energy required to. operate digital circuits. Recent technological advances in CMI devices manufactured on LSI circuits, however, together with improvements in pacemaker batteries, mean that digital electronic circuits are beginning to be used in commercial stimulators. The natural advantages of digital circuits are their accuracy and reliability.

The digital circuit is typically operated in response to a crystal oscillator, which provides a very stable frequency over extended periods of time. In the prior art, there have been proposals to utilize digital technology in cardiac stimulators since at least 1966. For example, reference is made to an article by Leo F. Walsh and Emil Moore entitled "Digital Timing Unit for Programming Biological Simulators" in The American Journal of Medical Electronics, First Quarter, 1977, pp. 29-34. The first patent to propose digital technology is U.S. Patent 3,557,796. This patent discloses an oscillator, which operates a binary counter.

When the counter reaches a certain count, a signal is emitted which produces the output of a pacemaker pulse.

At the same time, the counter is reset and starts counting the oscillator pulses again. The said patent also discloses the digital variant of the type of need, whereby the counter is reset upon sensing a natural heartbeat, and »-.__. -.-.-.-- - -» 10 15 20 25 _30 35 7906205- The digital variant of the insensitivity period, in which the output signal is prevented for a certain time after the delivery of a cardiac pacing pulse or the sensing of a natural heartbeat.

As mentioned above, digital programming techniques are disclosed in both U.S. Pat. No. 3,805,796 and U.S. Pat. No. 3,833,005. In addition, U.S. Pat. No. 3,833,005 discloses digital control circuits for controlling the pacing pulse rate or rate by setting up a reset counter for continuous counting up to a certain value, which is compared against a value programmed in a storage register.

This patent also shows measures for adjusting the width of the pulse by switching the resistance in the RC circuit, which controls the pulse width.

Other patents that disclose cardiac pacing useful digital techniques include U.S. Patents 3,631,860, 3,857,399, 3,865,119, 3,870,050, 4,038,991, 4,043,347, 4,049,003 and 4,049,004.

Although it has been suggested in these that a variety of parameters, i.e. pulse width and pulse rate, can be changed in an internally implanted radiator, a device capable of operating in a variety of stimulation and / or sensing modes is a desire. The systems according to the prior art are capable of storing a programmable word by means of digital calculator circuits, which characterizes a desired rate or pulse width. In an internally implanted device, in fact, the space is limited for including a plurality of such counters, by means of which a number of such functions could be programmed. Furthermore, available energy for operating such calculators must be taken into account, as well as the service life of the stimulator's internal power source as a result of the applied power requirement. It is well known in the art that the complexity of the circuit included in an internally implanted device is limited by many factors, including the current withdrawal from the battery and thus the life expectancy of a battery, before surgery is required to replace the device's current source, such as a battery. . An object of the present invention is therefore to increase the flexibility and adaptability of an internally implanted device, so that a plurality of procedures, including tissue stimulation and remote measurement, can be performed.

A more particular object of the present invention is to provide a customizable, multi-purpose implantable stimulator capable of being programmed before or after implantation to perform a particular stimulation procedure (or remote measurement procedure) depending on the patient's present condition.

The stimulator according to the invention is based on a programmable microprocessor in combination with a multiplexer system. In this way, several different modes of stimulation can be realized by means of only one device. For example, V00 stimulation, VVI stimulation, VAT stimulation and VDD stimulation can be achieved. The known devices are intended to work according to a single stimulation method, which also applies to the device described in DE 2 738 871. This paper illustrates the use of a microprocessor to produce a V00 stimulator.

However, this stimulator does not have the sense amplifier structures which are found in the device according to the invention and which enable demand stimulation in the VVI and VDD working methods. In this known stimulator there is also no multiplexer system for switching the line configuration. In addition, there is also no analog-to-digital converter. The new and characteristic feature of the invention is thus the utilization of the fact that the microprocessor in combination with a multiplexer system can provide several different modes of stimulation in order to adapt the device to any changed condition of the patient.

An implantable cardiac stimulator, which is arranged to provide a therapeutic stimulation of the chamber of a patient's heart via a conduction system and which comprises an atrial connection for connection to the conduction system and a ventricular connection for connection to the conduction system, is characterized according to the invention 10 15 20 25 30 35 IPR the end of the delay period, 7906205-5 6 of an atrial sensing amplifier connected to the atrial connection, which is arranged to generate a atrial sensing signal in response to a detected depolarization of the atrial tissue, a ventricular sensing amplifier connected to the ventricular connector which is an amplifier in the ventricular tissue generating a ventricular sensing signal, a ventricular pacing coupled to the ventricular connection, which is arranged to respond in response to a ventricular, a microprocessor means, a trigger signal, a stimulation pulse, system, which is connected to a multiplexer means and coupled to the ventricular pacing means, the ventricular sense amplifier and the atrial sensing amplifier generating a first set of control signals during a first PR delay period, a second set of control signals during a second atrial insensitivity period and a third set of control signals during an atrial sensing period. an atrial sensing signal occurs during the atrial sensing period, and generates a ventricular trigger signal unless a ventricular sensing signal is generated during said PR delay period.

This pacemaker preferably has memory means comprising at least first and second storage portions, each of which stores a particular process for stimulating the patient's heart, the microprocessor system selectively performing one of the programs stored in the memory means and including address means for addressing the stored program. in a selected storage portion in the memory means.

In this case, the cardiac stimulator suitably has reset means which are connected to the microprocessor. "generating a reset signal for resetting the address means to a predetermined return address, wherein the address means inadvertently addresses an execution of a sentence microprocessor through, loose location in the memory means, of a selected program in the memory will continue addressing the predetermined return address in the 10 15 20 25 30 35 7906205-5 7 The microprocessor may include means connected to the reset means for periodic generation and supplying a repeal instruction signal to the reset means for canceling the work of the reset means, if the address means operate correctly.At least some of the input signals. Furthermore, analog-to-digital conversion means may be present and connected to an output of the multiplexer means for receiving and converting the selected analog input signals into a corresponding digital signal for supply to the microprocessor system.

Suitably, scaling means are also provided for selectively varying the gain applied to the selected input signal, so that the signals supplied to the microprocessor system have substantially the same amplitude.

According to a second aspect of the invention, there is provided an implantable stimulator which is arranged to provide a therapeutic stimulation of a patient's heart via a conduction system and which comprises atrial and ventricular connecting means for connection to the conduction system, of atrial and ventricular sensing amplifiers coupled to the connecting means. are arranged to provide atrial sensing signals and ventricular sensing signals and which have transmission means which are arranged to render the sensing amplifier insensitive to electrical signals on the connecting means, a ventricular pacing means which is coupled to the ventricular connecting means for responsive response to a ventricular response and , which is connected to a multiplexer means and which can issue a series of instructions defining an escape interval, and generate a "chamber trigger signal at the end of the rescue interval at from the presence of atrial and ventricular sensing signals, the system further comprising locking means connected to the transmitting means and arranged to store a set of control signals which can render the atrial and ventricular sensing amplifiers insensitive to electrical activity on the connections below the chamber trigger signal.

The invention will be described in more detail in the following with reference to the accompanying drawings. Fig. 1 is a view showing the manner in which the programmable stimulator according to the invention is implanted in a patient, and how signals are transmitted to and from the stimulator for changing or adapting the program realized by the stimulator and presentation on an external monitor of signals, respectively. indicating the activity of the heart (or other tissue).

Fig. 2 is a functional block diagram of the internally implanted stimulator, as generally shown in Fig. 1. Fig. 3A is a circuit diagram of specific interconnections from the stimulator in Fig. 2 to the patient's heart for realizing ventricular stimulation and sensing according to the type of need. Fig. 3B is a circuit diagram showing interconnections from the stimulator of Fig. 2 to the patient's heart for realizing a sequential stimulation of the patient's atrium and ventricles.

Fig. 3C is a circuit diagram of interconnections from the stimulator of Fig. 2 to the patient's atrium and ventricle for realizing a synchronous, ventricular atrial pacing (ASVIP). Fig. 4A is a timing chart of the activation of the switches and elements in the circuit of Fig. 3A for realizing a chamber stimulation of the demand type.

Fig. 4B is a timing chart of the activation of the switches and elements of Fig. 3B for realizing a bifocal stimulation method. Fig. 4C is a timing chart of the activation of the switches and elements of Fig. 3C for realizing an ASVIP mode of operation. Fig. 5 is a flow chart of one of a plurality of programs to be stored in the memory of the stimulator shown in Fig. 2, for realizing a chamber stimulation of the type of need in accordance with the timing diagram in Fig. 4A.

Fig. 6, is a functional block diagram of a further embodiment of the stimulator according to the invention. Figs. 7A and B are detailed circuit diagrams of two particular, illustrative embodiments of the stimulator generally shown in Fig. 6. Fig. 8 is a functional block diagram of the analog-to-digital converter included in the stimulator of Figs. 6 and 7. Fig. 9 is a graph illustrating the operation of the reversible counter shown in Fig. 8. .

Fig. 10 is a more detailed circuit diagram of the analog-to-digital converter shown in Fig. 8. In the drawings, and in particular in Fig. 1, to which reference is now made, a stimulator according to the present invention is shown arranged to be programmed in a variety of ways so that the patient's heart, including its atrium 40 and its chamber 42, can be stimulated in a variety of ways. various means, as well as sensing the electrical activity in the patient's atrium and ventricles (or other body tissue) to either modify the stimulator's stimulation parameters or to transfer to a site separate from the patient's body.

More specifically, the stimulator 12 comprises a housing 13 which is resistant to body tissue and fluid, a first lead 17 which is connected to and attached by means of an electrode to the atrium 40 of the heart, and a second lead 19 which is connected to and by a electrode attached to the patient's chamber 42. Furthermore, an external transmitter 10 is shown, which by means of a wire 15 is connected to a coil or antenna 16, located outside the patient's body 14, for transmitting radio frequency coupled signals to the internally implanted stimulator 12. Furthermore, a monitoring device is shown 63, which is connected to the transmitter 10 by means of a line 59. As will be explained in detail, the transmitter 10 can be influenced to send signals via the line 15 and the coil 16 to the internally implanted stimulator 12, whereby its mode of operation can be changed from one selected mode of operation to another. , so that the physician can control the type of stimulation of the patient's heart in accordance with the patient's change e state. It is clear that at the time of surgical implantation of the stimulator 12 in the patient's body 14 a particular mode of stimulation may be desirable. After the implantation, the patient's condition can change, whereby a different working method may be desirable.

It is further desirable that a variety of signals be transmitted from the patient's body, which signals indicate different states to be sensed and transmitted by the coil 16 and the transmitter 10 to be presented on the monitoring apparatus 63. As shown in Fig. 1, the internally implanted stimulator 12 may further comprise an additional output and lead 25, which is connected to a sensor 27, which may be of a mechanical type for sensing movement of a body organ.

The stimulator 12 may further have an additional output and lead 21 connected to a magnetically actuable heavy switch 23, which may be actuated by the physician by applying an external magnetic field thereto to close the switch 23 and effect a change in the operation of the stimulator 12. A lead 29 illustrates a plurality of leads, which may be connected to different locations in the patient's heart to provide, for example, stimulation, which could defeat an arrhythmia, or form redundant leads to replace a faulty lead 17 or 19.

According to the functional block diagram of Fig. 2, the stimulator 12 comprises as its central control element a microprocessor 100 and a multiplexer 106 for receiving analog data from a first input 38a, which is connected via the first line 19 (see Fig. 1) to the patient's chamber 42. ooh a second input l38b, which is connected via the second line 17 to the patient's atrium 40 (see Fig. 1).

These various analog (and digital) inputs are selected by the multiplexer 106 under the control of the microprocessor 100 in a selected manner and the input signals are processed in accordance with processes or programs stored in a memory 102.

The microprocessor 100 is further connected by means of an address bus 112 to the memory 102, whereby addresses addressed by an address counter 107 are supplied for addressing selected locations in the memory 102. The addressed data is transmitted from the memory 102 via a data bus 110 to the microprocessor 100. In addition, there are additional inputs 138c, d, e and f to the multiplexer 106. The microprocessor 100 outputs control signals via an input selector bus 120 to the multiplexer 106, so that one of the inputs 38a-f is selected for supply to the microprocessor 100 via _.:.._.._.-_-__....__...__.._.__- »~ 10 15 20 25 30 35 7906205-5 11 a line 118, a scaling amplifier and analog- digital converter 108 and a bus 114. As indicated in Fig. 2, the output voltage VS of a power source 126 is connected via input 138c to the multiplexer 106 for appropriate modification of the behavior of the stimulator as a function of variations in the power source. For example, it is desirable that the pacing pulse width be increased with decreasing supply voltage to create a pulse of more constant energy or to decrease the pacing rate with decreasing supply voltage to indicate a need to replace the stimulator or modify it via external programming. The spare inputs 38d and 38e may, for example, also be connected to the chamber 42 and the atrium 40 for redundant sensing of the activity in these parts of the heart. The intention is that the microprocessor could choose which of the inputs 138a, b, d and e provides the most efficient sense of the atrial and ventricular signals or requires the least power from the current source 136 or most effectively interrupts a heart rhythm. The input 138 f may further be connected by the line 21 to the heavy switch 23, so that the physician may apply an external magnet to close the switch 23, so that the microprocessor 100 is controlled to change or change the program stored in the memory 102. The multiplexer sequentially selects or controls one of the inputs 13a-f via line 118, which is input to the microprocessor 100 via an amplifier and analog-to-digital converter 108 and the conductor 114. Multiplexing was used to reduce the hardware required to process the analog information supplied to inputs 13a-f and also to reduce the power requirements for this function. Without the multiplexer 106, each of the inputs 38a-f would need its own individual scaling amplifier and analog-to-digital converter 108. Thus, the use of the multiplexer 106 reduces the current output from the power source 106 and also reduces the circuits that must be included in stimulator 12.

Via a line 116, the microprocessor 100 supplies a scaling control signal to the scaling amplifier and the analog-to-digital converter 108, so that the scaling factor or gain of the amplifier in the block 108 is controlled to accommodate the different amplitudes of signals which are applied to the multiplexers 106. inputs l38a-f. In this context, it is clear that the power source 126 for illustrative purposes could be of the order of 1.3 - 6 V (from the beginning), while the cardiac activity signals derived from the atrium 40 and the chamber 42 could be of magnitude. the scheme l - 20 mV. The output of the amplifier and analog-to-digital converter 108 is a set of digital signals which are to be stored in the microprocessor 100 and in particular in the register of the microprocessor 100. In a preferred embodiment of the present invention, the microprocessor 100 could also be realized with currently available CMOS low level technology, which realization would provide a relatively low power consumption from the power source 126.

An essential element of the stimulator 12 is the memory 102, which may comprise a non-volatile section, i.e. a read memory part 102a (ROM), and a volatile part, i.e. a direct access memory part 102B (RAM). In the read-only memory part l02a, the basic steps in each of the different types of stimulation methods (or other processes) are stored. On the other hand, a variety of parameters or entire programs are stored in the direct access memory portion 102b and can be reprogrammed at a later time depending on the patient's changing condition. The memory 102 may be programmed at the time of manufacture, prior to implantation in the patient's body 14 or via an external memory input interface 104, which is connected to the name '102 by means of a radio frequency or acoustic link. In an illustrative embodiment of the present invention, a such a link as that described in U.S. Pat. Nos. 3,833,005 and 4,066,086 is easily adapted for use as the interface 104. In particular, those patents disclose a receiver filter for sensing the beams of radio frequency pulses transmitted from an external transmitter, the beams being coded in a manner for reprogramming a program stored in the memory 102 or alternatively for changing a parameter stored in a memory location in the memory 102.

Thus, after the stimulator 12 has been implanted in the patient's body 14, the physician may, upon observing a change in the patient's condition, reprogram the program or special variables in a program stored in the direct memory portion 102b to most appropriately stimulate the patient's heart for his changed conditions. In particular, it is pointed out that there are a variety of stimulation parameters, such as the pulse width of the stimulation pulse, the rate, rate or frequency of pulse supply, the period between the supply of a pulsation signal and the detection of the corresponding cardiac activity, during which the sensing device is canceled. Each of these parameters is typically determined by, for example, a word of eight bits, which is stored in a word location in the direct access memory 102b in the memory 102. If one wishes to change the pulse width, the physician can thus easily enter a new word via the interface 104 and the line 105. of eight bits, which word indicates the new pulse width with which the stimulator 12 is to stimulate to a known addressable word location in the direct access memory part 102b. The intention is that a new stimulation method can also be programmed into the direct access memory part 102b by introducing the steps of the new process via the interface 104.

Alternatively, a change in mode of operation may be effected by inserting the start location of the desired program from the direct access memory portion 102b into the address counter 107 of the microprocessor 100 to trigger the addressing of the next program in the read memory portion of the memory 102. For example, if the initial mode of operation of the stimulator 12 is ventricular pacing of the need type and it becomes desirable to read a sequential atrial ventricular pacing, the physician enters the new start address of this mode via the interface 104 to access another portion of the read memory portion 102a, the microprocessor in the next mode of operation. As explained in detail later, it is desirable that the energy in each patient's heart applied pulse be kept constant even though the voltage level from the power source 126, such as a battery, decreases with life. As shown in Fig. 2, the multiplexer 106 periodically supplies the battery voltage VS via the input 383c to the microprocessor 100, which under the control of a program stored in the memory 102 compares the measured voltage with different, predetermined voltages stored in the read-only memory part 102a or the direct access memory part. 102b, wherein an adjustment of the pulse width of the stimulation pulse is made to keep the energy content of the stimulation pulse, i.e. the surface under the curve, substantially constant.

It is further contemplated that the memory 102 may be loaded with a program which is in fact self-selecting. In other words, such a program would respond to heart signals, such as applied to inputs 138a and b, to sense the state of the heart, and select one of a plurality of programs depending on the sensed state.

The distinguishing characteristics of the atrial P-wave signal and the chamber R-wave signal are more fully described in the publication "Electrocardial Electrograms and Pacemaker Sensing" by P. Hoezler, V. de Caprio and S. Furman in [Medical Instrumentation, Volume 10, No. 4, July, August 1976. In this regard, the criteria by which these cardiac signals are to be recognized and compared are stored in memory 102, and if a change is detected, the microprocessor can automatically select another stimulation method, which is suitable for the altered states of the patient's heart, without the need for an external physician to intervene via the external memory interface 104.

In another stimulation method, the intention is that the memory 102 of the stimulator 12 can be programmed to operate as a stimulator with automatic threshold tracking, whereby the energy in the stimulation pulses applied to the patient's chamber 42 (or atrium 40) can be reduced incrementally until the capture is lost, ie. the stimulation pulses fail to induce a corresponding ventricular contraction, revealed by an R-wave sensed within a sensing period. If in this mode the R-wave is detected within the period, a control signal is developed to reduce the pulse energy level by a given, incremental amount.

In particular, the pulse width is reduced until no R-wave induced by the stimulator is sensed, the program increasing the pulse width until the R-wave reappears.

In this way, the current withdrawal from the current source 126 is minimized by adjusting the pulse width to a level which is just sufficient to maintain capture of the patient's heart. Further (Fig. 2), the control output signals of the microprocessor are supplied via lines, commonly designated by the reference numeral 131, to latch drivers 134 and by a bus 132 to corresponding selector switches 130, which emit appropriate stimulator pulses via lines 17 and 19 (or 29) to the atrium 40 and the chamber. 42 in the patient's heart in accordance with the processes stored in memory 102. More specifically, a line 13a is connected to a first driver or chamber driver (or amplifier) 134a, which in turn is connected to its own group of bipolar / unipolar selector switches 130a.

It is clear that each of the driver amplifiers 134b, c and d also has an associated group of selector switches.

The output of the driver 134b is connected, for example, to selector switches 130b for driving the patient's atria via lines 17a, 17b and 17c. It is also clear that the drives 134a-134d may include voltage raising circuits, for example doubles, more triplicate, to increase the voltage level to what is necessary for effective stimulation of the cardiac tissue with a given current source voltage. The selector switches 130 are controlled by signals produced from the microprocessor via the bus 132, for selectively coupling the output of the first driver 134 to a selected one of the outputs 19a, 19b and 19c. It is clear in this connection that the switches 130 are connected via the chamber line 19, which may be in the form of a coaxial line, which is connected to a tip electrode via a conductor 19a and to a ring electrode 19c, as more fully shown and explained. ....-__- «_....-_-_- ~ _....- V -V, 7906205-5 10 15 20 25 30 35 16 cleared in, for example, U.S. Patent 4,010,758. a conductor 19b is provided, which is connected to a plate formed by the metal container or capsule 13, in which the stimulator 12 is encapsulated. In normal, bipolar operation, the selector switches 130 connect the negative and positive stimulation pulses via the conductors 19a and 19c in the coaxial line to the tip and ring electrodes, respectively.

If stimulation in the usual unipolar manner is desired, a negative voltage is applied via the conductor 19a on the tip electrode and a positive voltage via the conductor 19b on the plate, the ring electrode not being connected.

In addition to being able to emit pulses in a bipolar or unipolar manner, it is desirable that the stimulator be rendered fault tolerant so that if a faulty lead is detected as a result of poor connection of an electrode lead to the heart tissue or rupture or damage to a lead the microprocessor 100 responds by leaving suitable control signals via the bus 132 to the selector switches 130, whereby another combination of leads (or conductors in the leads) is selectively connected for supplying the stimulation pulses to the chamber 42. As an example, the selector switches 130 may be arranged to connect the tip and ring electrodes 19a and 19c . Alternatively, the selector switches 130 are selectively closed to supply the heart pulse between the ring conductor 19c and either of the tip conductor 19a and the plate conductor 19b, so that in the event of a fault on one of the conductors 19a and 19d the other can be easily used in its place and still supply the pulse over the two locations in the patient's heart.

A fault on one of the lines 17 and 19 can be detected by loss of the capture, i.e. a lack of detection of a cardiac activity signal at the input 138b after the stimulation of the chamber. Alternatively, a high impedance measurement between conductors 19a and 19b in the coaxial line 19 indicates a fault on the line due to either scar tissue buildup between one of the tip and ring electrodes and the chamber 42 or due to rupture of one of the conductors 19.

Upon detecting such an error, the microprocessor 100 selects another process or program, stored in _ -.._____............__ - ..__. Memory 102, for supplying signals to one of the selector switches 130 and providing a switching of the conductors 19a (or 29) in a manner illustrated above.

An output from the microprocessor is also connected to a second amplifier or atrial pacing amplifier 13bb, the output of which is connected to a further set of selector switches 130, which are to be connected via a corresponding set of leads 17 to the patient's atrium 40, as shown in Fig. 1. Also included are backup amplifiers 134c and 134d, which receive outputs from the microprocessor 100 and are connected to additional sets of selector switches 130. The intention is that such sets of selector switches 130 may be connected to the patient's heart by redundant lines. For example, the outputs of amplifiers 1340 and 134d could also be redundantly connected to chamber 42 and atrium 40 in the patient's heart. If one of the wires 19 and 17 was broken or the resistance between its electrode and the patient's heart became excessive, a redundant wire could be connected between the microprocessor 100 and the patient's heart by appropriately activating the corresponding set of selector switches 130. For measuring the impedance, as shown by one of the lines 17 and 19, it is pointed out that this line is connected to an output circuit, which will be described in connection with Fig. 3 and comprises a charging capacitor, and that an indication of the charging time of the capacitor constitutes an indication of the of the associated line showed the impedance. During operation, the output capacitor is charged and after charging, the output circuit is actuated to cause a discharge of the capacitor, whereby a stimulation pulse is supplied via the associated line to the patient's heart. The intention is that the period required for charging the output capacitor is measured by starting a counter, provided by a program in the memory 102, the counting continuing until the charging voltage level on the output capacitor reaches a predetermined level. The voltage level of the capacitor will thus be measured repeatedly under the control of the microprocessor 100, and the counting operation will continue as long as the voltage level is not above the predetermined level. When the charging voltage of the capacitor has reached the predetermined level, the count ceases and the achieved count number is used as an indication of the impedance of the line. If the line is open, its impedance will be high and thus make the charging time period greater, while if the line is short-circuited the time period will be relatively short. First and second time limits are thus established for determining whether the line is short-circuited or if its impedance is too high, corresponding to a break in the line. In each case, these limits are checked, which are in the form of time counts, and if either limit is exceeded, a second redundant line replaces the faulty line.

The spare drivers 134 may be arranged to provide stimulation at a plurality of different locations, for example five pieces, to break an arrhythmia, which may be sensed by the stimulator 12. Alternatively, the additional drivers 134c and d may be used to discharge a polarizing voltage on the lines. 17 and 19 after stimulation or used to rapidly charge the output capacitor for stimulators operating at high pacing rates. Arrhythmias can be detected by measuring the delay between the electrical activity at a first site in the heart, for example in the atrium, and the detection of cardiac activity at a second site in the heart, for example the ventricle. If the delay is less than a predetermined period, eg 100 - 200 ms, this is an indication of a possible arrhythmia.

Arrhythmias are caused primarily by the appearance of a second, competing ectopic focus in a patient's heart, which focus competes with the primary focus that typically occurs in the patient's atrium. The two stroke centers compete with each other to cause arrhythmia, whereby the heart's activity becomes incorrect and the heart does not pump blood efficiently. In an illustrative form of the invention, it is intended that a plurality of electrodes, each connected to an amplifier 134 and a selector switch 130, be connected to a corresponding number of selected locations on the patient's heart. Such a line is selected to supply stimulation pulses to the patient's heart, the remaining lines being connected to sense the resulting cardiac activities at the other sites. Time slots are established by a program stored in memory 102 for each of the four leads, in which cardiac activity signals are to be received, and if the signals are not received within the time slots, this is an indication of a possible arrhythmia. If a detected signal is not within its slot, another of said plurality of lines is selected for supplying the pacing pulses and the remaining lines sense the resulting cardiac activity signals. If the sensed signals do not appear within the time slots after the selection of the new stimulation line, then another line is selected. If the arrhythmia is not brought under control by this measure, the program is designed to supply stimulation pulses to all leads to bring the activity of the heart under control. The time periods during which the cardiac activity signals are to be received are determined in a manner which is explained below with reference to Figs. 4 and 5.

It is clear from the above description that the stimulator 12 is an exceptionally flexible, adaptable device, which allows correction or compensation for a variety of factors, such as sensing difficulties, current source voltage variations with time and unforeseen sources of interference. Methods or programs are input, for example, into the memory 102 for sensing the R-waves based on such essential features as the slope of the ECG signal, the pulse width of the R-wave from the patient's chamber 42, the amplitude of the R-wave, the similarity of the R-wave to a previous ECG complex, etc. The memory l02 is also programmed to overlook from oncoming AC noise sources and to overlook or filter out irrelevant muscle signals. The advantages of such an adaptable stimulator 12 allow the creation of a single stimulator, which can be programmed for a variety of operations and can be reprogrammed continuously with the changes of technology. From a manufacturer's point of view, it is no longer necessary to modify each fixed circuit to develop separate hybrid circuits which differ from each other by minor features, for example a change of the input filter, the pulse width or the pulse rate.

A further advantage of the stimulator 12 in Fig. 2 is that it eliminates the use of a main source of error, i.e. the pulse rate and pulse width controlling capacitors in the stimulators realized by the prior art by fixed connections. At present, these stimulators utilize a resistor-capacitor charging scheme to provide the desired time functions, such as pulse width, pulse rate and insensitivity time. Experience suggests that capacitors can be a major source of failure in these circuits.

In this embodiment of the invention, the microprocessor 100 may be in the form of a processor manufactured by RCA Corporation under the designation "CDP 1802 7 COSMAC" microprocessor or "CDP 1804 COSMAC" microprocessor ("processing on-chip memory"). .

As explained above in connection with Fig. 2, each of the drivers 134 is connected to its own set of selector switches 130, so that a pacing pulse is supplied by one of the lines 17 and 19 to a corresponding part of the patient's heart. The multiplexer 106 further supplies a selected signal, generated by lines 19 and 17, from the chamber 42 and the atrium 40 to the microprocessor 100.

Fig. 3A shows an illustrative arrangement of the driver amplifiers 134 and the selector switches 130 for supplying the pacing pulses via the line 19 to the patient's chamber 42 for providing ventricular type pacing, the time intervals being shown in Fig. 4A. The reference numbers used to denote elements in Fig. 3A correspond to those shown in Fig. 2 for denoting similar elements or blocks. More specifically, a stimulator output circuit consists of an output transistor QV for selectively coupling the voltage of a capacitor CV to the chamber 42 via the line 19. More specifically, a control output signal T is connected from the microprocessor 100 via the conductor 13a. the amplifier learn and a resistor Rvz to the QV base of the transistor, making the transistor conductive. As a result, the previously charged capacitor CV is discharged to ground, whereby a stimulation pulse having a pulse width corresponding to that of the signal TWV is supplied via line 19 to the patient's chamber 42. The selector switch 130a is closed for a selected period by the supply via bus 132 the control signal TCV for recharging of the capacitor CV during the interval between successive control signals TWV. The control signal TWV thus selectively makes the transistor QV conductive and non-conductive, so that corresponding series of stimulation pulses are fed via the line 19 to the patient's chamber 42. In the case of unipolar stimulation, the plate or container 13 in the stimulator 19 is connected to the second connection of the battery.

As shown in Fig. 3A, the ventricular lead 19 is also connected via a conductor 38a to the multiplexer and in particular to a switch 106a ', which is closed in response to the time slot signal TS to supply a signal which characterizes the ventricular activity of the heart, via amplification and analog the digital conversion circuit 108 to the microprocessor 100.

More specifically, the chamber line 19 is connected via the conductor 13a, a capacitor C1, resistors R1 and R2 and an amplifier 139 to the multiplexer switch 106a '.

When comparing the functional block diagram in Fig. 2 and the circuits in Fig. 3A (as well as Figs. 3B and C), it should be pointed out that there is no exact correspondence between the elements in these figures. Although it is stated that certain switches, in particular switch 106a ', form part of the multiplexer 106, there is a difference in the circuits in that the circuit in Figs. 3A (and 3B and C) includes sense amplifiers, for example the chamber sense amplifier 139, while the multiplexer 106 in Fig. 2 supplies a selection of a plurality of analog inputs to a single amplifier 108. The intention is thus that the various switching functions, which for the purpose of illustration are shown in Fig. 3A (as well as Figs. 3B and C), are shown for the sake of clarity and could be realized. --F ---.- .. n. ..- of 10 15 20 25 30 35 7906205-5 22 in different ways, for example, the multiplex switch 106a 'could be realized by means of a selector switch 130. The connection point between the resistors R2 and R1 is connected to earth via a capacitor C2. As shown in Fig. 4A, it is desirable that the amplifier 139 be locked relative to ground during certain periods, i.e., the insensitivity period, with no sensing of the chamber signal being desirable. For this purpose, a time signal TCV is supplied via the conductor 120 to a selector switch 130c, whereby the connection point between the resistors R2 and R1 is connected to ground during the insensitivity period. The circuit formed by the resistors R1 and R2 and the capacitors C1 and C2 serves as a coupling circuit between the ventricular sense amplifier 139 and the patient's heart. When the multiplexer switch 106a 'is closed and connects the input of the ventricular sense amplifier 139 to ground, it is especially desirable that isolation be provided between ground and the patient's heart, as otherwise significant damage could be caused to the patient's heart. For this purpose, the resistor R1 and the capacitor C1 are inserted between ground and the patient's heart. Capacitor C2 also acts as a low-pass filter for noise, which may be present on line 19 as well as to soften the closure of selector switch 130c. It is contemplated that the chamber sensing amplifier may be in the form of a well-known operational amplifier and that the resistor R2 be connected to its input for setting its gain in a manner well known in the art.

Fig. 4A shows a timing chart for the ventricular-type ventricular pacing corresponding to the output-input connections of Fig. 3A, whereby the system of Fig. 2 is adapted to stimulate the patient's ventricle 42. At a time to, a ventricular pacing pulse has just been applied via line 19 to the patient's chamber 42. The RV amplifier 139 is then locked to ground by closing the selector switch 130c during the insensitivity period from to to tl. During the insensitivity period, the capacitor CV is also recharged by applying the control signal T for closing the switch CV 130a, whereby the potential Vs is applied and the charge LT is recharged! 10 15 20 25 35 7906205-5 23 capacitor CV. The insensitivity period is typically 325 ms at the time the stimulator 12 is implanted in the patient and the battery or power source 126 is new. During the insensitivity period, the cardiac activity in the chamber 42 is not sensed, since various kinds of noise or extraneous electrical signals may be present in the chamber 42, which one does not wish to detect. After the insensitivity period and beginning at time t1, the selector switch 1300 is opened and the switch 106a 'is closed, so that if the heart generates an R-wave signal which would be applied via line 19, the conductor 138a, the chamber amplifier 139 and the closed switch 1066', the microprocessor l00 responds by resetting the rate control period to to. The appearance of the R-wave signal from the chamber 42 indicates that the cardiac activity is normal and that it is not desirable for a competing ventricular pacing signal to be applied. Thus, as long as the patient's heart produces an R-wave signal, the stimulator 12 will not produce any ventricular pacing signal. However, if after the end of the sensing period from t1 to tz no R-wave has been sensed, the microprocessor 100 will generate a time signal Twv, which is applied via the conductor 11a, the amplifier 13a, the resistor RV2, to the base of the transistor QV, whereby the transistor QV is made conductive and causes rapid discharge of the capacitor CV through the cardiac load (represented by a resistor R3), whereby a stimulation pulse is applied via lines 19 and 13 to the chamber 42. During the stimulation period from t2 to t3, the chamber amplifier 139 is locked at ground through the closed switch 1300 From the above it is clear that the different periods, which correspond to the pulse width of the chamber pulse between the times t2_ and t3, and the insensitivity period between the times to and t1, can be adjusted or reprogrammed by entering new words of eight bits in the memory 102, shown in Figs. 2.

Fig. 5 shows a flow chart of the measures for realizing chamber stimulation of the demand type, the timing diagram of which is shown in Fig. 4A and the output and input circuit connections of which are shown in Fig. 3A to that of Fig. 2, ........_ ._....... ~ -_., ._., ..__..._- W_ I s ........., --_ l __ '.l._ .. _._.... ..._ _. 7906205-5 24 illustrated in an illustrative embodiment of the present invention, the microprocessor 100 includes a plurality of pointer registers for storing pointers or address locations in word memory portion 102b of memory 102. This illustrative embodiment includes the following registers for storing the specified pointers or pointers. the addresses in the microprocessor 100: R (0) = Program counter (PC) R (3) = Loop counter (LC) R (4) = Timer (TC) R (A) = Output state table pointer (QP) R (B) = Time length table pointer (TP) R (C) = Voltage transition point table pointer (VP) R (D) = Insensitivity timer (TR) R (E) = Input pointer (VDD) Flag signals for the heavy switch (EF2) and the R-wave (EF1) are further supplied to the microprocessor, as will be explained in conjunction with Figs. 7A and 7B. The designation for the flag signals and pointers as well as the counters was used throughout the program listing below. As is conventional with microprocessors, the microprocessor 100 includes the address counter 107, which steps forward one by one for each step in the program, as it is performed under the control of the microprocessor 100, to indicate the next location in memory 102 from which information is to be read. The steps, to be explained with reference to Fig. 5, for providing chamber stimulation of the demand type were realized in an "RCA COSMAC" microprocessor by following machine instructions: _ - -__.._ _. _........._....,, 7906205-5 25 Memory ~ Symbolic Memory Step address designation content Note. läoe (Hexadecimal) 1 (Hexadecimal) 00 0000 D = 00 200 01 LDI F8 202 02 00 00 202 03 PHI, 3 B3 202 04 PLO, 3 A31- Set LC = 0 202 05 GLO, 3 83 _ R (3) - > D 204 06 BNZ 3A Is LC = 00 204 07 'oUTPUT 3D No? Go to 204 Output state memory address 3D 08 LDI FB Yes? Set 206 Output state table at address A0 09 QP A0 R (A) = QP 206 OA PLO, A AA I 206 OB LDI F8 Set 206 OC TP A4 R (B) = TP 206 on PLo, Bl Aß_ 206 OE LDI F8 206 OF VP BO _ 206 10 PLO, C AC Set R (C) 206 = VP ll LDI F8 206 12 TR A3 206 13 PLO, D AD Set R (D) 206 '= TR 14 LDI P8 206 15 VDD B6 2062 16 PLO, E AE SetR (E) 206 _ = VDD - 17 SEX, E EE> Set X = E 208 18 INP 68 Read AD 208 ll (VDD) 19 sEx, A EA set xéA 210 7906205-5 1A lB lC lD lE ~ lF 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 35 _ I ¶ OUT 'INC B INC B LDA, C sEx, E sn BUF VPVDDCompare DEC B DEC B DEC C LDI 03 PLO, 3 STROBE AD LDA, D PLO, 4 DEC, 4 GLO, BNZ Test 2- DEC, 3 BR Check 0 (LC = 0) GLO, 3 XRI 02 BNZ DECTC 60 lB lB 4C EE F7 33 lB 2B 2B 2C F8 03 A3 4D A4 24 84 3A 32 23 30 05 83 FB 02 3A 2B 62K (l5) M (QPyä OUT 210 PQ + l TP + 2 214 214 M (R (C) -> D, 214 VP + 1 Ev X 212 VP ~ VDD 212 If DF = l 212 VP§ VDD Branching to 214 VPVDD Compare Decrease 212,2l¶ R (B) 2l2,214 by 2 Decrease _ 2l2,2l4 R (C) by 1,216 21 6 Set LC = 3 216 218 M (TR) -> D, 220 TR + 1 M (TRyaTC 220 TC - 1 238 Try TC = 0 224 Nratill sample 224 LC = 2 Yes, LC-1 232 232 232 R (3) * D 226 '226 Is LC = 2 226 226 LC = 2, 226 Branch 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 Address A0 Al A2 A3 A4 A5 A6 A7 A8 A9 A9 AA AB AC AD AE AF BNl DECTC B2 DECTC BR STRT ~ l SEX, A OUT LDA PLO, 4 BR DECTC Anm q QP TR TP. 27 7906205-5 3C Try R-wave 228 input 2B No R-wave 228 ing_branch 35 Try heavy 230 switch 2B Yes to 230 reduce TC 30 No heavy 230 switch 01 Branch to STRT-1 EA Set X = A, QP 234 60 M (QP) åOUT, 234 QP + l 4B 236 A4 M (TP) èTC, 236 TP + 1 30 Extension to 222 2B Decrease 222 TC Assembler Machine language code Q REF 01 Q PP 02 P PW 04 T REF FF SP 5.2 V 60 PW 5.2 V 03 SP 4.8 V 60 PW 4.8 V 06 SP 4.4 V 50 PW 4.4 V 08 SP 4 V 60 PW 4 V 10 SP 3.6 V 60 PW 3.6 V 12 SP 0 V 60 Pw 0 V 12 7906205-5 28 B0 VP 5.2 V 52 Bl 4,8 V 48 B2 '4,4 V 44 B32 4,0 v 40 B4 4 3,6 V _ 36 BS 0 0.0 V 00 B6 VDD SP F Sensing period PW = Pulse width Fig. 5 shows a flow chart of the measures, which represent the instructions set out above, the corresponding measure for its instructions being identified under the heading "Step position". The program begins in the start step 200, which proceeds to a step 202, where the loop counter LC, which is formed by the register R (3), is set to zero, as realized by the instruction stored at the memory address 04, as shown above. As shown in Fig. 4A, the demand type of chamber stimulation includes an insensitive state corresponding to the insensitive period during which the chamber amplifier 139 is locked, a sensing period state during which the electrical activity of the chambers is accessible and sensed, and a pulse width state, during which the ventricular pacing pulse is delivered to the patient's ventricle 42. As will be apparent from a further description of the steps or actions in the program, the program continues in a looping manner through the steps of Fig. 5 three times, i.e. once for each of the three states mentioned, the loop counter LC is reduced at the completion of each loop to indicate that the process has moved to the next state.

From the beginning, the loop counter LC is set to zero in step 204. The process is now moved to step 206, in which the above-defined pointers VP, QP, TP and TR are initialized to their starting points. As defined above, VP is, for example, the voltage transition table pointer. Thus, in step 206, the register R (C) is set to the first Jokatloncn in the transition point table, which indicates the voltages, with .....- ..._ e - v-àm-a -... Q -... í-m -... w- ..,. . ...- - .. mvw- »- 7906205-5 29 which the output voltage VS from the power source 126 is to be compared.

The pointer QP, which points to the initial state table, as stored in register R (A), points to the location in the initial state table which identifies which of the states shown in Fig. 4A the processor is in, i.e. either the insensitivity period, the sensing period or the pulse or pulse width period . The output state table is shown below as follows: Q11 01 Insensitivity state Q2l 02 Sensing state Q3l 04 Pulse width state Next, in step 208, the microprocessor 100 commands the analog-to-digital converter 108 to read out a digital indication of the voltage of the current source Vs. In step 210, the initial state QP, as stored in the microprocessor register R (A), is incremented by one, i.e. to move it to the next initial state. At this point, the register R (A) thus indicates that the process is in its first insensitivity period.

Next, in step 212, the voltage vs is compared with the transition point voltage (VP), as indicated by the voltage transition point table pointer VP, as stored in the register R (C). If the voltage Vs is greater than the voltage transition point, the process moves to step 216, while if not the process moves to step 214 in which the voltage transition point table pointer VP is incremented by one to point to the next location in the table to obtain the nearest lower value of the transition point voltage, and further the time length pointer TP is increased by two to mark the next two locations in the time length table.

The next value of the voltage transition point is obtained from the voltage transition point table, which is given below: .7906205-5 30 HEX.

V1 B3 179 = 5.2 V V2 A2 162 = 4.8 V V3 91 145 = 4.4 V V4 80 128 = 4.0 V V5 6E '110 = 3.6 V V6 00 = 0.0 V The next the set of values for the sensing time and p flfi æwmemähswt fifl à fl mæ fl mmv fl mnä given below: T2l 475 HIS? vs 2 5.2 .V Tal soo ps_ Tzz 475 msïš Vs z (ha v T32 1000 us.

.T23 475 msš vä 2 4.4 V T33 1250 us, T24 475 ms} Vš 2 4.0 V T34 1550 US.

Tzs eoo ms Vs Z 3.8 V T35 1850 us_ T26 600 mss vs 2 3.6 V T36 2300 us As can be seen from every other location, first a length is given for the sensing period and then the pulse width for a given voltage transition point, ie a reference value with which the voltage Vš must be compared. As will be explained, the program thus adjusts the pulse width of the ventricular pacing pulse to maintain constant energy in the ventricular pacing pulse as well as to increase the sensing period suddenly, as the voltage Vs of the current source 126 is attenuated, to provide a stepwise rate lowering behavior at the end of battery life. In step 214, the voltage transition point is moved from V1 to V2, for example from 5.2 V to 4.8 V. The value of VS is again compared with the voltage transition point (VP) and if it is larger (yes ), the program proceeds to step 216, in which the LC value of the loop counter is entered with the value "three", which indicates that the oscillator is in the insensitivity period. The analog-to-digital converter 108 is then strobeed to read the current source voltage Vs. In step 220 the timer is read and stored TC (register R (4)), the value of the insensitivity period stored in the location TR.

Thereafter, the process proceeds to step 222, in which the value stored in the timer (TC) is reduced by one and the timing of a period is caused to start running through step 222 until the value stored in the timer (TC) has been counted down to zero. Next, in a step 224, a decision is made whether the TC value of the timer is equal to zero, ie if the counting function has been terminated, and if not, the process proceeds to a step 226, where a decision is made to determine if the loop counter LC is equal to two , which indicates whether the process is in the sensing state corresponding to the RV sensing period. If not, as is the case at the present point, the process passes through the loop formed by steps 222, 224 and 226 until the first count (corresponding to the insensitivity period), as set in the timer TC, has been reduced to zero through step 222, as detected by step 224, thereby terminating the insensitivity period. At that point, step 224 moves the process to a step 232, where the loop counter LC is reduced by one to thereby indicate that the process is in the sensing state, i.e. LC is equal to two, so that the process returns to step 204. At this point, the loop counter LC is not equal to zero and the process is moved to step 234, where the output state table pointer QP is incremented by one, since the process is at this time moved to the sensing state. Next, in a step 236, the value obtained from the time table is placed in the timer TC and the time table pointer (TP) is incremented by one to address the nearest wider pulse width in the time table. The process then moves via step 222 to abruptly reduce the count entered in the timer TC, and if thereafter this count is not zero, as determined by step 224, the program steps up to step 226. If the process, as in this case , is in the sensing state, it is the decision step 228 for determining whether an R-wave has been applied to the multiplexer 106. If within the time period of a single reduction count the R-wave is not sensed, the process goes back for a new cycle, whereby the count is reduced in step 222 corresponding to the sensing period until the count is equal to zero, as detected by step 224. If an R-wave is detected by step 228, the process proceeds to a step 230 for checking the state of the heavy switch 23 . If this is open, the process is reset, as shown in Fig. 4A, to return the process to two, i.e. to step 202, where the loop counter LC is reset to zero and the process or process is restarted. The heavy switch 23 is a magnetically actuable switch inside the stimulator 12.

After implantation, the physician can actuate the tongue switch 23 by placing an external magnetic field near the implanted stimulator 12, closing the tongue switch 23 to trigger the asynchronous operation. If the heavy switch 23 is closed, indicating a desire to work in the asynchronous manner, the process continues to loop and return to step 222 to again reduce the time count TC, even if an R-wave has been detected. In this way, the detection of an R-wave is ignored and the stimulator 12 continues to stimulate in the asynchronous mode of operation without reset upon detection of the R-wave.

After the second sensing period has elapsed, i.e. when the count stored in the timer TC has been counted down to zero, as indicated by step 224, the process is transferred back to step 232, where the loop counter 'LC is reduced by one, whereby in that counter stored value 10 15 20 25 30 35 7906205-5 33 is equal to one, indicating that the process enters its third loop and returns to step 204. Since the loop counter LC is not equal to zero, the process proceeds to step 234, whereby the output state value QP increased by one, which indicates that the process is now in the pulse width state. Next, in step 236, the duration value is addressed and access is provided from the duration table and the said value is stored in the timer TC. The value of the time length table pointer TP is increased by one to point to the next location in the time length table, as indicated above.

At this point the process enters a series of cycles, through which the count in the timer TC is reduced by one of the steps 222, and if the count is not zero, a transition is made to the step 226 and, since it is not the sensing period, returns for renewed reduction in step 222. The process is repeated until the value of the count in the timer TC has been reduced to zero, as determined by step 224.

At this time, the process moves back to step 232, where the loop counter LC is again reduced by one, the value now being zero. The process proceeds to step 204 and begins all over again with the triggering of the values of VP, QP, TP and TR through step 206.

In the above, the manner in which the stimulator 12 implements the chamber stimulation program of the need type, as stored in the memory 102, is described, a shift taking place first to the insensitivity period, then to the sensing period and finally to the stimulation or pulse width period, before a new cycle start again. As stated above, the length of each of the insensitive period and the pulse width period is determined by the voltage Vs of the current source 226, said periods and especially the pulse width period increasing with decreasing voltage Vs to keep the energy content of the ventricular pacing pulse substantially constant.

As explained above, the memory 102 can be programmed by any of a variety of modes to stimulate the patient's heart, which are selectable depending on the patient's condition, including a postoperative change. of the pacemaker 12.

For example, as shown in Fig. 4B, the stimulator 12 may be operated in a sequential rate control manner, with pacing pulses applied to both the patient's chamber 42 and the atrium 40. After corresponding insensitive periods, the activity of the chamber is sensed and the stimulator is reset if a chamber signal does not occur after either stimulation. of the chamber or atrium. The output and input connections of the stimulator shown in Fig. 2 are selected in the manner shown in Fig. 3B. With respect to Figs. 3B and 4B, the patient's chamber 42 is pulsed immediately before time t0 by applying a stimulus signal via line 19. After time t0, the chamber sensing amplifier 139 is locked by supplying the signal TCl to the selector switch 130c, thereby connecting the amplifier 139's input to ground. during 7 a first insensitivity period from to to tl. During the first insensitivity period, the chamber output capacitor CV is recharged by supplying the control signal TCV to the selector switch 130a, whereby the current source voltage Vš is applied to charge the capacitor CV. During the period t1 - t2, a control or clock control signal Tal, as derived from the microprocessor 100, is applied to close the switch 106a ', whereby any existing chamber R wave via the chamber amplifier 139 and the multiplexer 106 is applied to reset the clock control operations 100 of the microprocessor 100.

If at time tz no R-wave from the chamber has been sensed, the stimulator 12 provides a supply of a stimulation pulse via line 17 to the patient's atrium 40.

More specifically, a pulse control signal TWA is supplied via the driver amplifier 13b and a resistor RA2 to the base of the pre-output terminal transistor QA, thereby making this transistor QA conductive and causing a discharge of the atrial output capacitor in the patient's atrium 40, thereby stimulating it. Starting at time t2, the rate control control signal is supplied to the selector switch 130c, locking the input of the chamber amplifier 13a to ground, thereby ignoring any signal in response to the stimulation of the atrium 7906205-5. Starting at a time t3, the atrial output capacitor CA is recharged by applying the rate control signal T to close the selector switch 130b and apply the source voltage Vš to the capacitor CA. During the period from t4 to ts, the activity of the chamber is sensed again and a clock control signal from the microprocessor 100 is applied to close the switch 106a ', which allows the chamber R-wave to be supplied via the unlocked chamber amplifier 139 and the closed switch 106a'. to the microprocessor 100. If the R-wave from the chamber is sensed during this second sensing period from t4 to t5, the rate control period is reset to to.

If no R ~ wave occurs during the period from t4 to ts, a rate control pulse VWV is supplied from the microprocessor 100 via the chamber driver 134a and the resistor RV2 to make the chamber output transistor QV conductive, whereby the charged capacitor CV is connected to ground, discharged and supplied via line 19. a pacing pulse to the patient's chamber 42. Typical values for the periods TA, ranging from t0 to t2 and for the period TV from t0 to t5 are given below: TV (ms) TA (ms) zooo 0 1100 iooo vso sso voo aso sso vso soo 750 soo 650 aoo ssø 425 The sequential mode of operation shown in Fig. 4 may, for illustrative purposes, be programmed in a manner similar to that shown in Fig. 5 except that six initial states and corresponding time periods, as shown in Fig. 4B, are set by counter values, such as generated 10 '15 20 25 30 35 -.- _ .. 7 -... -_ .. - -. -from a corresponding table stored in memory 102 7906205-5 36. Thus, from the beginning, typical values of TV and TA for a particular patient are programmed by establishing access to specific locations in the corresponding tables, one for each of the six periods. After the count has been entered in the timer, successive cycles are performed until the count is counted down to zero for the end of that period.

Fig. 4C illustrates the timing of an atrial synchronized, ventricular-inhibited stimulator (ASVIP), sensing both the activity of the ventricle and the atrium in the patient's heart to reset the pacing period.

Such an approach is typically used in a younger patient, whose atrium beats normally but whose ventricles may or need not be defective. It is desirable that the stroke frequency of the atria be increased and that the ventricular activity is thereby stimulated. A sensed P-wave from the atrium triggers a pacing cycle, but if there is a fault in the conduction of this signal to the patient's chamber, a stimulation signal will in any case be applied to the patient's chamber 42. It is desirable that the rate of the striking atria be utilized. for synchronization of the ventricular pacing, which may be impaired due to a myocardial infarction or other defect in the cardiac conduction system.

As shown in Fig. 4C, the cycle begins at time two with the sensing of the atrium P-wave. As shown in Fig. 4C, a single cycle or period is divided into six clock control periods (and states). During the first clock control period from to to t1 (as well as the second and third clock control periods up to time t4), the maximum amplifier 141 to ground by supplying a clock control signal for closing the switch 130d. During the first period, the unlocked chamber sensing amplifier 139 also supplies each Rrwave signal applied from the chamber 42 via line 19 to a switch 106a ', which is closed by an Rv control signal. If an R-wave signal is sensed during the first period from to to tl, the rate control signal is reset to to. During the second period or the pulsation period from t1 to tz, the atrial amplifier 141 remains locked to ground, since the switch l30d is closed, and a beat control pulse TWV is previously supplied via the driver amplifier 134a and the resistor RV2 base of the chamber output transistor QV, whereby the trans- 42.

During the second period (also extending into the period-charged chamber output capacitor CV discharged through the system QV via line 19 to the patient's chambers three and four at time t4), the chamber amplifier 139 is also locked to ground by a switch 130C, which is applied to a chamber lock signal. TCl, thereby disregarding the cardiac activity that would occur during the period after ventricular stimulation. During the fourth and fifth periods from t3 to t5, the atrial amplifier 141 is not locked, which allows the supply of the atrial P-way signal via a closed selector switch 106b 'to reset the beat control process to to. From t3 to ts, a sensing rate control signal RA is applied for closing the switch 106b '. During normal operation, it is the intention that a P-wave signal from the atrium can be sensed during the fourth and fifth beat control periods from t3 to ts, whereby the beat control cycle is reset to zero. However, if no P-wave is sensed, the chamber is again stimulated by the supply of a control pulse TWV to the base of the chamber output transistor Qv, whereby a pulse is fed via line 19 to the patient's chamber 42, as explained above.

The ASVIP method of stimulation may, for the sake of clarity, be programmed in a manner similar to that of Fig. 5 but with six periods or initial states defined in a similar manner and with each of the six rate control periods established by addressing or establishing pointers. to corresponding tables, whereby varying values of the periods were sent to a rate control counter, the count of which is to be reduced while the process is performed through each of six loops.

In Fig. 6, to which reference is now made, an alternative embodiment of the adaptable, programmable stimulator 10 according to the present invention is shown, wherein similar elements and circuits are identified by reference numerals, which are similar to those in Fig. 2. except that the percentage figure 3 has been used. The microprocessor or central unit (CPU) is, for example, identified by the reference number 300 and is connected to a multiplexer 306, a selection of input signals 338a, b, e and f being supplied in the form of a flag via a bus 318 to the microprocessor 300. Via an address bus 312, the microprocessor selectively addresses a memory 302, which for the sake of clarity has a plurality of sections 302-1 - 302-16. As shown in Fig. 6, the memory 302 may be in the form of a volatile memory, such as a direct access memory, or a programmable read only memory (PROM) or an erasable read only memory (EROM). The addressed data is read from the memory 302 and fed to a data bus 310, which connects the memory 302, the microprocessor 300, a decoder 342 and an analog-to-digital converter 308.

The analog-to-digital converter 308 converts the analog value of the V voltage to digital form for input to the microprocessor 300 via the data bus 310. It is clear that the other analog values, such as the P and R waves, are also converted to digital form and scaled prior to supply to the multiplexer. 306. The analog-to-digital converter and scaling circuit, which would be connected to the multiplexer 306, are similar to those described above and are not shown in Fig. 6. The microprocessor 300 supplies rate control signals via an Nsbus 352 to control the decoder to start decoding the signals occurring. on data buses 310.

The decoder 342 interprets the output signal from the microprocessor 300 to select one of a plurality of switches 1-16 within the block 330. In this regard, each such switch in the block 330 has its own latch circuit within the block 340, which circuit is set by the output signal from the decoder 342 and i. in turn is connected to an amplifier and an output drive circuit, as described above. In this way, the flexibility is ensured for providing a plurality of output circuits, which can be connected by means of wires to different parts of the patient's heart, as well as to ensure the ability to recharge the output drive circuits and enable access to data at various points either on the patient's heart or on other parts of the patient's body.

Thus, a remote measurement system is provided for transmitting data from or to the programmable stimulator, as shown in Fig. 6.

According to a further feature of the embodiment of Fig. 6, an auto-reset oscillating circuit 344 is arranged to reset an address counter 307 within the microprocessor 300. The address counter 307 counts for each processed step in order to address the next word location in the memory 302. It has been found , that such disturbances generated by a defibrillation pulse or other source could cause the address counter 307 to address a meaningless or erroneous location in the memory 302. As a result, the process or process would be "suspended" in a meaningless location. If the address were to be affected by interference or noise for addressing a meaningless location, the oscillator circuit 344 is reset on a regular basis, for example every 0.5 s, whereby the address of a start address in the program is executed. In the event that the address counter 307 is operating normally, an output signal is generated from the data bus 310 and fed through the line 346 to reset the circuit 344, thereby preventing its regular reset output signal.

According to a further feature of the present invention, the multiplexer 306 comprises a further group of inputs 339a-339d for receiving a binary start address, which is to be placed in the address counter 307, whereby each of said plurality of blocks 302-1-1302-16 can be selected and performed. The intention is thus that a plurality of cardiac pacing modes can be stored in the memory 302, each pacing mode and associated starting point stored in a separate block could be addressed by entering a binary number via the inputs 339a-339d and an external link 341, which has the shape of a radio frequency (or acoustic) link, as described above. 10 15 20 25 30 35 7906205-5 40 In addition, self-control routines or data acquisition routines may be stored in specified blocks among the blocks in memory 302. Fig. 3A gives an indication of the manner in which an exemplary self-control routine could be performed to test the further the operability of the chamber sensing amplifier 139. An additional selector switch 130g may be closed in response to a test signal Tt generated by such a self-check routine or program stored in the memory 102 for supplying a reference voltage Vref of the order of magnitude 1 m entrance. The amplified output signal is in turn supplied by the multiplexer 106 to the microprocessor 300, whereby the amplified voltage is compared with a reference value for determining whether the amplifier 139 is operable. If this is not the case, another output circuit and sense amplifier could be connected to replace the faulty sense amplifier. In yet another mode of operation, a program would be stored in one of the blocks in memory 302 to provide sensing and transmission of data, such as wired to the implanted stimulator. The wires could, for example, be connected to cardiac tissue, other tissue or sensors for sensing the patient's ECG, pulse rate, pulse width, depolarization time between atrium and ventricle, etc. The transmission time of the depolarization signal is considered to characterize the heart condition and a gap is established by a sensing program. transfer time. If the received signal is outside the limits of such a gap, an indication thereof is transmitted outside the stimulator. In a data collection method, the idea is that the latches associated with the leads to sites on the heart, tissue sites or sensors are connected one at a time by selective closing of the corresponding selector switch 330, whereby the data is transmitted by the external link 341 to an external monitoring device.

In addition, an input 338f, which is connected to the heavy switch 23 of the type closed by an external magnet, is included for changing the mode of operation of the stimulator shown in Fig. 7. The intention is that a sequence of signals can be generated by opening and closing the switch 23, whereby it becomes possible for the external link 341 to receive or send data from the respective to the stimulator 12 '. As an example, a new address is entered into the address counter 307 to address the start location of the next block in memory 302, thereby executing a new mode of operation.

Fig. 7A, to which reference is now made, shows a more detailed circuit diagram of the blocks in a first particular embodiment of the apparatus generally shown in Fig. 6. For illustrative purposes, the microprocessor 300 is specifically identified as the COSMAC microprocessor manufactured by Radio Corporation of America, which is described in the publication "USER MANUAL FOR THE CDP 1802 COSMAC MICROPROCESSOR (1976)". The multiplexer 306 has a series of sixteen inputs 0-15 and may be in the form of the RCA-manufactured CD0067 to provide an output to the analog-to-digital converter 308, an illustrative embodiment of which will be described later in connection with Figs. 8, 9. and 10.

The analog-to-digital converter 308 is in turn connected to the microprocessor 300 by means of the data bus 310 and is also connected to a latch 309, so that one of the sixteen inputs of the multiplexer 306 is selected for supplying analog data to the analog-to-digital converter 308.

The N-rate control bus 352 is shown as a bundle of conductors 352a-d and is connected to the decoder 342, which consists of a plurality of gates manufactured under the designation CD40122. The outputs of two of the gates are connected via lines 356 to a conversion instruction input, so that the analog-to-digital converter 308 receives data from the multiplexer 306, and to a three-state output, so that the analog-to-digital converter 308 is instructed to feed the digitally converted data to the data bus 310. Strobe outputs 1 and 2 are further produced from lines 354a and b and are supplied with latches 342a and 342b, respectively. ... u-am -..- l- 10 l5 20 25 30 35 7906205-5 42 whereby the data supplied to the data line 3010 can be selectively fed to one of a plurality of switches, which are housed in the blocks 330a and 330b, respectively. Blocks 330a and 330b each include four solid state selector switches for providing output signals to selected output drives. In the particular embodiment shown in Fig. 7A, the detected microwave signal is further fed to the input of the microprocessor 300 and the heavy switch input is applied to the input of the microprocessor 300. In this embodiment, the microprocessor 300 'acts as its own multiplexer for selective access to and influence of signals applied to these inputs, in the desired sequence. The microprocessor 300 leaves addresses via the address bus 312 to the memory 302, so that data can be read out and supplied to the data bus 310.

Fig. 7B shows a detailed circuit diagram of a second embodiment of the stimulator device, which is generally shown in Fig. 6. The elements in Fig. 7B have the same reference numerals as the elements in Fig. 6 except that the hundreds digit is 5. The input signals corresponding to R the wave, the P-wave and the heavy-duty switch output signal, are fed to the inputs Éïï, ÉFÜ and Éïï to the microprocessor 500, which for illustrative purposes may also have the form of the microprocessor CDP 1802 manufactured by RCA. In this embodiment, the microprocessor 500 performs multiplexing functions, whereby one of these values are processed at a time. Typically, these inputs have an analog form and require conversion to digital form by the circuits shown within the dashed lines and generally denoted by the reference numeral 508. The analog-to-digital converter includes a circuit manufactured by RCA under the designation CD4508 and receives inputs from operational amplifiers 511. which are applied to a reference signal established by means of zener diodes 513. A clock signal is applied via a flip-flop 509 and a field effect transistor 517 to an input of the converter 515. The system memory 502 is connected to the outputs of the microprocessor 500 and includes two of the RCAs under the designation.

CDP 18225 manufactured blocks. The microprocessor 500 outputs instruction signals via the N-bus 552 to a decoder 542, which is in the form of a chip manufactured by RCA under the designation CD 4514B. The decoder 542 performs decoding functions on the output 50 of the memory 502 under the control of rate signals supplied via the N-bus 552. The output signal of the decoder 542 is supplied to a pair of latches 540a and 540b, each of which is constituted by the RCA under the designation CD 4508. lâskretsen. The decoder 542 selects a latch, thereby closing a corresponding selector switch in the sets 530a and 530b. The sets of selector switches can be composed of such integrated circuits manufactured by RCA under the designation 4066AE.

In Fig. 8, to which reference will now be made, an illustrative embodiment of a low-power analog-to-digital converter 308 is shown, as included in the stimulator shown in Fig. 7. As shown in Fig. 8, an analog voltage V (x) to be converted to digital form is supplied by an input line 404 to a switch (S1) 407, which is connected in a position or first position for supplying the analog voltage V (x) to the input (VIN) of a voltage controlled oscillator (VCO) 402, the output of which is applied to the input of an accumulator counter 400. As indicated by the inputs of the counter 400, the accumulator counter 400 may count either "up" or "down" to via a gate 414 provide an output signal to an input of an "N" * output counter 412. A clock signal is applied via an input line 418 to a control logic 408 and in particular to an H dividing circuit 410, the output of which is connected to reverse the switch 407 to a second position or down position, a reference voltage being supplied via a conductor 406 to the input of the voltage controlled oscillator 402 at the same time as a down instruction signal is applied via a gate 418 to the down input to the accumulator counter 400, which then triggers a countdown. At the same time, an output signal is provided from the control logic 408 to the reset input of the counter 412.

The analog-to-digital converter 308 of Fig. 8 operates in the following manner. An unknown voltage VX is applied to the voltage controlled oscillator 402 via the switch 407 for a fixed period of time Tup. During this time period, the accumulator counter 400 counts upward based on the output of the oscillator 402. The accumulator counter 412 acts in much the same way as an analog integrator in that the count in the accumulator counter 400 is rebuilt linearly for a given voltage level at VX.

The time Tup depends on the clock frequency applied to the line 418 via the control logic 408 and the n-counter 410. At the end of the time Tu, the switch S1 is switched to its second position to switch the input of the oscillator 402 to the reference voltage Eref. Coincidentally, with this switching to the reference voltage, the "A" accumulator counter 400 is set in the downward counting mode. During this countdown, circuits are used, which check when the accumulator counter 400 has counted back to a predetermined count, eg zero. The time required to count the reference voltage back to zero is proportional to the average of the input voltage V. While the accumulator counter 400 is made to count back to zero, the clock frequency FCLK is counted by the "N" output counter 412. In the "N" counter 412 accumulated numbers have a digital form and are directly proportional to the original, unknown voltage VX. This results in a voltage-frequency conversion.

The basic equations for the operation of the analog-to-digital converter 308 are: A = K up VCO up A (2) down = KVCO.Eref TX Equations 1 and 2 give the counts up and down in the accumulator counter 400 as a function of the unknown voltage. the reference voltage and the length of time that this voltage is applied to the oscillator 402. The counter 400 counts up and count down are equal, since the counter 400 starts from zero and returns back to zero at the end of the cycle. By equating these equations, the scaling factor KVC0 of the voltage controlled oscillator can be eliminated from the effect on the result of the analog-to-digital conversion. Equation 3 below, which gives the output counter's accumulated count N (X) as a function of the clock frequency FCLK and the time required to force the accumulator counter back to zero, ie TX, is given as follows: N (x) = TX FCLK <3) Equation 4 below, which gives the time Tup for counting up as a function of the "n" counter and the clock frequency, are the following: T = n / F up CLK (4) Equation 5, which shows that the output counter's count N is proportional to n and the unknown voltage divided by the reference voltage, has the following appearance: N (x) = n V (x) A (5) 'Equation 5 shows that the digital output count N (x)' is independent of the clock frequency FCLK, the strobe frequency and, which is of particular interest, the scaling factor of the voltage-controlled oscillator. For example, if the unknown voltage VX was 2 V, the reference voltage was 2 V and the N-counter counted to 64, at the end of each conversion the output counter N would have a count 64. This special feature of the analog-to-digital converter allows the introduction of a gain in series with switch S1 and oscillator 402 without any significant effect on the output count, even if this gain would change or vary from unit to unit, provided that the gain was constant over a conversion cycle. In other words, since, as shown in Fig. 8, a single voltage controlled oscillator is used for supplying both the analog input voltage V (x) and the reference voltage EREF, the voltage controlled oscillator 407 scaling factor not the digital output of the counter 412.

Furthermore, since the same clock signal fCLK is used to clock the first counter or accumulator counter 400 during the countdown period TX as well as to clock the "N" output counter 412 during the same period, the frequency of the clock signal fCLK does not affect the digital output of the counter 412. analog input signals V (x). The clock used for supplying the clock signal fCLK thus does not have to be of the type with high precision and relatively high power consumption, but can be designed to impose a minimum current outlet on the power source, ie the stimulator's battery.

Fig. 10 shows a detailed circuit realization of the analog-to-digital converter 308 generally shown in Fig. 8.

The input signal is applied to a bilateral switch, which is in the form of a switch 407, the output of which in turn is applied to the voltage-controlled oscillator 402, which is included in a circuit with a phase-locked loop. The output signal of the voltage controlled oscillator is in turn applied to the accumulator counter 400, which consists of four reversible counters CD4029A. The clock frequency FCLK is applied together with the strobe pulse via conductors_188 and 420 to time the output of the accumulator 400 to the "N" output counter 412. A key part of the illustrated realization of the analog-to-digital converter 308 is that the control circuit 408, Fig. 8, is constructed to include a counter 409 in the form of a four-bit ring counter. This counter 409 forces the analog-to-digital converter 308 to one and only one of four possible states, corresponding to its four output states 0, 1, 2 and 3. These four operating states of the analog-to-digital converter 308 are, as shown in Fig. 10, (1 ) wait, (2) preset, (3) count up and (4) count down.

The standby state is a quiescent state of the analog-to-digital converter 308, in which the voltage controlled oscillator 402 is turned off, the unknown voltage and the reference voltage, _._._...-__.__._...__ .., _ . 10 l5 20 30 35 79n62os-5 47 is disconnected via the switch S1 from the oscillator 402 and the last converted digital word remains in the counter 412 as a digital word of eight parallel bits. The converter 308 rests in this wait state until it receives a strobe pulse, which drives it to the preset state. Very little power is drawn from the analog-to-digital converter 308 while it is in the standby state.

The preset state follows the wait state and is used to preset the accumulator, which consists of counters 400a, 400b and 400c, on a binary word one via a "jam" input. The counter 4112 is reset during the preset state. The maximum time that the preset condition prevails is half the clock period. Z During the counting state, the output of the divider 409 is set to logic 1, forcing the accumulator counters 400a, 400b and 400c to count in this state {During this state, the switch S1 conducts the analog input signal to the input of the voltage controlled oscillator 402.

Furthermore, the "n" counter 410 begins to control the length of time the unknown voltage is applied by counting the reference clock frequency to the pre-programmed count, which will transfer an output 9 from an AND gate '425 to a logic 1. counting pulses are accumulated in the counters 400a, 400b and 4000. When the output 9 of the AND gate 425 reaches the level logic 1, which indicates that the time period for counting upwards has been reached, both its outputs 8 and 9 are at the level logic l and an instruction When the next clock pulse reaches logic l, the ring counter is applied to the next state, which is the countdown gate 427. the counter 407 is applied to the ring counter 404.

A countdown state is established by transferring the output 7 from the ring counter 409 to logic 1. This state forces the accumulator counter 400 to count down.

The reference voltage is also applied to the voltage controlled oscillator 402. Likewise, the clock frequency is conducted to the input of the N counter 4112. Thus, as the counts 10 15 20 25 30 35 7906205-5 48 are driven from the accumulator counters 400a, 400b and 4000, clock pulses accumulate in the N-counter 412. When the accumulator-counting chain has been driven to logic 0 in all states, the AND gate 429 passes output to logic 1 and forces the ring counter 409 to its waiting state via the previously described pulse capture network. The completion of this cycle results in the unknown input voltage V (x) being digitized and stored in the output counter 412 with the scaling factor, as described above.

As shown in Figs. 8 and 10, the analog-to-digital converter 48 is specifically designed to be included in the stimulator 12 shown in Fig. 1. As indicated above, it is important that the stimulator include circuits which require a minimum current withdrawal from the stimulator's power source, e.g. ex its battery. For this purpose, circuits such as those shown in Fig. 10 for the sake of convenience can be realized by CMOS technology. Second, as described above, the oscillator 402 is activated only to provide an output signal during the times when an analog input signal V (x) is to be digitized, while the oscillator 402 is inactive at all other times. The operation of the oscillator 402 takes place under the control of the control circuit 408 and in particular of the ring counter 409. Thirdly, the analog-to-digital converter 308 can be adjusted to include different values of "n" in the counter 410, whereby the analog-to-digital converter 308 is adapted to sense voltages of varying amplitudes. . In the various embodiments of the stimulator of the present invention, as described above, it is contemplated that it would be desirable to convert the relatively high voltage Vs of the battery as well as the relatively small voltage signals derived from the patient's ventricle. As shown in Fig. 10, the preselected count-up time period Tup is determined by the value "n" as set in the counter 410.

In an illustrative embodiment of the invention, the value of "n" can be set by connecting one of the outputs Q4, Q5, Q6 and Q7 from the "n" counter 410. It is possible to: include a switch circuit (not shown) between one of the counters 410 outputs and AND gate A9, whereby the value of "n" could be set under the control of the microprocessor 300, as shown in Fig. 7A. In addition, a programmable counter, as is well known in the art, could be used in place of the current counter 410, whereby a suitable binary word could be stored in the counter to be varied under the control of the microprocessor. The value of "n" could thus be varied depending on which analog input signal is to be converted to digital form.

The value "n" is varied depending on the amplitude of the intended input voltage V (x), with larger values of "n" being selected for smaller amplitudes. In practice, it is desirable that in the output counter 412 a count be obtained which is close to the known capacity of the counter, whereby the maximum resolution of an input signal of a given amplitude is ensured. Thus, a single analog-to-digital converter 308 can be used for different inputs of varying amplitude while ensuring the accuracy of the binary output by varying the value of "n".

Claims (9)

10 (15 20 25 30 7906205-5 50 PATENT CLAIMS An implantable cardiac stimulator, which is arranged to provide a therapeutic stimulation of the chamber of a patient's heart via a conduction system and which comprises an atrial connection (17) for connection to the conduction system and a chamber connection (19) for connection to the conduction system, characterized of an atrial sensing amplifier (39) coupled to the atrial connection (17), which is adapted to generate an atrial sensing signal in response to a detected depolarization of the atrial tissue, a ventricular sensing amplifier (139) coupled to the ventricular connection (19), in response to detecting a depolarization of the ventricular tissue, generating a ventricular sensing signal, a ventricular pacing means (134a, 130a) coupled to the ventricular connection (19), which is arranged to output a pacing pulse, a microprocessor system, in response to an ventricular 100), which is connected to a multiplexer means (106) and connected to the ventricular pacing means, the ventricular sense amplifier and the atrial sensing amplifier generating a first set of control signals during a first PR delay period, a second set of control signals during a second atrial insensitivity period and a third set of control signals during an atrial sensing period. if an atrial sensing signal occurs during the atrial sensing period, and generates a ventricular trigger signal after the end of the PR delay period, unless a ventricular sensing signal is generated during said PR delay period. A stimulator according to claim 1, characterized by memory means (102), comprising at least first and second storage portions (10a, 102b), each of which stores a particular process for stimulation known by the patient's patient. heart, the microprocessor system (100) selectively executing one of the programs stored in the memory means and comprising address means (107) for addressing the program stored in a selected storage portion in the memory means. Stimulator according to claim 2, characterized by reset means (344) coupled to the microprocessor (300) for periodically generating a reset signal for resetting the address means (307) to a predetermined return address, whereby, if the address means inadvertently addresses a known - meaningless location in the memory means (302), the microprocessor execution of a selected program in the memory will be continued by addressing the predetermined return address in the selected program. Stimulator according to claim 3, characterized in that the microprocessor (300) comprises means connected to the resetting means (344) for periodic generation and supplying a repeal instruction signal to the resetting means for canceling the work of the resetting means, if the address The nne means (307) operate correctly. Stimulator according to claim 4, characterized in that at least some of the inputs to the multiplexer means (106) are of analogous type and that analog-to-digital conversion means (108) are included and connected to an output of the multiplexer means receiving and converting the selected analog inputs to a corresponding digital signal for supply to the microprocessor system (100). A stimulator according to claim 5, comprising scaling means (108) for selectively varying the gain applied to the selected input signal so that the signals transmitted by the microprocessor system (100) have substantially the same amplitude. Stimulator according to claim 2, characterized in that means are arranged for selectively changing the address of the address means, so that the address means address a start location in another of the first and second storage portions. , whereby another way of stimulating the patient's heart is performed. Stimulator according to claim 2, by means (104) for reprogramming the feature - characterized the program stored in either (10bb) of the first and second storage portions (102a, 10bb), so that the method of stimulating the patient's tissue changes. An implantable stimulator, which is arranged to provide a therapeutic stimulation of a patient's heart via a conduction system and which comprises atrial and ventricular connecting means (17, 19) for connection to the conduction system, characterized by the connecting means (17, 19) coupled atrial and ventricular sensing amplifiers (139), respectively, which are arranged to provide atrial sensing signals and ventricular sensing signals and which have transmission means (130c) which are arranged to render the sensing amplifier (139) insensitive to electrical signals on the connection means, (130a, 134a), which is coupled to the chamber connection means (19) for generating a pacing pulse in response to chamber trigger signals, and a microprocessor system (100) which is connected to a multiplexer means (106) and which can issue a series of instructions defining an ventricular escape interval, and generate a ventricular trigger at the end of the rescue interval in the absence of atrial and ventricular sensing signals, the system further comprising locking means connected to the transmitting means and arranged to store a set of control signals which can render the pre- and ventricular sensing amplifiers insensitive to electrical activity on the connections. - the signal.