DE2929498A1 - IMPLANTABLE ELECTRONIC DEVICE - Google Patents

Abstract

A multi-mode pacemaker includes a microprocessor 100 and a memory 102 programmable with a variety of processes for stimulating a heart and/or a sensing and transmitting to an external device conditions of the heart or pacemaker. The microprocessor controls a multiplexer 106 to input via a scaling amplifier and a/d converter 108 signals from atrial and ventricular leads 17, 19, the power source 126, a reed switch 23 operable by an external magnet, or redundant leads on lines 138d,e. The output comprises latch drivers 134 a-d with respective output select switches 130 a-d selectively operable to supply stimulation pulses to the leads or allow sensing. External apparatus 104 may transmit coded information to change the stored program or operation of the reed switch may select a different program starting address. Pulse width, rate and amplitude may be controlled in response to sensed heart activity or power source level and different pacing modes (demand, asynchronous, etc.) or multi-site pacing to disrupt arrhythmias may be selected automatically or externally. In an aid converter 308 (Figure 8), counter 400 counts up the output of VCO 402 controlled by unknown signal V(X) and then counts down to zero the output of VCO 402 then controlled by reference EREF and during such countdown a counter 412 counts clock pulses so that when counter 400 reaches zero the output of counter 412 depends on V(X) but not on the scale factor of VCO 402. <IMAGE>

Description

Ger. P-338

MEDTRONIC, INC.

3055 Old Highway Eight, Minneapolis, Minn. 55440 V. St. A.

Implantable electronic device

The invention relates to an implantable electronic device and, more particularly, to a device that can be used in a plurality of Modes of operation can be operated to stimulate body tissue or to address various conditions of the device itself or from body tissue such as a patient's heart.

Cardiac pacemakers are known (US Pat. No. 3,057,356) which deliver electrical stimuli to the heart, causing the heart to contract at a desired rate, on the order of 72 beats per minute. Such a pacemaker can be implanted in the human body and work there for a long period of time. Typically, pacemakers are surgically implanted in the pectoral or abdominal area of the patient

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an incision is made in the affected area and the pacemaker has its own internal power supply is inserted into the patient's body. Said pacemaker works asynchronously, i. i.e., he cares for a fixed rate stimulus that is not is changed automatically according to the body's needs. Such a pacemaker was found to be effective at face the symptoms of complete heart block. However, an asynchronous pacemaker has the potential disadvantage that it competes with the natural, physiological pacemaker during periods of normal sinus function

Artificial demand pacemakers are also known (US Pat. No. 3,478,746) in which artificial stimuli can only be triggered when necessary and then suppressed when the heart returns to the sinus rhythm. The on-demand pacemaker eliminates the problem that occurs with asynchronous pacemakers by locking itself in the presence of ventricular activity (the R-wave of the ventricle), but switching to on-line mode when there is no ventricular activity and supplements missing heartbeats.

One with such known, implantable, on-demand pacemakers A related problem is that previously there was no possibility without surgical intervention Frequency or other operating parameters with which this stimulus

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pulses are generated to temporarily increase or decrease. Another problem is the great difficulty in determining the remaining battery life, one Detect and correct failure of an electrode and an appropriate R-wave sensitivity safety range with an implanted reliever pacemaker.

Some known implantable cardiac pacemakers allow the pulse rate to be overridden, but do not control the satisfactory compliance with the demand function. Other Devices are equipped with a magnetic reed switch arrangement that allows the demand amplifier to be deactivated, to control the demand function; but it is missing a possibility of overriding the rate.

Another improvement that has become known is the provision of means that allow the pacemaker to be reprogrammed after implantation. For example, a circuit arrangement is known (US Pat. No. 3,805,796) which allows the pacemaker rate to be changed without surgical intervention after the pacemaker has been implanted. The rate will change according to the number of times a magnetically actuated reed switch is closed. The number of times the reed switch is closed is counted; the relevant count is stored in a binary counter.

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Each stage of the counter is connected in such a way that a resistor in a series-connected chain of resistors is activated or bridged. The resistor chain is part of the RC timing element that controls the pacemaker rate pretends.

The principle outlined last was made possible by a programmable Improved pacemaker (US-PS 4,066,086) that responds to the application of RF pulse trains while a magnetic field, generated in the vicinity of a magnetically actuated reed switch located in the pacemaker housing, the Keeps the reed switch closed. In this circuit arrangement, too, only the rate is a function of the number of applied RF pulse trains programmable. The use of RF signals for programming cardiac pacemakers is also known from US Pat. No. 3,933,005. The one described there Device allows both rate and pulse width to be programmed. So far, however, no pacemaker has been made which is able to program more than two parameters or more than two predetermined parameters on command Run tests. Such a pacemaker could be described as a universally programmable pacemaker.

An area in which pacemaker technology has so far lagged behind the conventional state of electronics technology lags behind, the use and exploitation of digital

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talen electrical circuits. One reason for this was the high Energy required to operate digital circuits. Due to recent technological advances in the field of large-scale CMOS devices and improvements to pacemaker batteries digital electronic circuits are now beginning to be used in commercial pacemakers as well. The advantages of digital circuits are their accuracy and reliability. Typically one works digital circuit depending on a crystal oscillator that has a very stable frequency over extended periods of time supplies. Proposals have been made since at least 1966, digital techniques in cardiac stimulation devices and pacemakers apply. For example, see the article by Leo F. Walsh and Emil Moore entitled "Digital Timing Unit for Programming Biological Simulators "in The American Journal of Medical Electronics, Q1 1977, pages 29-34 referenced. The first patent to suggest digital techniques in the present art is U.S. Patent 3,557,796. There is disclosed an oscillator driving a binary counter. When the counter reaches a certain count, a signal is delivered that indicates the delivery of a cardiac stimulus caused. At the same time the counter is reset; he begins again to count the oscillator pulses. There is also a digital demand concept in which the counter returns after a natural heartbeat has been recorded.

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ORIGINAL INSPECTED

is provided, and a digital refractory concept is described, after which the output signal for a predetermined period of time after the delivery of a cardiac stimulation pulse or the Detection of a natural stroke is blocked.

Digital programming methods are known from US Patents 3,805,796 and 3,833,005 known. The latter reference also discloses a digital control circuit for controlling the rate of the stimulus pulses by causing a resettable counter to continuously count up to a certain value which is compared with a value programmed into a memory register. The output pulse width is also set by switching over the resistance in the RC circuit that specifies the pulse width.

Another state of the art that deals with pacemaker applications suitable digital techniques can be found in U.S. Patents 3,431,860, 3,857,399, 3,865,119, 3 870 050, 4 038 991, 4 043 347, 4 049 003 and 4 049 004.

Although it has already been proposed, various parameters, namely the pulse width and the pulse frequency, in one To make implanted pacemaker modifiable, there is a need for a device that is capable of several different Pacemaker and / or monitor modes of operation. The known systems can by means of a

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digital counter circuit store a programmable word, which is indicative of a desired rate or pulse width. In the case of an implanted device, the room is for housing a plurality of such counters which would allow a number of such functions to be programmed. In addition, the energy available to feed such meters as well as the service life of the internal energy source to be taken into account with regard to the expected current draw. It is recognized in the art that numerous factors limit the complexity of the circuitry provided in an implanted device which includes the current draw from the battery and, accordingly, the expected battery life before the energy source of the device has to be replaced as part of a surgical procedure.

The invention is accordingly based on the object of providing an implantable device with increased flexibility and adaptability that allows a variety of processes to be performed including tissue stimulation and telemetry belong. According to a preferred application of the invention, an adaptable, implantable Multipurpose pacemaker can be created that can be programmed to perform as a function of before or after implantation of the respective condition of the patient for a different stimulus impulse application or remote measurement

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care for. It is to be obtained, an implantable electrical device that is provided with a message link to transmit signals to and from a arranged outside the body of the patient transmitters, so that control signals Submitted can be, in order to influence the running of the implanted device process, and that data relating to the activity of the tissue (heart) and data relating to the functions of the implanted device can be received by the implanted device.

With regard to these and other tasks, an implantable electrical device, for example in Form of a cardiac pacemaker, which has a control in the form of a digital computer, for example a microprocessor, and a memory in which a plurality of different processes or programs for generating of stimulus pulses are stored, which are executed by the microprocessor in order in this way to the body tissue To apply stimulation impulses. Data which form part of the program stored in the memory determine, for example the pulse width of and the period between stimulus pulses.

According to a further feature of the invention is for a connection between the implanted electrical device and an external transmitter so that encrypted

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. - 27 -

Control signals can be transmitted to the implanted electrical device, whereby the effected by means of the controller Process is changed or reprogrammed. The transmitted control signals can in particular change the address, to which the microprocessor in memory has access, so that a new process is then carried out which is on the new address begins. In a further embodiment of the invention, the transmitted from the external transmitter can be used Reprogram the memory signals with a new set of parameters, making variables such as the pulse width or pulse amplitude, the duration between stimulus pulses and the sensitivity of the measuring amplifier can be changed. In addition, control signals can be transmitted in order to change the type of stimulation impulses applied to the heart. To the stored, selectable operating modes preferably include a chamber demand stimulation, an asynchronous chamber stimulation, a bifocal stimulation, atrial synchronous, ventricular-locked stimulation (ASVIP), an extension of the pulse width as a function of the voltage of the energy source or battery, a stimulation with automatic threshold value tracking, in which the pulse width of the pacemaker pulse is set to the smallest value that still leads to cardiac entrainment and cardiac stimulation at multiple points to interrupt arrhythmias. It can also be in memory a program or programs for performing a plurality of telemetry functions are stored. In addition

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especially hear the recording of various cardiac activities or from other bodily functions as well as the transmission of data relating to the operation of the pacemaker, such as parameters for the respective pulse width, pulse amplitude, the interpulse interval, current and voltage of the power source, moisture content within the implanted device, Pacemaker lead impedance and pacemaker self-test programs.

According to a further feature of the invention, the pacemaker comprises a multiplexer controlled by the microprocessor to select one of a plurality of inputs, whereby optionally one after the other for the cardiac activity of the Signals identifying patients, e.g. B. Signals relating to atrial and ventricular activity, or other body conditions or conditions, such as moisture applied inside the pacemaker, can be processed by the microprocessor to become. A selected output of the multiplexer is sent to an A / D converter and normalization amplifier stage supplied, whereby the analog input signal is converted into a digital signal and brought to the appropriate size to to be processed by the processor.

In a further embodiment of the invention, the memory has a plurality of blocks for each receiving a program to be executed by the microprocessor. With such training

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ORIGINAL INSPECTED

The management form is the multiplexer with inputs for receiving a digitally encrypted signal to cause a change of address, creating a starting place in a other block can be addressed to cause the execution of the program in that block. The digitally encrypted Address signal may optionally be sent to the multiplexer of the implanted pacemaker from an external transmitter are transmitted from, so that the doctor is able to change the program executed by the microprocessor, to provide a different type of stimulus application depending on the given condition of the patient.

In accordance with a further feature of the invention, the microprocessor provides output control or clock signals to a group of selector switches, each of which is coupled to its own driver and line. A line can from that Pacemaker to a certain point of the heart, e.g. to the ventricle or to the atrium, to another body tissue a mechanical transducer used to detect physical activity or to one located inside the pacemaker Transducers lead to a state of the pacemaker, for example the humidity. By optionally closing one of the selector switches, the relevant line is connected, For example, to stimulate tissue or to pick up a signal that is indicative of a condition to be monitored is. A failure of a line can thus be countered

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that redundant lines are provided. Will the If one lead fails, a second lead can be connected between the pacemaker and the patient's heart to continue for tissue stimulation or to provide surveillance. According to a preferred embodiment of the invention, a decoder is for acquisition and decrypting digital signals derived from the memory of the pacemaker in order to provide the Closing the relevant switch to generate and apply serving control signals, so that one of the plurality of switches and the respective associated lead is optionally coupled to the pacemaker.

According to a further feature of the invention, an oscillator circuit with automatic reset is provided, which is designed to reset the addressing device or register of the microprocessor. So if a External interference signal causes the address register to have a free or incorrect location within the system's memory addressed, the process remains uninterrupted. Rather, the addressing device is reset after a predetermined interval in order to start the process from the beginning. If the addressing device works normally, there are the microprocessor periodically sends a blocking signal to the self-resetting oscillator circuit, which prevents a reset command from being fed to the addressing device.

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ORIGINAL INSPECTED

The device according to the invention allows the pacemaker pulse width to increase when the supply voltage drops. Due to the presence of multiple lines you can not only damaged lines are bridged. Rather, it can be used for redundant recording of measured values and / or stimulation impulses to be taken care of; furthermore, that line can be selected which has the most favorable threshold value for the Has measured value acquisition and / or stimulation impulses; it can also be from a unipolar electrode to a bipolar electrode be passed over.

The device can be designed in such a way that it automatically selects the most favorable operating mode based on the detected signals. Self-test or data acquisition programs can be stored in the memory, for example to check the accuracy of peripheral components, e.g. B. the measuring amplifier, with or without telemetry transmission to control.

The invention is described below on the basis of preferred exemplary embodiments explained in more detail. In the accompanying drawings show:

Fig. 1 'is a schematic representation of a

programmable pacemaker implanted in a patient, to and from which signals are transmitted,

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the program performed by the implanted pacemaker to change or adapt and to allow for the activity of the heart (or other tissue) display characteristic signals on an external monitor,

Fig. 2 is a functional block diagram of the

implanted pacemaker according to FIG. 1,

3A is a circuit diagram of the step

Makers of Fig. 2 to the patient's heart going connections for stimulating impulses and recording of measured values in the chamber operation,

3B is a circuit diagram of the step

Maker of Fig. 2 leading to the heart of the patient connections for A-V follow-up stimulation of Atrium and chamber,

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ORIGINAL INSPECTED

Fig. 3C * a circuit diagram of the connection between

between the pacemaker according to Figure 2 and the atrium and the ventricle
for performing atrial-synchronous, ventricular-locked stimulation (ASVIP),

Figure 4A is a flow chart for the scarf

ter and the components of the circuit arrangement according to FIG. 3A for
Carrying out a chamber demand stimulation,

4B is a flow chart for the actuation

supply of the switch and the components of FIG. 3B for implementation bifocal stimulation,

4C is a flow chart for the actuation

supply of the switch and the components of Fig. 3C for implementation an ASVIP stimulation,

Fig. 5 is a flow sheet for one of several

reren to be stored in the memory of the pacemaker according to FIG.

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the programs for carrying out a chamber demand stimulation according to the flow chart of FIG. 4A,

6 is a functional block diagram ei

Another embodiment of the Pacemaker according to the invention,

Figs. 7A and B circuit diagrams of two execution

shaping the pacemaker according to Fig. 6,

Fig. 8 is a functional block diagram of the

with the pacemaker according to FIGS. 6 and 7 provided A / D converter,

FIG. 9 shows a graphic representation to explain the mode of operation of the up / down counter according to FIG. 8, and

Fig. 10 is a circuit diagram of the A / D converter

according to FIG. 8.

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Fig. 1 shows a pacemaker operating on a plurality of Modes of operation can be programmed so that the heart of the patient, whose atrium is denoted by 40 and whose chamber is denoted by 42 stimulation pulses can be applied in different ways. It also increases the electrical activity from the atrium (atrium) and chamber (ventricle) or from other body tissue to determine either the pacemaker operating parameters to modify or to transmit corresponding signals remotely from the body 14 of the patient.

The pacemaker 12 has a housing 13 that is resistant to body tissue and fluids, a first lead 17 which is coupled to the atrium 40 and attached there via an electrode, and a second lead 1? on, which is in communication with the chamber 42 and is fixed to this via an electrode. An external transmitter 10 is connected via a line 15 to a coil or antenna 16 which is arranged outside the patient's body 14 in order to transmit signals to the implanted pacemaker 12 via an RF connection. A monitor 63 is connected to the transmitter 10 via a line 59 . The transmitter 10 can be caused to transmit signals to the implanted pacemaker 12 via the line 15 and the antenna 16 in order to allow it to change from one operating mode to a selected other operating mode. In this way, the doctor can specify the manner in which the patient is in a changed condition

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ORIGINAL-INSPECTED

2Ü9498

which stimulate impulses are delivered to the heart of the patient. It will be understood that at the time the pacemaker 12 is surgically implanted in the body 14, a particular type of stimulation may be desired. The patient's condition may change after implantation. Another operating mode may then be desired. In addition, there is a desire to transmit a series of signals from the patient's body which are characteristic of various detected conditions and which run via the antenna 16 and the transmitter 10 in order to be displayed on the monitor 63. The implanted pacemaker 12 can furthermore, as shown in FIG. 1, have a further output and a line 25 coupled to a transducer 27. The transducer 27 can be a mechanical transducer that detects the movement of a body organ. Furthermore, the pacemaker 12 can be equipped with an additional output and a line 21, which is connected to a magnetically operated reed switch 23, which can be operated by the doctor by bringing an external magnet close to the switch in order in this way to close the switch 23 and bring about a change in the mode of operation of the pacemaker 12. A line 29 is representative of a plurality of lines which can be coupled to different parts of the heart, for example to provide stimulation that suppresses an arrhythmia, or to provide redundant lines that can replace a defective line 17 or 19.

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ORJGlNAL INSPECTED

Figure 2 shows a functional block diagram of the pacemaker 12, which has a microprocessor 100 as the central control element and a multiplexer 106 to receive analog data from a first input 138a, which is via the first line 19 (Fig. 1) is coupled to the ventricle 42, and a second input 138b come, which via the second line 17 with communicates with the atrium 40 (FIG. 1). The various analog (and digital) inputs are used by the multiplexer 106 is selected in a predetermined manner under the influence of the microprocessor 100 and in accordance with the processes or programs processed, which are stored in a memory 102.

The microprocessor 100 is via an address bus 112 with the Memory 102 connected so that stored addresses which are forwarded by means of an address counter 107 are applied, to address selected locations within memory 102. The addressed data are from the memory 102 via a Data bus 110 transferred to microprocessor 100.

The multiplexer 106 has additional inputs 138c, d, e and f. The microprocessor 100 provides control signals over an input selection bus 120 to the multiplexer 106, whereby one of the inputs 138a to f is selected to transmit the signal in question a line 118, a normalization amplifier and analog-to-digital converter stage 108 and a bus 114 to the microprocessor 100. As is apparent from Fig. 2, the output voltage becomes V of a voltage source 126 via the input 138c to the

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Multiplexer 106 applied to pacemaker performance to modify appropriately depending on changes in the voltage source. For example, it is desirable to increase the stimulus pulse width when the supply voltage drops in order for a pulse with more or less to provide constant energy; it may also be desirable to reduce the pacemaker rate when the supply voltage drops, to indicate that the pacemaker has been replaced or modified via external programming must become. The reserve inlets 138d and 138e can also be provided to the chamber 42 and the atrium, for example 40 be coupled in order to redundantly monitor the activities of these areas of the heart. The interpretation can be made so be for the microprocessor to select which of the inputs 138a, b, d and e for the most efficient detection of the Provides atrial and ventricular signals or requires the least amount of energy from the voltage source 120 or a cardiac arrhythmia interrupts most effectively. The input 138f can be connected to the reed switch 23 via the line 21. if then the doctor arranges an external magnet so that the switch 23 closes, the microprocessor 100 is caused to to change or change the program stored in the memory 102. The multiplexer selects or controls the series to one of the inputs 138a to f to the relevant input via the line 118, the stage 108 and the bus 114 to connect to the microprocessor 100. The multiplex operation

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is provided in order to reduce the circuit complexity for the processing of the analog information which is fed to the inputs 138a to f, as well as in order to further reduce the energy requirement for this function. Without the multiplexer 106 would have to
a separate normalization amplifier and A / D converter stage 108 can be provided for each of the inputs 138a to f. By
the use of the multiplexer 106 thus becomes the
Current draw from voltage source 126 reduced; At the same time, this reduces the circuit complexity for the pacemaker 12.

The microprocessor 100 applies a normalization control signal to the normalization amplifier and A / D converter stage 108 via a line 116. This increases the gain of the
a part of the stage 108 forming amplifier so that the different amplitudes of the signals into account
carried to the inputs 138a to f of the multiplexer
106 to be received. The output voltage of the voltage source 126 can, for example (initially) be on the order of 1.3 to 6 V, while the cardiac activity signals derived from the atrium 40 and the chamber 42 can have a voltage on the order of 1 to 20 millivolts, for example. The output signal of the amplifier and A / D converter stage 108 is a sequence of digital signals that are in the microprocessor 100,
in particular in the registers of the microprocessor 100 are stored. According to a preferred embodiment

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Rung form of the invention, the microprocessor 100 is implemented in CMOS technology with a low threshold value, what for a relatively low current draw from the voltage source 126 ensures.

An essential component of the pacemaker 12 is the memory 102, which can expediently have a read-only memory part (ROM) 102a and a memory part 102b with direct access (RAM). The basic steps of each of a plurality of pacemaker modes (or other processes) are stored in the read-only memory part 102a. On the other hand, a plurality of parameters or whole programs are stored in the RAM storage part 102b; this part can be reprogrammed at a later time depending on the changing condition of the patient. The memory 102 can be programmed at the time of manufacture, prior to implantation in the patient's body 14, or via an external memory charging interface 104 that is coupled to the memory 102 via an RF connection or an acoustic connection 105. Known devices (US Pat. No. 3,833,005 and US Pat. No. 4,066,086) can be used as the interface 104. In this context, for example, a receiver filter can be provided which detects sequences of RF pulses which are transmitted by an external transmitter and which are encrypted in such a way that a program stored in the memory 102 is reprogrammed or

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that alternatively a parameter which is stored in a memory location of the memory 102 is changed.

Therefore, if, after the pacemaker 12 is implanted in the patient's body 14, the doctor sees a change in condition of the patient can be observed, the program or special variables of a program stored in the RAM part 102b can be reprogrammed to provide stimulation to the heart that is appropriate for the changed State best suited. Various parameters occur during stimulation, such as the pulse width of the stimulus pulse, the rate or frequency of pulse delivery, the duration between the application of a pulse signal and the detection of the resulting cardiac activity, during this the measuring device is made ineffective, and the pulse amplitude. Typically, each of these parameters is for example determined in the form of an 8-bit word, which is stored in a word location of the RAM part 102b of the memory 102 will. Therefore, if it is desired to change the pulse width, the physician need only via interface 104 and the link 105 to enter a new 8-bit word in a known, addressable word space within the RAM part 102b, which is indicative of the new pulse width with which the pacemaker 12 is to operate. A new type of stimulation can can also be programmed into the RAM part 102b by the relevant steps of the new

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Process. Alternatively, you can change the operating mode thereby causing the starting location of the desired program from RAM portion 102b to be in the address counter 107 of the microprocessor 100 is entered in order to address the next program within the ROM part 102a of the memory 102 to trigger. For example, when the initial mode of operation of the pacemaker 12 is a chamber demand sstimulation and it turns out to be desirable to switch to A-V follow-up stimulation, the Doctor the new starting address for the A-V follow-up stimulation type via the interface 104 to gain access to another portion of the ROM portion 102a, whereby the Microprocessor 100 begins to function in the next mode of operation.

As will be explained in more detail below, it is useful to measure the energy of each stimulus pulse supplied to the heart of the patient to keep constant, even if the voltage level of the energy source 126, for example a battery, in Decreased over time. According to F.ig. 2 sets the multiplexer 106 periodically applies the battery voltage V via the input 138c to the microprocessor 100, which is under the influence of a program stored in the memory 102, the measured voltage with various predetermined voltages compares stored in the ROM part 102a or the RAM part 102b. In this way an adjustment is made

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the pulse width of the stimulus pulse to determine the energy content, d. H. the area below the stimulus curve to keep essentially constant.

The memory 102 can be loaded with a program that makes a self-selection. In other words, such a program can respond to cardiac signals sent to the inputs 138a and b are applied to determine the condition of the heart and, depending on the sensed condition, one select from several programs. The distinguishing features of the on the atrial P-wave and the ventricular R-wave declining input signals are in the publication "Electrocardial Electrograms and Pacemaker Sensing" by P. Hoezler, V. de Caprio and S. Furman in "Medical Instrumentation" Volume 10, No. 4, July / August 1976, discussed in detail. The criteria by which this Cardiac signals to be recognized and compared are stored in memory 102. When a change is detected the microprocessor can automatically select a different pacemaker mode for the changed Conditions of the heart of the patient is suitable without an external intervention by a doctor via the external memory charging interface 104 becomes necessary.

According to a further operating mode, the memory of the pacemaker 12 can be programmed in such a way that it is used as an

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automatic threshold tracking pacemaker works, where the energy of the stimulus pulses applied to the chamber 42 (or the atrium 40) can be gradually decreased until no more entrainment takes place, i.e. until the stimulation impulses no longer trigger a ventricular contraction, which is caused by an inside R-wave detected during a measuring or monitoring period noticeable. If in this operating mode the R wave is within the Measuring period is detected, a control signal is generated, on the basis of which the pulse energy is reduced by a predetermined amount will. This is preferably done by decreasing the pulse width until there is no pacemaker triggered R-wave more is noted. Then the program increases the pulse width until the R wave reappears. In this way the energy draw from the voltage source 126 is minimized because the pulse width is set to a value which is just enough to keep the heart entrained.

In the circuit configuration according to FIG. 2, the control output signals of the microprocessor are applied via lines 131 to latch driver 134 and via a bus 132 to corresponding selector switches 130, which generate appropriate pacemaker pulses via lines 17 and 19 (or 29) in accordance with the processes stored in memory 102 enter the atrium 40 and / or the chamber 42 of the heart. The line 131a is coupled to a first or chamber driver (or amplifier) 134a, which in turn is connected to his

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ORIGINAL INSPECTED

own group of bipolar / unipolar selector switches 130a connected is. The driver amplifiers 134b, c and d are each assigned a corresponding group of selector switches. For example the output of driver 134b is connected to selector switches 130b to the atrium via conductors 17a, 17b and 17c to be controlled. The drivers 134a to 134d can increase voltage levels, e.g. voltage doubler or tripler, in order to raise the output voltage level to the value which is necessary to effectively stimulate the heart tissue at a given voltage of the energy source. the Selector switches 130 are controlled by signals coming from the microprocessor over bus 132 to selectively to apply the output of the first driver 134a to predetermined ones of the outputs 19a, 19b and 19c. The switches 130 are connected to the ventricular line 19, which is formed in a known manner (US Pat. No. 4,010,758) as a coaxial line which can be connected via the conductor 19a to a tip electrode and via the conductor 19c to a ring electrode can be. In addition, there is a conductor 19b which is connected to a plate formed by the metal container or housing 13 within which the pacemaker 12 is housed. In normal bipolar operation, the selector switches 130 release the negative and positive stimulus pulses reach the tip electrode and the ring electrode via the conductors 19a and 19c of the coaxial line. if it is desirable to stop the stimulation pulse application in the conventional

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to carry out unipolar operation becomes a negative one Voltage is applied to the tip electrode via the conductor 19a, while a positive voltage is applied to the via the conductor 19b Plate goes. The ring electrode is not connected.

It is not only desirable to be able to work in bipolar or unipolar mode, but a pacemaker insensitive to errors should also be created, in which, in the event of a defective lead due to a defective connection of an electrode lead to the heart tissue or due to breakage or damage On a line, the microprocessor 100 provides appropriate control signals over the bus 132 to the selector switches 130, thereby selectively coupling another combination of lines (or conductors within the lines) to deliver the pacing pulses to the chamber 42. The selector switches 130 can be arranged, for example, so that the conductors 19a and 19c can be connected to one another. Alternatively, the selector switches 130 are selectively closed so that heart pulses are applied between the conductor 19a or the conductor 19b and the conductor 19c. If one of the conductors 19a or 19b fails, the other can easily take its place in order to continue to deliver the pulse to the heart at two points.

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The failure of one of the lines 17 or 19 can be through Detect the loss of entrainment, i.e. by the fact that at the input 138b after the impulse has been applied to the ventricle no cardiac activity signal appears. Alternatively, the measurement shows a high impedance between the conductors 19a and 19b of the coaxial line 19 indicates a failure of the line, which is due to the formation of scar tissue between the Tip or ring electrode and the ventricle 42 or the breakage of one of the conductors. To Upon detection of such a failure, the microprocessor 100 selects another process or another in the memory 102 stored program to apply signals to one of the selector switches 130 and reconnect the line 19 (or 29) in the manner described above.

An output of the microprocessor also goes to a second or atrial driver amplifier 134b, the output of which is connected to a further group of selector switches 130 in order to have a corresponding group of conductors or lines 17 to be coupled to the atrium 40 of the patient (Fig. 1). There are also spare amplifiers 134c and 134d present, take up the output signals of the microprocessor 100 and connected to further groups of selector switches 130 are. Such groups of selector switches 130 can be connected to the patient's heart via redundant lines be. For example, the outputs of the amplifier

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134c and 134d may also be connected to chamber 42 and atrium 40 in a redundant manner. If one of the lines 19 or 17 should break or the resistance between the associated electrode and the heart becomes excessively high, a redundant line between the microprocessor 100 and the heart can be switched on by actuating the relevant selector switch group 130 accordingly. In order to measure the impedance of one of the lines 17 and 19, the line in question is connected to an output stage which is explained in connection with FIG. 3 and which has a charging capacitor. The charging time of this capacitor is characteristic of the impedance formed by the associated line. The output capacitor is charged during operation. After it has been charged, the output stage is actuated to cause the capacitor to discharge. As a result, a stimulus pulse is given to the heart via the associated line. The period of time required for charging the output capacitor can be determined in terms of time by starting a counter via a program in the memory 102. The counting process continues until the charging voltage on the output capacitor reaches a predetermined value. The voltage level of the capacitor is measured repeatedly under the influence of the microprocessor 100; if the predetermined level is not exceeded , the counting process is continued. When the charging voltage of the capacitor has reached the predetermined value, the counting process stops; the relevant counter value is used as a characteristic value for the impe-

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ORH3INAL INSPECTED

danz the line used. If the line is broken, the line impedance is high, which results in a longer charging time. If, on the other hand, there is a short circuit in the line before, the charging time is relatively short. First and second time limit values are specified to determine whether the line is short-circuited or whether the line impedance is too high due to a line break. In any case these limit values, which are in the form of time counting values, are checked; if they are exceeded or not reached, the defective line is replaced by a redundant second line.

The spare drivers 134c and d can be provided to provide stimulation in several different places, e.g. five places, in order to cause arrhythmias in this way interrupt, which the pacemaker 12 may detect. Alternatively, the additional drivers 134c and d can be used to set a polarization voltage on the lines 17 and 19 to be eliminated after the stimulus has been applied, or, in the case of high-frequency pacemakers, to quickly charge the output capacitor. Arrhythmias can be determined by measuring the time lag between electrical activity at a first point in the heart, e.g. the atrium and the detection of cardiac activity at a second location, e.g. the ventricle. When the delay falls below a predetermined period of time, for example 100 to 200 ms, this is an indication of a possible

909885/0909

before arrhythmia. Arrhythmias are primarily caused by this causes a second competing ectopic focus to appear in the patient's heart, which is in competition with beats the primary focus that typically appears in the atrium. The two striking centers compete with each other with the formation of an arrhythmia, which makes heart activity erratic and blood no longer pumps effectively will. According to an expedient embodiment a plurality of electrodes each connected to a drive amplifier 134 and a selector switch 130 are on a corresponding number of selected locations of the patient's heart is coupled. Such a line is selected, to deliver stimulation impulses to the heart while the resulting cardiac activities are carried out by means of the remaining lines are recorded at the other places. By means of a program stored in the memory 102, time windows for each of the four lines specified, within whose cardiac activity signals are received. The signals appear not within the relevant time window, this is an indication of a possible arrhythmia. If a detected signal does not occur within the time window assigned to it, another of the several lines is selected to to deliver the stimulation impulses. The remaining lines detect the resulting cardiac activity signals. If the detected signals do not appear in the associated time windows after the new stimulus conduction has been selected

909085/0909

again determined another line. Will this way If the arrhythmia is not brought under control, the program is designed to stimulate all lines to get the heart activity under control. The time periods within which the cardiac activity signals are to be received, are specified as shown below in connection with FIGS. 4 and 5 is explained.

The pacemaker 12 thus forms a high Dimensions flexible and adaptable device that allows to correct or compensate a multitude of factors. These include difficulties in recording measured values and fluctuations over time from the energy source output voltage and unforeseen sources of interference. For example, processes or programs are stored in the memory input to capture the R waves based on key characteristics such as the slope of the EKG signal, the pulse width of the R wave from ventricle 42, the amplitude of the R wave, the Similarity of the R wave to a previous EKG complex and the like. In addition, the memory 102 is programmed to that external AC voltage sources of interference are ignored or insignificant muscle signals are ignored or filtered out will. The advantages of such an adaptable pacemaker 12 are that a single pacemaker is provided which can be programmed according to a large number of operations and which changes with

909885/0900

that allows technology to be constantly reprogrammed. From the manufacturer's point of view, it is no longer necessary to modify every hard-wired circuit in order to develop separate hybrid circuits that differ from one another in relatively minor features, for example by changing the input filter, the pulse width or the pulse frequency. Another advantage of the pacemaker 12 of FIG. 2 is that it eliminates a major source of error in known hardwired pacemakers, namely the timing capacitor capacitors which determine the frequency and pulse width. Currently, hardwired pacemakers use RC charges to perform the timing functions desired, such as determining pulse width, pulse rate, and refractory duration. Experience teaches that capacitors in such circuits can be a major cause of failure.

In the present embodiment of the invention, a microprocessor may be used as the microprocessor 100, which is brought from the RCA Corporation under the name "CDP 1802 COSMAC" or "CDP 1804 COSMAC" (processing on-chip memory) on the market.

As can be seen from FIG. 2, each of the drivers 134 is connected to its own group of selection switches 130 , whereby

909685/0901

a stimulus pulse is fed to a corresponding part of the heart by means of one of the lines 17 or 19. In addition, the multiplexer 106 applies a dialing signal, which is derived from the chamber 42 and the atrium 40 by means of lines 19 and 17, to the microprocessor 100. 3A shows an exemplary embodiment for the arrangement of the driver amplifiers 134 and the selection switches 130 for supplying the stimulus pulses via the line 19 to the ventricle 42 in order to provide for a ventricular demand stimulation. The timing intervals involved are illustrated in Figure 4A. The pacemaker output stage consists of an output transistor Qy, via which the voltage present at a capacitor C. can optionally be coupled to the chamber 42 via the line 19. An output control signal T _{wv of} the microprocessor 100 is fed via the line 131a, the amplifier 134a and a resistor Ry ~ to the base of the transistor Qy, whereby the latter is made conductive. As a result, the previously charged capacitor Cy is discharged to ground; A stimulus pulse with a pulse width which corresponds to that of the signal T ^ y is applied to the chamber 42 of the patient via the line 19. The selector switch 130a is closed for a predetermined period by means of a control signal T ^ y, which is supplied via the bus 132, in order to recharge the capacitor Cy in the interval between successive control signals Ty, y. In this way, the control signal T _W y makes the transistor Qy selectively conductive and non-conductive, whereby a de-

909Ö8S / 0909

speaking sequence of stimulus pulses via the line 19 to the chamber 42 goes. In unipolar pacemaker mode, the Plate or housing 13 of pacemaker 12 connected to the other terminal of the battery.

As can be seen from FIG. 3A, the chamber line 19 is also connected to the multiplexer via the conductor 138a, in particular to a switch 106a ¹ which closes as a function of a time window signal T <-. In this way, a signal indicative of the chamber activity is applied to the microprocessor 100 via the amplifier and A / D converter stage 108. ^{The chamber line 19 is connected to the multiplex switch 106a 1} via the line 138a, a capacitor C1, resistors R1 and R2 and an amplifier 139. When comparing the functional block diagram of FIG. 2 with the circuit layout according to FIG. 3A (as well as FIGS. 3B and C) it must be taken into account that between the components of these FIGS. no exact correspondence exists. Although it is stated that certain switches, in particular the switch 106a ¹ , constitute part of the multiplexer 106, there is a circuit difference in that measuring amplifiers, for example the chamber measuring amplifier 139, are provided in the circuit arrangement according to FIG. 3A (and 3B and C) , while the multiplexer 106 of FIG. 2 connects a particular one of a plurality of analog inputs to a single amplifier 108. It can therefore be assumed that the examples in

909885/0909

3A (and FIGS. 3B and C) shown switching functions can be carried out in different ways. For example, the multiplex switch 106a ′ can be replaced or supplemented by a selector switch 130. The connection point between the resistors R2 and Rl is connected to ground via a capacitor C2. As can be seen from FIG. 4A, it is desirable to hold the amplifier 139 at ground (clamped) during certain periods of time, the refractory period, during which no chamber signal is to be detected. For this purpose, a time control signal T ~ jw ^ ker is applied to line 120 to selector switch 130c, whereby the connection point between resistors R2 and R1 is connected to ground during the refractory period. The circuit formed by the resistors R1 and R2 and the capacitors C1 and C2 serves as a coupling circuit between the chamber measuring amplifier 13? and the heart. When the multiplex switch 106a ^{1 is} closed and the input of the ventricular amplifier 139 is connected to ground, it is desirable to provide a separation between ground and the heart, because otherwise the heart could be seriously damaged. For this purpose the resistor R1 and the capacitor C1 are inserted between ground and the heart. The capacitor C2 also serves as a low-pass filter in order to filter out interference signals which may be present on the line 19 and in order to attenuate the closing action of the selector switch 130c. The chamber measurement

909886/0909

stronger may take the form of a known operational amplifier. The resistor R2 is connected to the input of the amplifier connected to adjust its gain in a known manner.

FIG. 4A shows a flow chart for the chamber demand stimulation corresponding to the output / input connections of FIG. 3A in order to apply stimulation pulses to the chamber 42 by means of the arrangement according to FIG. 2. At time t “a ventricular stimulus was just sent over line 1? applied to the chamber 42 of the patient. Thereafter, the RV amplifier 139 is clamped to ground by closing the selector switch 130c for the refractory period from tn to t1. During the refractory period, the capacitor CV is recharged by applying the control signal T- _v to close the selector switch 130a. This applies the voltage V to recharge the capacitor Cy. At the time of implantation of the pacemaker 12 and with a fresh battery 126, the refractory period is typically on the order of 325 ms. During the refractory period, the cardiac activity of the chamber 42 is not detected because various interfering or extraneous signals may be present in the ventricle 42, the recording of which is not desired. After the refractory period, starting at time t, the selector switch 130c is opened while the switch 106a ¹ closes. When the heart generates an R-wave signal that travels through line 19, conductor 138a, and cam-

S0988B / 0Q0 *

When amplifier 139 ^{goes to closed switch 106a 1} , microprocessor 100 responds by resetting the timing cycle to t _Q. The appearance of the R-wave signal from ventricle 42 indicates that cardiac activity is normal and that it is undesirable to deliver a competing ventricular pace signal. Therefore, as long as the patient's heart is generating an R-wave signal, the pacemaker 12 will not deliver a ventricular stimulation signal. If, however, the measurement period from t 1 to t 2 has elapsed without an R-wave being detected, the microprocessor 100 generates a timing signal T ^ ,,., Which via the conductor 131a, the amplifier 134a and the resistor R ^. goes to the base of transistor Qw. This makes the transistor Qw conductive. The capacitor Cw rapidly discharges through the heart (represented by the resistor R-) so that a stimulus pulse is applied to the chamber 42 via the line 19 and the housing 13. During the stimulation period from t ~ to t ^, the chamber amplifier 139 is kept at ground by means of the closed switch 130c. Based on the discussion above, it will be understood that the various periods corresponding to the pulse width of the chamber pulse between times t 1 and t 1 and the refractory period between t 1 and t 1 can be set or reprogrammed by adding new 8-bit words 2 must be entered into memory 102.

FIG. 5 shows a flow diagram for the steps which take place in the case of the chamber stimulation in the demand mode. About this flow chart

909865/0909

ORlGiNAU INSPECTED

includes the flow chart of FIG. 4A; the connections the output and input stages to the pacemaker 12 of FIG FIGS. 2 correspond to those of FIG. 3A. According to one embodiment of the invention, the microprocessor 100 several pointer address registers for storing pointer addresses or addresses of word locations in the ROM part 102b of the Memory 102. In this embodiment, the Microprocessor 100 uses the following registers for storing the specified address addresses:

R (O) = program counter (PC)

R (3) = loop counter (LC)

R (4) = time counter (TC)

R (A) = reference address for output status table (QP)

R (B) = reference address for duration table (TP)

R (C) = reference address for voltage transition point table (VP)

R (D) = reference address for refractory period (TR) R (E) = input reference address (VDD)

Furthermore, as explained with reference to FIGS. 7A and 7B, the position input signals for the reed switch are supplied to the microprocessor (EF2) and the R-wave (EFl) supplied. The notation for the flag inputs and the reference addresses as well as the counters is used in all of the following program listing. As in As is customary in microprocessors, the microprocessor 100 has the address counter 107, which is used for each step of the program

909886/0909

^Of «GWAL INSPECTED

during this under the influence of the microprocessor 100 is performed to increment by one to designate the next location in memory 102, from the information is to be read out. The steps to be explained with reference to FIG. 5 in connection with a chamber demand stimulation were using an RCA COSMAC microprocessor executed by the following machine instructions:

Storage
address
(Hexadecimal) Symbolic
Notations Storage
content
(Hexadecimal) Remarks step
Storage
Job 00 0000 D = 00 200 01 LDI FS ^ 202 02 00 00 202 03 PHI, 3rd B3 202 04 PLO, 3rd Set LC = O 202 05 GLO, 3 R (3) - > D 204 06 BNZ If LC = OO 204 07 EXIT A3> No? 204 83 EXIT 3A State memory 3D memory address 3D 08 LDI YES? Expose 206 initial state table on F8 ^ Address AO 0? QP R (A) = QP 206 OA PLO, A 206 IF LDI SET 206 OC TP AO R (B) = TP 206 OD PLO, B AA 206 ™ \ A4 Γ AB ^

909886/0909

Symbolic
Notations Storage
content
(Hexadecimal) I. EE Remarks 2929498 Storage
address
(Hexadecimal) LDI F8.
BO I
AC J 68 step
Storage
Job OE VP F8 < EA 200 OF PLO, C A3 B. 60 Set R (C)
= VP 206 10 LDI AD IBl
ibJ 206 11 TR F8 ' 4C 206 12th PLO, D B6 EE Place R (D)
= TR 206 13th LDI AE F7 206 14th VDD 33 206 15th PLO, E IB Set R (E)
= VDD 206 16 SEX, E. 2B "\ Set X = E 206 17th INP 2 B Read AD
H (VDD) 208 18th SEX, A Set X = A 208 19th THE END M (QP) - »OFF
PQ + 1 210 IA INC B TP + 2 210 IB INC B 214 IC LDA, C M (R (C)) - »D
VP + 1 214 ID SEX, E. EX 214 IE SM VP - VDD 212 IF BDF If DF = I
VP = £. VDD 212 20th VPVDD
Comparisons Branches off
VPVDD
Comparisons 212 21st DEC B Decrease
R (B) BY2 after 214 22nd DEC B 212.214 23 212.214

90988B / 090 «

Symbolic
Notations Storage
content
(Hexadecimal) > 4D 2929498 step
Storage
Job 232 Storage
address
(Hexadecimal) DEC C 2C A4 Remarks 212.214 232 24 LDI F8 ' 24 Decrease
R (C) BYl 216 25th 03 03 84 216 26th PLO ₇ 3 A3 3A 216 27 Question
AD 62 (15) 32 Set LC = 3 218 28 LDA, D 23 220 29 PLO, 4th 30th M (TR) - »D,
TR + 1 220 2A DEC, 4 M (TR) - ^ TC 238 2 B GLO, 4 TC - 1 2C BNZ 224 2D TEST 2 TEST TC = O No- »after test 224
LC = 2 2E DEC, 3 Yes, LC-I 2F BR 30th

Check 0 05 (LC = 0)

GLO, 3

XRI

R (3) - «- D

232

226 226

909885/0909

Memory Symbolic memory address Notations Contents

(Hexadecimal) (Hexadecimal)

Remarks

Step memory place

02

BR STRT-I

SEX, A FROM LDA PLO,

BR DECTC

02

30 If LC = 2

226

35 BNZ 3A LC = 2,
Branches off 226 36 DECTC 2 B R-wave test
entry 226 37 BNl 3C No, branches off
R wave input 228 38 DECTC 2 B Test tongue scarf
ter 228 39 B2 35 Yes, after decrease
TC 230 3A DECTC 2 B 230

No, reed switch

01 Branches off after
STRT-I 234 EA Set X = A, QP 234 60 M (QP) - * OFF,
QP + 1 236 4B 236 A4 M (TP) - »TC,
TP + 1 222 30th Branches off after 222 2 B Decrease TC 909885 / 0909

Address Comment Comment / assembler

Language machine language code

AO QP Q REF Al Q PP A2 P PW A3 TR T REF A4 TP SP 5.2V A5 PW 5.2V A6 SP 4.8V A7 PW 4.8V A8 SP 4.4V A9 PW 4.4V AA SP 4V AWAY PW 4V AC SP 3.6V AD PW 3.6V AE SP OV AF PW OV BO VP V5.2 Bl V4.8 B2 V4.4 B3 V4.0 B4 V3.6 B5 V0.0 B6 VDD SP = Measuring period PW = Pulse width

10 60 12 60 12 52 48 44 40 36 00

909885/0909

Figure 5 is a flow chart of the steps which make up the instructions compiled above. The corresponding step for the associated commands can be found under the heading "Step memory location". The program begins with the start step 200 and then proceeds to the step 202, where the loop counter LC formed by the register R (3) is set to zero in accordance with the instruction stored at the memory address 04. As can be seen from Fig. 4A, a refractory state corresponding to the refractory period during which the chamber amplifier 139 is clamped, a measuring or monitoring period during which the electrical chamber activity is detected and evaluated, and a pulse width state, during which the ventricular Stimulus pulse is applied to the ventricle 42 of the patient. The program loops through the steps of FIG. 5 three times for each of the three mentioned states, the loop counter LC being decremented after the completion of each loop to show that the process has proceeded to the next state.

First, the loop counter LC is set to zero in step 204. The process now proceeds to step 206 within whose reference addresses VP, QP, TP and TR defined above are set to their starting points. For example is VP the reference address for the voltage transition point table. In step 206 the register R (C) is set to the first place in

909885/0909

QIl 01 Q21 02 Q31 04

of the transition point table, which specifies the voltages with which the output voltage V of the voltage source 124 is to be compared. The QP reference address for the im Output status table stored in register R (A) indicates the space within the output status table which identifies in which of the states according to FIG. 4A the processor i.e. in the refractory period, the measuring or monitoring period or in the pulsing or pulse width period. The initial status table looks like this:

Refractory state

Measurement or monitoring status Pulse width status

In step 208, the microprocessor 100 then instructs the A / D converter 108 to read out a digital parameter for the supply voltage V. In step 210 the in the microprocessor register R (A) stored output state QP is advanced by one, i.e. brought to the next output state. At this point the register R (A) shows that the process is in the initial refractory period. At step 212, the voltage V is compared to the transition point voltage (VP) derived from that in register R (C) stored pointer is specified for the voltage transition point table. When the voltage V is greater than is the voltage transition point, the process goes to step

909885/0909

Further. If this is not the case, a transition is made to step 214, which contains the pointer VP for the voltage transition point table is advanced by one to indicate the next place in the table and the next lower To obtain the value of the transition point voltage. The reference address TP for the duration table is advanced by two, to identify the next two places within the duration table.

The next value of the voltage transition point is obtained from the voltage transition point table below:

HEX 179 = 5.2V Vl B3 162 = 4.8V V2 A2 145 = 4.4V V3 91 128 = 4.0V V4 8Q 110 = 3.6V V5 6E = 0.0V V6 00

The next group of values for the monitoring duration and the pulse width is obtained from the duration table below:

T21 475 ms) γ ^ 5.2V

T31 800 jjs
T22 475 ms

T32 1000 us' ^s

V α 4.8V

909885/0909

T23
T33 475
1250 ms ν
ps J ^V s ^ 4.4V T 24
T34 475
1550 ms ν
ps J v _s ^ -4.0V T25
T35 600
1850 ms \
psj ^V s - 3.8V T26
T36 600
2300 ms "»
IJS J v _s - 3.6V

As can be seen, there is first a duration for the monitoring period and then the pulse width in two places for a given voltage transition point, i.e. a reference value against which the voltage V is to be compared. The program in this way sets the pulse width of the ventricular stimulation pulse in such a way that a constant energy for the ventricular stimulation pulses is maintained; also the monitoring period increases abruptly when the voltage V of the voltage source 126 drops to the end of the life of the battery for a Slowing down the pace.

In step 214, the voltage transition point is changed from V1 to V2, for example from 5.2 to 4.8 V. Again the If the value of V is compared with the voltage transition point (VP), if it is greater (yes), the program goes to step 216 about where the value "three" entered into the loop counter LC

909886/0909

to indicate that the oscillator is in the refractory period is located. Then the A / D converter 108 is queried, to read out the supply voltage V. In step 220, the value TR of the refractory period stored at location TR is read out and stored in the time counter TC (register R (4)).

Thereafter, the process proceeds to step 222 where the in the time counter (TC) stored value is decreased by one and the timing of a period is initiated to the step to run through until the value stored in the time counter (TC) counts down to zero. Next is the At step 224 a decision is made as to whether the value of the timer counter TC is equal to zero, i.e., the timing function completed is. If not, the process continues to step 226 where a decision is made to determine whether the loop counter LC is at two, which indicates whether the process is in the monitoring state accordingly the RV measurement period. If this is not the case, as is the case here, steps 222, 224, 226 are in sequence after running through until the initial count value (corresponding to the refractory period) which is inserted in the time counter TC, is returned to zero by step 222, which is determined in step 224. This will make the refractory period completed. At this point, step 224 allows the process to proceed to step 232 where the loop counter LC

909885/0909

is decreased by one to indicate that the Process is in the monitoring state, i.e. LC equals two. This returns the process to step 204. At this Position the loop counter LC is not at zero; the Process proceeds to step 234. There the reference address QP for the output status table is advanced by one, while now the process goes to the measurement or monitoring state. Then, during step 236, that becomes from the duration table received value entered into the time counter TC. The reference address (TP) for the duration table is increased by one switched to address the next larger pulse width within the duration table.

Thereafter, the process goes through step 222 to decrease the count entered in the timer TC by one. If the value zero is not reached in step 224, the program goes to step 226. Is the monitoring status if so, the process continues to decision step 228 to determine if a R-wave was applied to multiplexer 106. If within the duration of a single countdown step the R-wave is not detected, the process jumps back, urr. again run a cycle. The counter value corresponding to the monitoring period is reduced in step 222, until the count is equal to zero, which is determined in step 224. If an R-wave is determined in step 228,

909885/0909

the process proceeds to step 230 to check the state of the reed switch 23. If the reed switch is open, the process is reset to t _{Q as shown in} FIG. 4A, ie to step 202, where the loop counter LC is set to zero and the process is started again. The reed switch 23 is a magnetically actuatable switch accommodated within the pacemaker 12. After the implantation, the doctor can operate the reed switch 23 by bringing an external magnet close to the implanted pacemaker 12. This closes the reed switch 23; the asynchronous operating mode is initiated. If the reed switch 23 is closed, indicating that asynchronous operation is to be performed, the process continues by looping with a return to step 222 to again decrease the time count TC even if an R-wave has been detected. In this way the detection of an R-wave is ignored; the pacemaker 12 causes stimulation impulses to be applied in asynchronous operation without a reset taking place when the R-wave is detected.

After the second monitoring period has expired, i.e. when the count value stored in the time counter TC corresponds of the display is counted down to zero in step 224, the process returns to step 232 where the loop counter LC is set back by one. The saved there

909885/0909

Value is now equal to one, which shows that the process goes into its third loop and returns to step 204. Because the count in the loop counter LC is not the same Is zero, the process proceeds to step 234, whereby the Value QP of the initial state is advanced by one, which indicates that the process is now in the pulse width state. Next, in step 236, addressing occurs des and an access to the value of the duration from the Duration table; this value is stored in the time counter TC. The value of the reference address TP for the duration table is advanced by one to the next Place in the duration table in the manner discussed above. At this point the process begins with a sequence of cycles within which the count in the time counter TC is reduced by one in step 222. The count is not equals zero, there is a transition to step 226. Since the process is not in the monitoring period, a return is made, to provide a new decrease in step 222. The process repeats until the count value is in the time counter TC is reduced to zero, a corresponding decision is made by step 224. At this time the process goes back to step 232, within which the loop counter LC urr again. one is reduced so that the value is now zero. The process proceeds to step 204 and starts from the beginning with initialization the values of VP, QP, TP and TR in step 206.

909885/0909

The way in which the Pacemaker 12 is the program stored in memory 102 for the ventricular demand stimulation, in which he successively the refractory period, then the monitoring period and finally go through the pacing or pulse width period before beginning a new cycle. The length the refractory period and the pulse width period is determined by the voltage V of the voltage source 126. These periods in particular the pulse width period, become larger as the voltage V decreases, by the energy content of the ventricular To keep the stimulus pulse essentially constant.

As stated, the memory 102 can be programmed with any of a plurality of operating modes for the stimulation impulses to the heart, the respective program depending optionally on the condition of the patient or also on a change of condition after the implantation of the pacemaker. For example, as shown in FIG. 4B, the pacemaker 12 can operate in an AV sequential mode, with stimulation pulses being supplied to both the chamber 42 and the atrium 40. Chamber activity is monitored after appropriate refractory periods. If a ventricular signal occurs after pacing the ventricle or atrium, the pacemaker is reset. The output and input terminals of pacemaker 12 of FIG. 2 are selected as shown in FIG. 3B. As shown in FIGS. 3B and 4B, the chamber 42 is _{supplied with a pulse immediately before time t Q} by sending a stimulus signal via

909885/0909

the line 19 is applied. After t ~ the chamber measuring amplifier 139 is clamped in that the signal T- is applied to the selector switch 130c. Thereby the input of the amplifier 139 is connected to ground for a first refractory period from t ~ to t. During the first refractory period, the ventricular output capacitor Cy is recharged in that the control signal T ^ w is fed to the selector switch 130a. As a result, the supply voltage V is applied to charge the capacitor Cw. In the period from t to t, the switch 106a ^{1 is closed} by means of a control or clock signal Τς coming from the microprocessor 100. As a result, a ventricular R-wave, if any, is applied through ventricular amplifier 139 and multiplexer 106 to defer microprocessor 100 timing operations.

If no ventricular R-wave was detected at t «, causes the pacemaker 12 that a stimulus pulse on the line 17 goes to the atrium 40. A pulse control signal T ^ ,, through the driver amplifier 134b and a resistor R. the base of an atrial output transistor Q. is applied. Of the Transistor Q. is made conductive so that there is an atrial output capacitor Ci discharges via the atrium 40 and thereby irritates it. Starting with the time t "is the timing signal applied to the selector switch 130c. The input of the chamber amplifier 139 is connected to ground, whereby each signal due to the stimulation of the atrium and

903885/0909

is considered. Beginning at time t-, the atrial output capacitor C. is recharged by supplying the timing signal Tp. In order to close the selector switch 130b and to apply the supply voltage V to the capacitor C. In the period between t 1 and t 1, the chamber activity is again monitored. A timing signal from the microprocessor 100 closes the switch 106a ¹ so that the ventricular R-wave can be applied to the microprocessor 100 via the enabled chamber amplifier 139 and the closed switch 106a ^1. If during this second, from t. until the ventricular R-wave is detected during the monitoring period t 1, the timing period is reset to t 3. Appears within the period from t, to tr no R-wave, a timing pulse T ^,., From the microprocessor 100 via the ventricular driver 134a and the resistor R _v "is applied to make conductive at the chamber output transistor Qw. As a result, the charged capacitor C. is connected to ground. The capacitor Cw discharges. Over line 1? A stimulus pulse is sent to the chamber 42. Typical values for the _{period TA extending from t Q} to t ₂ and the period TV extending from t »to te are given below:

TV (ms) TA (ms)

2000 1700 1000 750

850 700

850 650

750 600

909895/0909

TV (ms) TA (ms)

750 500 650 300 550 425

The A-V follow-up stimulation method of FIG. 4B can, for example can be programmed similarly to "Figure 5, except that the six output states and their corresponding time periods 4B are set by counter values that are stored in memory 102 by a corresponding one Table can be derived. So initially typical values of TV and TA for a specific patient are programmed by there is access to certain places in the corresponding tables, namely to one place for each of the six periods. After a count is entered into the timer, subsequent cycles are performed until the Count value is counted down to zero in order to ensure a corresponding timing of this period.

4C shows the flow diagram of an atrial synchronous, ventricular blocked Pacemaker (ASVIP), in which both ventricular and atrial activity of the heart is detected reset the timing period. Such a mode of operation is typically intended for a younger patient, whose atria beat normally, but whose ventricles may be defective. It is desirable to beat the

909885/0909

Accelerate the atria and thereby stimulate ventricular activity. A sensed atrial P-wave initiates a timing cycle. However, if there is a disturbance in the transmission of this signal to the chamber, the chamber 42 is in any case supplied with a stimulus signal. It is desirable to take advantage of the beating atrial rate to synchronize the pacing of the ventricles, which may be compromised as a result of a myocardial infarction or other defective conduction system. As can be seen from Fig. AC , the cycle begins at time t _Q with the detection of the atrial P-wave. Referring to Figure 4C, a single cycle is divided into six time periods (and states). During the first time period from t «to t1 (as well as during the second and third time periods up to tj) the atrial amplifier 141 is clamped to ground potential by a timing signal; the switch 130d is closed by means of this signal. During the initial period, the released chamber amplifier 139 applies an R-wave signal, possibly coming from chamber 42, via line 1? to switch 106a 'which is closed by means of an RV control signal. If an R-wave signal is detected during the initial period from t _Q to t 1, the time cycle is reset to t ~. In the second or pulsing period from t 1 to t 1, the atrial amplifier 141 remains clamped to ground. The switch 13Od is closed. A timing pulse T ^ y goes through the driver amplifier 134a and the resistor R _v _ to the base of the ventricular output

909885/0901

output transistor Qy. The previously charged ventricular output capacitor Cy is discharged via the transistor Q .., the line 19 and the chamber 42 Switch 130c clamped to ground. A chamber clamping signal TCl is fed to switch 130c. As a result, cardiac activity occurring in the post-ventricular stimulus period is ignored. In the fourth and fifth periods from t- to t-, the ventricular amplifier 141 is enabled so that the atrial P-wave signal can be applied through this amplifier and a closed selector switch 106b 'to reset the timing of the process to t " . A monitoring time signal RA is applied from t to t, by means of which the switch 106b 'is closed. In normal operation, an atrial P-wave signal can be measured during the fourth and fifth time periods from t 1 to te, thereby resetting the timing cycle to zero. If, however, no P-wave is detected, the chamber is again stimulated by applying a control pulse T _wv to the base of the chamber output transistor Qy. As a result, in the manner explained above, a pulse is applied to the chamber 42 of the patient via the line 19.

For example, the ASVIP pacemaker procedure can be similar of Fig. 5, where six periods or output states are defined in a similar manner and where for

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each of the six time periods is catered for by pointing addresses addressed to corresponding tables or formed. This way the values of the periods are varying is entered into a time counter, the count of which is decremented as the process passes through each of the six loops is performed.

FIG. 6 shows a modified embodiment of the adaptable, programmable pacemaker, with corresponding components and circuit stages being denoted by reference numerals similar to those in FIG. 2, but which are in the three hundred series. The microprocessor or the central processing unit (CPU) 300 is coupled to a multiplexer 30ό, whereby one of the inputs 338a, b, e or f is transmitted to the microprocessor 300 via a bus 318 in the form of a flag. Via an address bus 312, the microprocessor optionally addresses a memory 302 which, for example, has a plurality of sections 302-1 to 302-16. According to FIG. 6 , the memory 302 can be designed as a regeneration memory, for example as a memory with direct access, or as a programmable read-only memory (PROM) or as an erasable read-only memory (EROM). The addressed data are read out from the memory 302 and fed to a data bus 310 which connects the memory 302, the microprocessor 300, a decoder 342 and an A / D converter 308 to one another. The A / D converter 308 sets the analog value of the supply voltage V _g

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into a digital form. The signal in question is input to the microprocessor 300 via the data bus 310. It goes without saying that the other analog values, for example the P and R waves, are also converted into digital form and normalized before they are sent to the multiplexer 306. The A / D converter and normalization stages are coupled to multiplexer 306. They are constructed in a manner similar to that explained above and are not shown in FIG. 6. The microprocessor 300 outputs timing signals via an N-bus 352, whereby the decoder is supplied with commands to initiate the decoding of the signals appearing on the data bus 310. Based on the output signal of the microprocessor 300, the decoder selects one of a plurality of switches 1 to 16 within the block 330. Each switch of block 330 is assigned its own latch stage in block 340, which is set by the output signal of decoder 342. The switches are in turn connected to an amplifier and output driver circuit in the manner explained above. In this way, sufficient flexibility is ensured in order to be able to provide a plurality of output circuits which can be coupled to different parts of the heart via lines. In addition, the output driver circuits can be recharged. Access to data at various points on either the heart or other parts of the patient's body is possible. A telemetry system is thus provided for communicating data to or from the programmable pacemaker of FIG.

909888/0809

ORIGINAL fNSPECTED

According to a further feature of the embodiment 6, a self-resetting oscillator circuit 344 is provided to an address counter 307 within the microprocessor 300 to reset. The address counter 307 is incremented for each step processed to the to address the next word location within the memory 302. It has been found that interference signals such as generated by a defibrillation pulse or other source that address counters 307 could cause a address insignificant or defective space within memory 302. As a result, the process would get stuck in a meaningless place. If the address is so affected by interfering signals that it is meaningless Space is addressed, the self-resetting oscillator circuit 344 provides on a regular basis, for example 0.5 s, the address returns to an initial output address for the executed program. If the address counter 307 is operating normally, an output signal is derived from the data bus 310 and applied via a line 346 to the Reset circuit 344 and thereby disable the periodic reset output.

In accordance with a further feature of the invention, the multiplexer 306 has an additional set of inputs 339a to 339a 33? D for the receipt of a binary start address, which is to be entered in the address counter 307, so that each of the

809865/0909

A plurality of blocks 302-1 to 302-16 can be controlled. in the A plurality of pacemaker modes can be stored in memory 302. The storage of each operating mode takes place in a separate block. The associated starting point can be addressed by adding a binary number over the inputs 339a to 339d and an external connection 341 is input, which as explained above, as an RF connection or acoustic connection can be designed.

In addition, self-test programs or data acquisition programs can be stored in certain blocks of the memory 302 be. FIG. 3A shows how, for example, a self-test program can be executed to check the operability of the Chamber measuring amplifier 139 to be checked. Another selector switch 130g can be closed as a function of a test signal T i , which is generated by means of such a self-test program stored in the memory 102, to a reference voltage V r. on the order of 1 mV at the input of the chamber measuring amplifier 139 to be applied. The amplified output signal is in turn via the multiplexer 106 the Microprocessor 300 is supplied, wherein the amplified voltage is compared to a reference value to determine whether the Amplifier 139 works fine. If this is not the case, another output stage and another measuring amplifier can be used be coupled to replace the defective measuring amplifier.

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According to a further operating mode, a program can be stored in one of the blocks of the memory 302 in order to to record and transmit data to the implanted pacemaker via appropriate leads are fed. For example, the leads can be connected to heart tissue, other tissue, or transducers in order to the patient's EKG, pulse rate, pulse width, depolarization time between the atrium and the ventricle, and the like capture. The transmission time of a depolarization signal is considered to be indicative of the state of the heart considered, and it is determined by means of a measurement program, a time window corresponding to a normal transfer duration. If the received signal is outside the limits of such a time window, an indication of this will be given transmitted externally. As part of a data acquisition operation, the latch stages that are assigned to the relevant points of the heart, lines leading to other tissue or transducers are assigned by selective closing of the corresponding Selector switch 330 are coupled individually one after the other, so that the relevant data via the external connection 341 can be transmitted to an external monitoring device.

In addition, an input 338f is provided that connects to the reed switch 23 is connected, which can be closed by means of an external magnet to the operation of the pacemaker to change according to FIG. By opening and closing the

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Switch 23 can generate a sequence of signals; in this way the external connection 341 is enabled Receive or transmit data to or from the pacemaker 12 '. For example, a new address will be in the address counter 307 is entered in order to address the starting position of the next block of the memory 302, whereby another operating mode is carried out.

FIG. 7k shows a more detailed schematic diagram of the blocks of a first embodiment of the device according to FIG. 6. The microprocessor 300 can be, for example, the COSMAC microprocessor of the Radio Corporation of America, which is described in the reference "USER MANUAL FOR THE CDP 1802 COSMAC MICROPROCESSOR (1976) ". The multiplexer 306 has a sequence of sixteen inputs 0 to It can be the multiplexer CD0067 of the RCA. The multiplexer 306 gives an output signal to the A / D converter 308. An embodiment of this converter is described below with reference to FIGS. 8, 9 and 10 explained. The A / D converter is connected to the microprocessor 300 via the data bus 310 and is also connected to a latch circuit 309, whereby one of the sixteen inputs of the multiplexer 306 is selected to supply the A / D converter 308 with analog data. The N timing bus 352 is in the form of a bundle of lines 352a-d; it is connected to the decoder 342, which consists of a plurality of gates CD4012 of the RCA. From-

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outputs from two of the gates are connected via lines 356 to a translation command input and to a tristate output. The conversion command input causes the A / D converter 308 to accept data from the multiplexer 306, while the A / D converter 308 is caused to put the data converted into digital form onto the data bus 310 via the tristate output. In addition, sample pulses 1 and 2 are derived from lines 354a and b; these sampling pulses go to latches 342a and 342b, whereby data applied to the data bus can optionally be fed to one of several switches provided in blocks 330a and 330b, respectively. Blocks 330a and 330b each include four solid-state select switches that provide output signals to selected output driver circuits. In the embodiment illustrated in FIG. 7k , the detected R-wave signal is also fed to the input EF1 of the microprocessor 300, while the reed switch input signal is applied to the input EF2 of the microprocessor 300. In this embodiment, the microprocessor operates as its own multiplexer to selectively gain access to signals applied to these inputs and to respond to these signals in the desired sequence. The microprocessor 300 also provides addresses to the memory 302 via the address bus 312, whereby data can be read out and applied to the data bus 310.

909886/0909

2929438

FIG. 7B shows a detailed schematic circuit diagram of a second embodiment of the pacemaker according to FIG. 6. The components in FIG. 7B are provided with the same reference numerals as corresponding components in FIG. 6, but in the five hundred series. The input signals corresponding to the R-wave, the P-wave and the reed switch output signal are applied to the inputs EF1, EFO and EF2 of the microprocessor 500, which can also be, for example, the microprocessor CDP 1802 of the RCA. In this embodiment, the microprocessor 500 performs multiplexing functions so that one of these values is processed at a time. Typically, such input signals are in analog form; they must be converted to digital form by circuitry summarized in block 508 in dashed lines. The A / D converter has a circuit component CD4508 of the RCA and receives input signals from operational amplifiers 511, to which a reference signal formed by Zener diodes 513 is fed. A clock signal is fed to an input of the converter 515 via a flip-flop 509 and a field effect transistor 517. The memory 502 is connected to outputs of the microprocessor 500 and consists of two blocks manufactured by the RCA under the designation CDP1822S. The microprocessor 500 provides commands via the N-bus to a decoder 542, which may be a chip from the RCA with the designation CD 4514B. The decoder 542 performs decryption functions for the output of the

. 909885/0909

Memory 502 under the influence of the timing signals that are received via the N-bus 552. The output signals of the decoder 542 are applied to two latch stages 540a and 540b, which can each be circuit components of the RCA with the designation CD4508. The decoder 542 selects a latch stage, whereby a corresponding selector switch within the switch groups 530a and 530b is closed. The selector switch groups may consist of integrated circuits manufactured by the RCA under the designation 4066AE .

Figure 8 shows a preferred embodiment of a low power A / D converter 308, as provided in the pacemaker according to FIG. As shown in Fig. 8, one is in digital form Analog voltage V (X) to be converted is applied via an input line 404 to a switch (S,) 407 which, in a first position (on) the analog voltage V (X) to the input (V.) of a voltage-controlled oscillator (VCO) 402, the output of which is connected to the input of an accumulator counter 400. As indicated by the inputs of the counter 400, the Accumulator counter 400 either forwards (up) or backwards (a counting. An output signal of the counter goes via a gate to an input of an N output counter 412. A clock signal is applied via an input line 418 to a control logic 408 and in particular to a circuit 410 dividing by η, by means of the output signal of the S; holder 407 into a

909885/0909

second position (down) can be brought. As a result, a reference voltage is given to the input of the oscillator 402 via a line 406. Simultaneously, a starting command signal passes through a gate 418 'to the starting input of Akkumulatorzählers 400, which then causes a reverse counting. At the same time, an output signal from the control logic also goes to the reset input of the N output counter 412.

The A / D converter 308 of FIG. 8 operates as follows. An unknown one Voltage V (X) is applied to oscillator 402 via switch 407 for a fixed period T. While during this period T, the accumulator counter 400 counts the

up

output signal of the oscillator 402 in the forward direction. In this respect, the accumulator counter 400 works very similarly to a Analog integrator by taking the count of the accumulator counter 400 for a given voltage level of V (X) with linear speed builds up.

The time T depends on the clock frequency, which is supplied via the line 418, the control logic 408 and the circuit 410 will. At the end of the period T, the switch Sl is in the

up

brought the second position to connect the input of the oscillator 402 to the reference voltage E η. Simultaneously with this Switching to the reference voltage, the "A" accumulator counter 400 is switched to counting down. During this Counting down checks an appropriate circuit stage

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when the accumulator counter 400 has counted down to a predetermined counter value, for example zero. The time required to count down the reference voltage to zero is proportional to the mean value of the input voltage V (X). While the accumulator counter 400 is counted down to zero, the clock frequency F.- ,. “ Counted by means of the N output counter 412. Count values occurring in the N output counter 412 are in digital form and are directly proportional to the initially unknown voltage V (X). This leads to a voltage / frequency conversion.

The basic equations for operating the A / D converter 308 are:

r = Km VlXT T (1)
on VCO ^K ' up

^A ab ^{= K} VCO ^E ref ^T X * ² *

Equations (1) and (2) give the up and down count values of the accumulator counter 400 as a function of the unknown voltage and the reference voltage as well as the duration during which this voltage is supplied to the oscillator 402. The up count and down count of the counter 400 are the same because the counter 400 starts at zero and returns to zero at the end of a work cycle. If you put this If both equations are equal to each other, the scale factor falls for the voltage controlled oscillator, i.e. the

909885/0909

This factor has no influence on the output signal of the A / D conversion. Equation (3), which gives the accumulated count N (X) of the output counter as a function of the clock frequency F-. _v and the length of time it takes to bring the accumulator counter back to zero, i.e. Ty, is as follows:

N (X) = T _x F _CLK (3)

Equation (4) showing the count up duration T as a function of the "n" counter and the clock frequency has the following form:

^T up = ^{n / F} CLK

The equation (5) showing that the count value N of the output counter proportional to η and the unknown voltage divided by the reference voltage is:

vixy

N (X) = η (5)

^E ref

Equation (5) shows that the digital output count N (X) is independent of the clock frequency F ~. ,,, the sampling frequency and, which is of particular interest is also independent of the scale factor of the voltage controlled oscillator. For example, if the unknown voltage V (X) is 2 volts, the

909885/0909

Reference voltage is equal to 2 volts and the η counter is at 64 , there is a count of 64 in the output counter N at the end of each conversion. This special property of the A / D converter allows it to work in series with the switch S1 and the voltage-controlled oscillator 402, substantially without affecting the output count. This is true even if the gain changes or differs from unit to unit, provided that the gain remains constant during a conversion cycle. In other words, because a single voltage-controlled oscillator 402 is used in accordance with FIG. 8 to process both the analog input voltage V (X) and the reference voltage E -, the scale factor caused by the oscillator 402 has on the digital output of the counter 412 no influence. Furthermore, because the same clock signal F ^. "Is used to set both the clock for the accumulator counter 400 during the countdown period Τ _χ and the clock for the N output counter 412 during the same period, the frequency of the clock signal Fp. ^ Affects the." digital output of the counter 412, which is indicative of the amplitude of the analog input signal V (X). The delivery of the clock signal F ^. j, clock generators used therefore do not require a high level of accuracy and therefore also do not require a relatively high power consumption. Rather, the clock generator can be designed in such a way that it draws only a minimal amount of power from the energy source, ie the battery of the pacemaker.

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Fig. 10 shows a detailed circuit diagram of the A / D converter 308 of Fig. 8. The input signal becomes a bidirectional switch in the form of the switch 407, the output signal of which goes to the voltage-controlled oscillator, which is in a Phase locked loop circuit is included. The output signal of the voltage-controlled oscillator is fed to the accumulator counter 400, which consists of four up / down counters CD4029A exists. The clock frequency Fp.., Together with the Sampling pulse is applied on lines 418 and 420, respectively, to the output signal of the accumulator counter 400 to set in time to the N output counter 412. A crucial part of the illustrated Embodiment of A / D converter 308 is the Design of the control logic 408, which, according to FIG. 8, has a counter 409 in the form of a 4-bit ring counter. This Counter 409 forces A / D converter 308 to one and only one of four possible modes of operation corresponding to its four Output states 0, 1, 2 and 3. These four modes of operation of the A / D converter 308 of Figure 10 are: (1) wait; (2) preset; (3) count up and (4) count down.

The waiting mode represents an idle state for the A / D converter 308, in which the voltage-controlled oscillator 402 is switched off is, the unknown voltage and the reference voltage are separated from the oscillator 402 via the bidirectional switch S1 and the last converted digital word is in the counter 402 as a digital, parallel 8-bit word. The Um-

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Setter 308 remains in the wait state until it receives a sample pulse which causes the transition to the presetting mode. In the wait state, the A / D converter 308 takes very little Energy on.

The preset operation following the waiting state is used to set the accumulator composed of the counters 400a, 400b and 400c preset to a binary word of one via a fault input. The counter 412 is during this mode of operation deferred. The maximum time available for the presetting is half of a clock period.

During the counting up, the output 3 of the divider becomes 409 brought to logic 1, whereby the accumulator counters 400a, 400b and 400c are forced to count in the forward mode. During this mode of operation, the bidirectional switch Sl gives the unknown analog input signal to the input of the voltage controlled oscillator 402. The n counter 410 begins determine the length of time during which the unknown voltage is applied by setting the reference clock frequency up to the preprogrammed count is counted, which brings the output 9 of an AND circuit 425 to logic 1. During this During the work phase, count values are accumulated in the counters 400a, 400b and 400c. When the output 9 of the AND circuit 425 is on logic 1 jumps, which shows that the count-up period has been reached, outputs 8 and 9 are both at logic 1;

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a command, the ring counter 40? to switch on goes to a Pulse stretching gate 427. When the next clock pulse reaches the value logic 1, the ring counter 40? to the next State changed, which corresponds to the downcounting.

A downward counting operation is effected by the output 7 of the ring counter 40? is brought to logic 1. This condition forces the accumulator counter 400 to count down. In addition, the reference voltage is sent to the voltage controlled oscillator 402 created. The clock frequency is fed to the input of the N counter 412. Therefore, if the counts from the accumulator counters 400a, 400b and 400c are driven out, clock pulses are accumulated in the N counter 412. When the accumulator counter chain is controlled to logic 0 in all states, the output of an AND circuit 429 jumps to logic 1. The Ring counter 40? is via the burst network described above put on hold. Completion of this cycle causes the unknown input voltage V (X) to digitize and held in the output counter 412 with the scale factor discussed above.

The A / D converter 408 according to FIGS. 8 and 10 are particularly suitable for the pacemaker 12 of Fig. 1. It is critical to include circuit components in the pacemaker provide that the pacemaker's energy source, e.g. in the form of the pacemaker battery, has a minimum of power.

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draw. For this purpose, the circuit arrangement according to FIG. 10 can be implemented in CMOS technology. Furthermore, for the purpose of supplying an output signal, the oscillator 402 is supplied with energy only during those time periods during which an analog input signal V (X) has to be digitized. At other times, the voltage controlled oscillator 402 is de-energized. The oscillator 402 is fed under the influence of the control logic 408 and in particular the ring counter 409. In addition, the A / D converter 308 can be set by providing different values of "n" in the counter 410. The A / D converter 308 is therefore suitable for detecting input voltages of varying amplitudes. In the various embodiments of the pacemaker explained above, it is expedient to convert both the relatively high voltage V of the battery and the relatively small voltage signals which are derived from the chamber and the atrium of the patient. According to FIG. 10, the preselected up counting period T is determined by the value “n” which is entered in the “n” counter 410. The value of "n" can be adjusted in accordance with an embodiment of the invention by connecting one of the plurality of outputs Q4, Q5, Q6 and Q7 of the "n" counter 410. A switching stage (not shown) may be provided between one of the outputs of the counter 410 and the AND circuit A9 to subject the value of "n" to the control of the microprocessor 300 as shown in FIG. 7A. In addition, a

909885/0909

ORtGiNAL INSPECTED

known, programmable counter instead of the present one Counter 410 can be provided, which makes it possible to read a binary word stored in the counter under the influence of the microprocessor to vary. The value of "n" can thus be changed depending on which analog input signal should be implemented in digital form. The value "n" is dependent varies on the amplitude of the relevant input voltage V (X), with larger values for "n" for smaller amplitudes are provided. In practice it is desirable to have a count in the output counter 412 which is well known Counter capacity comes close in order to ensure the maximum resolution for an input signal of a given amplitude in this way. A single analog-to-digital converter 308 can in this way vary for different input signals Amplitude can be used, the accuracy of the binary output signal being ensured by varying the value of "n" will. It should be understood that translator 308 is not limited to the particular application described above.

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Claims (41)

PATENT Attorney DlPL-ING. GERHA & D SCHWAN ELFENSTRASSE32 · D-8Q00 MUNICH 83 Ger. P-338 Claims 1. Implantable electronic device which can be coupled to body tissue via a plurality of lines, characterized by a) a memory with at least a first and a second memory section, in each of which a different Program can be stored; b) a controller for the optional implementation of one of the programs stored in the memory with an addressing device, by means of which an access to
one of the memory sections can be produced, and c) a device for optionally changing the address of the addressing device in such a way that by means of the
Addressing another program is addressed and carried out by means of the controller. 909885/0909 TELEPHONE: 089/6012039 CABLE: ELECTRICPATENT MUNICH ORIGINAL INSPECTED 2. Apparatus according to claim 1, characterized in that the ν Control a microprocessor for selective feeding of addresses from the addressing device to the memory for the purpose of controlling the execution of a selected one Program. 3. Apparatus according to claim 2, characterized in that with a reset device for periodically generating a reset signal is coupled to the microprocessor, by means of which the addressing device can be reset to a predetermined return address, such that in the event of inadvertent addressing of a meaningless memory location in the memory, the execution of a selected program in the memory by means of the microprocessor by addressing the predetermined return address within the selected program. 4. Apparatus according to claim 3, characterized in that the microprocessor has a circuit stage coupled to the reset device, by means of which a shutdown command signal can be periodically generated and applied to the reset device in order to prevent the reset device from working when the addressing device is working properly. 909885/0909 ORIGINAL INSPECTED 5. Apparatus according to any one of claims 1 to 4, characterized by a multiplexer which has at least one first and has a second input for receiving an input signal, and with the controller in such a way is coupled that it receives control signals coming from the controller and the input signal of a selected one Input optionally applied to the control. 6. Apparatus according to claim 5, characterized in that at least some of the input signals fed to the multiplexer are analog signals and that an analog-digital converter is coupled to an output of the multiplexer which converts the selected analog input signals into a corresponding digital signal to be applied to the controller . 7. Apparatus according to claim 6, characterized in that a normalizing device is provided for optionally changing the gain of the selected input signal, by means of which the signals fed to the controller can be brought to substantially the same amplitude. 8. Apparatus according to any one of claims 5 to 7, characterized by a first line for connecting the first input of the multiplexer to the heart chamber of the patient and a second line for connecting the second input of the multiplexer to the patient's atrium. 909885/0909 9. Apparatus according to claim 8, characterized in that a supply device is provided for forming and supplying a supply signal to the components of the implanted device and that a third input of the multiplexer is coupled to the supply device in such a way that it receives the supply signal. 10. Device according to one of claims 1 to 9, characterized by one arranged outside the body of the patient Device for transmitting encrypted signals for changing the signals stored in the memory Program. 11. Apparatus according to claim 5, characterized in that the Multiplexer has a third input for receiving an address signal indicative of a The starting position of a selected memory section and its program is to be supplied to the addressing device is, such that the addressing device addresses the start location of the program in the selected the first and second sections of the memory is stored. 909885/0909 12. Apparatus according to claim 11, characterized by a receiver coupled to the address input of the multiplexer and a transmitter arranged outside the patient's body for transmitting encrypted signals to the receiver in such a way that the address signal indicative of the starting point of the selected section within the memory the address input goes. 13. Apparatus according to claim 5, characterized in that with a magnetically operable switch is coupled to a third input of the multiplexer, by means of which the The address of the "addressing device" can be changed in such a way that a program in a different section of the memory is addressed. 14. Device according to one of the preceding claims, characterized in that first and second outputs are provided are that selector switches coupled to a first and a second line arrangement are present and that one of the selector switches can be closed under the influence of the controller. 15. Device according to one of the preceding claims, characterized by first and second output selector switches, which are coupled to a first and a second line arrangement, as well as by the output signal of the 909885/0909 Memory receiving and responsive decoding device for closing a predetermined one of the output select switches. 16. Apparatus according to claim 15, characterized in that with the first and the second switch, a first and a second latch device is coupled, which is responsive to the output signal of the decoder the selected Keeps switch closed. 17. Apparatus according to claim 5, characterized by a power supply for delivering a supply signal for the components of the device, a first and a second Selector switches that can be selectively closed in response to control signals from the controller, and an output circuit, which is coupled via a first lead to a part of the patient's heart in order to selectively To supply stimulus pulses, the first selector switch in response to a first control signal coming from the controller responsively supplies the supply signal to the output circuit, as well as to a second coming from the controller Control signal sent a stimulus pulse over the first line to body tissue. 18. Apparatus according to claim 17, characterized in that the first line is additionally connected to an input of a measuring amplifier is coupled that the input of the measuring amplifier 909885/0909 kers is coupled to a third selector switch that the input signal of the measuring amplifier to one of the Control coming third control signal can optionally be derived to ground and that the measuring amplifier a Having output coupled to a fourth selector switch responsive to a fourth signal from the controller applies the output signal of the measuring amplifier to the multiplexer. 19. Apparatus according to claim 18, characterized in that a decoding device coupled to the output of the memory is provided, which decodes the output signal of the memory receives when a program is executed within a section of memory under the influence of the controller is, and that the decoder is responsive to the memory output signal on the first selector switch first timing signal to be supplied, a second timing signal to be supplied to the second selector switch, a third timing signal to be supplied to the third selection switch and a third timing signal to be supplied to the fourth selection switch supplies fourth timing signal. 20. Implantable cardiac pacemaker, which can be coupled to the heart of a patient via a line arrangement, via which stimulus pulses go to the heart, characterized by 909885/0909 α) a memory with at least a first and a second memory section, in each of which a different Operating mode for stimulating the heart is stored, b) a microprocessor for the optional implementation of a the programs stored in the memory, the addressing device for addressing the program which is stored in a selected memory section of the memory, c) first and second selector switches, each via a line arrangement with a predetermined part of the The patient's heart are connected in such a way that the heart receives stimulation impulses and cardiac activity signals of the relevant part of the heart can be detected, and d) a decoder, responsive to signals derived from the memory, which by executing a selected program are generated in memory by the microprocessor, the decoder a first control signal for closing the first selector switch is generated to during a first period of time to apply a stimulus pulse via the associated lead arrangement and a first part of the heart 909885/0909 to stimulate, and wherein the decoder generates a second control signal, by means of which the second selector switch can be closed for a second different period of time to the on the line arrangement to apply detected cardiac activity signals to be processed by the microprocessor. 21. A pacemaker according to claim 20, characterized by a third and a fourth selector switch, each are coupled to a second part of the patient's heart via a second line arrangement, the decoding device in response to the signals from the memory, a third timing signal applied to the third switch generated in order to give a stimulus pulse to the second part of the heart via the second lead arrangement, and wherein the decoder generates a fourth timing signal which is applied to the fourth selector switch to override the second line arrangement and the closed fourth selector switch to be processed by the microprocessor apply second detected cardiac activity signal. 22. A pacemaker according to claim 21, characterized in that the first line arrangement is coupled to a measuring amplifier, that a fifth selector switch is coupled to the input of the measuring amplifier, that the decoding device generates a fifth timing signal in response to the signals of the memory and that the fifth 909885/0909 Selector switch in response to the fifth timing signal
prevents the measuring amplifier from working. 23. Cardiac pacemaker according to claim 22, characterized by
means for optionally changing the address of the
Addressing device such that the addressing device has a starting position in another of the first and
second memory sections addressed and a stimulus
of the heart takes place according to a different mode of operation. 24. A pacemaker according to claim 20, characterized in that a multiplexer equipped with several inputs is provided which has at least one first input coupled to the second switch and a second input coupled to the second selector switch and which is responsive to the control signals of the microprocessor multiple inputs for processing
selected by the microprocessor. 25. Cardiac pacemaker according to claim 20, characterized by
a power source, a third selector switch and an output circuit coupled to the first line arrangement for delivering a stimulus pulse via the first line arrangement to the first part of the heart, the decoder being responsive to signals from the memory 909885/0909 third timing signal generated for a third, prior to the first period of time and wherein the third Selector switch responsive to the third timing signal of the decoder to the supply signal Power supply of the output circuit couples. 26. A pacemaker according to claim 25, characterized by a driver amplifier for applying the first timing signal to the output circuit, such that the output circuit supplied with current during the third period of time emits a stimulus pulse to the heart via the first line arrangement during the first period of time. 27. Implantable electrical stimulation device, characterized by a) at least one first and one second output selector switch device, which are coupled to at least a first and a second line arrangement, of which at least the first line arrangement is attachable to body tissue; b) a multiplexer with at least a first and a second input, by means of which on the basis of control signals Signals fed to one of the first and second inputs optionally to an output of the multiplexer are applicable; 909885/0909 c) a control provided with a control processor and a memory, the memory at least one first and second memory sections each having a starting address and different ones stores first or second programs, and the control is equipped with: (1) a first supported by a program stored in the first memory section Device by means of which, in a first operating mode, a device to be supplied to the patient's tissue Stimulus can be generated, and (2) a program supported by means of a second program stored in the second memory section second device, by means of which, in a second operating mode, a tissue des The stimulation pulse to be supplied to the patient can be generated, and d) a device for selectively changing the address of the addressing device in such a way that it is a start address to one of the first and second memory sections for the purpose of carrying out the associated program and stimulating the patient's tissue in the appropriate Operating mode there. 909885/0909 28. Stimulation current device according to claim 27, characterized in that the memory has a third memory section for receiving a program for selectively acquiring data appearing on one of the lines, and that the control is additionally equipped with a device suitable for carrying out the third program for an optional Closing the selector switch device assigned to a line arrangement for the purpose of transmitting data to the control. 29. Stimulation current device according to claim 27, characterized in that the controller has a third device for forming a first period which corresponds to the pulse width of the stimulus signal to be applied to the patient's tissue, and a third device for forming a pulse interval between the stimulus pulse trains. 30. Stimulation current device according to claim 29, characterized by a device for reprogramming the memory in such a way that the values for the pulse width and the pulse interval predetermined by the first and second devices can be changed. 31. Stimulation current device according to claim 27, characterized by a device for reprogramming the in the first and / or in the second memory section stored programs 909885/0909 grams in such a way that the type of stimulus pulse supply for the patient's tissue can be changed. 32. Stimulation current device according to claim 27, characterized in that the first device has a circuit stage for setting the first operating mode for stimulating the Has tissue, in turn with means for specifying a first refractory period, a second measurement period 'and a third pulsing period. 33. Stimulation current device according to claim 32, characterized by a device for changing the first program for the purpose of changing the lengths of the first, second and third periods of the first device. 34. Stimulation current device according to claim 33, characterized in that in the second memory section a program for the application of stimulus pulses of the tissue can be stored in the second operating mode, which is different from the first operating mode is, and that a device for specifying a first period for the detection of a coming from a first tissue Signal and a first signal period for detecting a second signal from a second different tissue provided is. 909885/0909 35. Stimulation current device according to claim 32, characterized in that the second device has a circuit stage for setting an eTth period corresponding to the pulse width of the stimulus pulse supplied to a first tissue part, a second rest period and a subsequent third period which is the pulse width of a stimulus pulse for a second tissue part corresponds, and that by means of the means for changing the address a change of from the addressing device applied to the memory start address space can be brought about such that a Access to a starting location in one of the first and second memory sections in order to carry out the corresponding one Program is possible. 36. Device for converting analog input signals into corresponding digital output signals, characterized by a) an oscillator with an input for supplying a first output signal, the frequency of which is different from his Depends on the input signal, b) a reference device for generating a reference signal, 909885/0909 c) a switch coupled to the input of the oscillator, which switch from a first position in which it feeds the analog input signals to the input of the oscillator, can be brought into a second position, in which it feeds the reference signal to the input of the oscillator, d) a first one which receives the first output signal Counter that corresponds to the frequency of the first output signal with the formation of a second output signal counts up in a first operating mode and counts down in a second operating mode, e) a second counter optionally receiving the second output signal to form a corresponding one third digital output signal, f) a clock generator for supplying a clock signal and g) a control receiving the clock signal for supplying a control signal after receipt of a selected one Number (n) of oscillations of the clock signal, the switch being responsive to the control signal from the first goes into the second position, the first counter responding to the control signal to operate ended in the first mode, so to this 909885/0909 Time, the first output signal has a first count value characterizing the analog input signal represents, and the first counter with the second mode of operation begins to operate from the first count value off to count down, further comprising the second counter in response to the counting signal in response to the control signal the oscillations of the clock signal begins and the second output signal with a second predetermined Counting value responsive to the counting of the oscillations of the clock signal with formation of the third digital Output signal ended, which is characteristic of the analog input signal and independent of the frequency of the clock signal. 37. Apparatus according to claim 36, characterized in that the controller has a third counter which counts (n) oscillations of the clock signal and then emits the control signal and which is provided with a device for a changeable setting of the value of (n) . 38. Apparatus according to claim 37, characterized in that the third counter has a device for receiving and storing a characteristic value for (n). 39. Apparatus according to claim 36, characterized in that the controller has a device which is directed to the 909885/0909 Presence of an analog input signal to be converted, characterizing the sampling signal corresponding to the oscillator activated for a period of time equal to the amount of time required to turn the first counter to work in the first and the second operating mode to convert the analog input signals into the corresponding to implement third digital output signals. 40. Apparatus according to claim 39, characterized in that a ring counter with a first output, which is characteristic for the period of time within which the oscillator is deactivated, a second output which is characteristic is provided for the first mode of operation of the first counter and a third output, which is indicative of is the second mode of operation of the first counter. 41. The device according to claim 36, characterized in that the device parts are designed as CMOS components. 909885/0909