DE2929498C2 - - Google Patents

Abstract

A multi-mode pacemaker includes a microprocessor 100 and a memory 102 programmable with a variety of processes for stimulating a heart and/or a sensing and transmitting to an external device conditions of the heart or pacemaker. The microprocessor controls a multiplexer 106 to input via a scaling amplifier and a/d converter 108 signals from atrial and ventricular leads 17, 19, the power source 126, a reed switch 23 operable by an external magnet, or redundant leads on lines 138d,e. The output comprises latch drivers 134 a-d with respective output select switches 130 a-d selectively operable to supply stimulation pulses to the leads or allow sensing. External apparatus 104 may transmit coded information to change the stored program or operation of the reed switch may select a different program starting address. Pulse width, rate and amplitude may be controlled in response to sensed heart activity or power source level and different pacing modes (demand, asynchronous, etc.) or multi-site pacing to disrupt arrhythmias may be selected automatically or externally. In an aid converter 308 (Figure 8), counter 400 counts up the output of VCO 402 controlled by unknown signal V(X) and then counts down to zero the output of VCO 402 then controlled by reference EREF and during such countdown a counter 412 counts clock pulses so that when counter 400 reaches zero the output of counter 412 depends on V(X) but not on the scale factor of VCO 402. <IMAGE>

Description

The invention relates to a microprocessor-controlled implantable pacemaker, which can be coupled via a line arrangement with body tissue to be stimulated.

A well-known pacemaker of this type (DE-OS 27 38 871) is the output side via a single output line to connect to the heart. The microprocessor is a read-only memory whose memory contents on the one hand the stimulus pulse width and on the other hand, the stimulus pulse interval for asynchronous, fixed-frequency stimulation operation pretends.

Furthermore, an implantable with the heart via a single line is implantable Cardiac pacemaker known (DE-OS 27 55 702), which is normally in demand mode with a predetermined one of several different pulse repetition frequencies is working. By pressing a magnetic tongue switch group can be the charging current of a follower frequency determining capacitor change to this way to select another of the available pulse repetition frequencies. About the Tongue switch group can also be switched to an asynchronous operation.

It is also known ("cottage" of the engineer paperback, 28th edition, volume IVB, electrical engineering, Part B, 1962, pages 1062 and 1063), interference of shortwave telegraphy reception in that a shortwave receiver in such a way with multiple antennas works together, that he automatically to the antenna with the best reception is turned on while the other antennas remain ineffective.

Finally, a catheter is used to stimulate the heart in the chamber and in the atrium (US-PS 38 25 015), which isolated for the atrial irritation with several mutually electrical lines is provided, each of which has its own ring electrode connected. These electrodes are spaced apart on the catheter part arranged, which comes to rest during implantation in the forecourt. It will be some of the atrial ring electrodes have better contact with the atrial tissue than make other of these electrodes. These contacts are determined by following the Inserting the catheter into the heart, but before its permanent connection with the associated pacemaker different line pairs are tested by the doctor. The most favorable lines or cable combinations are selected and then permanently connected to the pacemaker.

The invention is based on the object, a microprocessor-controlled pacemaker  to specify the type specified in the preamble of claim 1, the automatically the most favorable mode of operation and the associated interconnections brought about and the case with little circuit complexity with as little energy gets along.

This object is achieved in that the conduit arrangement more Having lines or line combinations that the same and / or different Sites of body tissue are connected that one of the microprocessor provided with associated memory controlled evaluation is the input side via a controlled by the microprocessor multiplexer and on the output side via a likewise controlled by the microprocessor selector device connected to the line arrangement is that the evaluation device so is constructed and programmed to be based on in the course of pacemaker operation detected characteristic determines which line or line combination for the implementation of the respective stimulation and / or measuring task most suitable is, and by appropriate control by the microprocessor over the Selector switch automatically the line or line combination on the one hand for the transmission of input signals from the body tissue to the evaluation device and on the other hand, for the transmission of stimulus pulses to the body tissue makes and that between the multiplexer and the microprocessor all multiplexer analog input signals common combined normalization amplifier and A / D converter is switched.

In the pacemaker according to the invention can automatically detected defective lines and be bridged; it can be for a redundant data acquisition and / or Stimulation impulse be taken care of. You can select the line that the most favorable threshold value for the acquisition of measured values and / or stimulus impulse exposure Has. It may also be transitioned from a unipolar electrode to a bipolar electrode become. Due to the detected signals can also automatically the most favorable Pacemaker mode are selected. To these selectable operating modes preferably include ventricular demand stimulation, asynchronous ventricular pacing, a bifocal stimulation, atrial-synchronous, chamber-locked stimulation (ASVIP), a change in the pulse width as a function of the supply voltage, a stimulation with automatic threshold tracking, in which the Pulse width of the pacemaker pulse is set to the minimum value that still leads to cardiac entrapment, and a cardiac stimulation in several places for interruption of arrhythmias. In the memory can also programs to carry out  stored by telemetry functions. These include in particular the Capture of various cardiac activities or other bodily functions as well the transmission of data concerning the operation of the pacemaker, such as characteristic values for the respective pulse width, the pulse amplitude, the pulse break, current and Voltage of the power source, the moisture content within the pacemaker, the Pacemaker lead impedance and pacemaker self-test programs.

The multiplexer allows, one after the other, individually for the cardiac activity of the patient Patient characterizing signals, eg. B. atrial and ventricular activity signals, or for other body conditions or conditions, such as the humidity within the pacemaker, then apply these signals from the microprocessor are processed. The combined normalization amplifier and A / D converter converts the analog multiplexer input signals, which vary in their amplitude considerably from each other into a digitized signal of suitable size for processing in the microprocessor. A single normalization amplifier is enough and A / D converter, reducing the circuitry and power consumption kept small.

Preferred further embodiments of the invention will become apparent from the dependent claims.

Preferred embodiments of the invention are described with reference to the accompanying drawings explained in more detail. It shows

To Fig. 1 is a schematic representation of an implanted, programmable, microprocessor-controlled pacemaker, transferred to and from the signals to modify the processing performed by the implanted pacemaker program in line and to the activity of the heart (or other tissue) characteristic signals to play an external monitor,

FIG. 2 is a functional block diagram of the implanted pacemaker of FIG. 1; FIG.

FIG. 3A is a circuit diagram of the pacing circuitry of the pacemaker of FIG. 2 to the patient's heart for pacing and sensing in ventricular demand mode . FIG.

FIG. 3B is a circuit diagram of the connections leading from the pacemaker of FIG. 2 to the patient's heart for atrial and ventricular AV sequencing . FIG.

Fig. 3C is a circuit diagram of the connection between the pacemaker of FIG. 2 and the atrium and the chamber for carrying out an atrial synchronous, chamber locked stimulation (ASVIP)

FIG. 4A is a flow diagram for the switch and the components of the circuit arrangement of FIG. 3A for carrying out a chamber demand pacing,

FIG. 4B is a flow chart for the operation of the switches and of the components of Fig. 3B for carrying out a bifocal pacing,

FIG. 4C is a flowchart for actuating the switches and components of FIG. 3C to perform ASVIP pacing . FIG.

Fig. 5 is a flow diagram for one of several in the memory of the pacemaker of FIG. 2 einzuspeichernden programs for performing a chamber demand pacing according to the flowchart of Fig. 4A,

6 is a functional block diagram of another embodiment of the pacemaker according to the invention;

FIGS. 7A and B are circuit diagrams of two embodiments of the pacemaker of FIG. 6,

Fig. 8 is a functional block diagram of the provided in the pacemaker of Figs. 6 and 7 A / D converter,

Fig. 9 is a graph for explaining the operation of the up / down counter of Fig. 8, and

Fig. 10 is a circuit diagram of the A / D converter according to Fig. 8.

Fig. 1 shows a pacemaker which can be programmed into a plurality of modes so that the patient's heart, whose atrium is indicated at 40 and its chamber at 42 , can be imparted with stimuli in various ways. In addition, the electrical activity of the atrium and ventricle or other body tissue is sensed to either modify the pacemaker working parameters or to remotely transmit corresponding signals out of the patient's body 14 .

The pacemaker 12 includes a body tissue and fluid resistant housing 13 , a first conduit 17 coupled to the atrium 40 and attached thereto via an electrode, and a second conduit 19 in communication with and adjacent the chamber 42 is determined via an electrode. An external transmitter 10 communicates via a line 15 with a coil or antenna 16 located outside the body 14 of the patient to transmit signals to the implanted pacemaker 12 via an RF link. A monitor 63 is connected to the transmitter 10 via a line 59 . The transmitter 10 may be caused to transmit via the line 15 and the antenna 16 signals to the implanted pacemaker 12 to transition it from one mode to a selected other mode. In this way, according to a changed condition of the patient, the physician can prescribe the manner in which stimulation pulses are supplied to the heart of the patient. It is understood that at the time of surgical implantation of the pacemaker 12 in the body 14, a particular type of stimulation may be desired. After implantation, the condition of the patient may change. Another mode may then be desired. In addition, there is a desire to transmit from the patient's body a series of signals indicative of various detected conditions passing through the antenna 16 and the transmitter 10 to be displayed on the monitor 63 . The implanted pacemaker 12 may further comprise, as shown in FIG. 1, another output and a line 25 coupled to a transducer 27 . The transducer 27 may be a mechanical transducer that detects movement of a body organ. Furthermore, the pacemaker 12 may be provided with an additional output and a lead 21 which is connected to a magnetically actuated tongue switch 23 which can be actuated by the physician by bringing an external magnet in proximity to the switch To close the switch 23 and cause a change in the operation of the pacemaker 12 . A lead 29 is representative of a plurality of leads that may be coupled to various locations of the heart, for example to provide stimulation that suppresses arrhythmia, or to provide redundant leads that may replace a defective lead 17 or 19 .

Fig. 2 shows a functional block diagram of the pacemaker 12 having as a central control a microprocessor 100 and a multiplexer 106 to receive analog data from a first input 138 a, via the first line 19 ( Fig. 1) with the ventricle 42 is coupled, and a second input 138 b come, which is connected via the second line 17 with the atrium 40 ( Fig. 1) in combination. The various analog (and digital) inputs are selected in a predetermined manner by the multiplexer 106 under the influence of the microprocessor 100 and processed according to the processes or programs stored in a memory 102 .

The microprocessor 100 is connected to the memory 102 via an address bus 112 so that stored addresses, indexed by an address counter 107 , are applied to address selected locations within the memory 102 . The addressed data is transferred from the memory 102 via a data bus 110 into the microprocessor 100 .

Multiplexer 106 has additional inputs 138c , d, e and f. The microprocessor 100 provides control signals to the multiplexer 106 via an input selector bus 120 selecting one of the inputs 138 to f to apply that signal to the microprocessor via a line 118 , a normalization amplifier and analog to digital converter stage 108, and a bus 114 To give 100 As is apparent from Fig. 2, the output voltage V _{s of} a voltage source 126 is applied via the input 138 c to the multiplexer 106 in order to modify the pacemaker operating behavior in response to changes in the voltage source in a suitable manner. For example, it is desirable to increase the stimulus pulse width as the supply voltage decreases to provide a pulse of more or less constant energy; it may also be desirable to decrease the pacing rate as the supply voltage decreases to indicate that the pacemaker needs to be replaced or a modification made via external programming. For example, reserve inputs 138d and 138e may also be coupled to chamber 42 and atrium 40 to redundantly monitor the activities of these areas of the heart. The design may be such that the microprocessor selects which of the inputs 138a , b, d and e provides the most effective detection of the atrial and ventricular signals or requires the lowest energy from the voltage source 126 or most effectively interrupts cardiac arrhythmia. The input 138 f may be connected via the line 21 with the reed switch 23 . Then, when the doctor places an external magnet so that the switch 23 closes, the microprocessor 100 is caused to change or change the program stored in the memory 102 . The multiplexer selects or sequentially controls one of the inputs 138a- f to connect the respective input to the microprocessor 100 via the line 118 , the stage 108, and the bus 114 . Multiplexing is provided to reduce the circuitry overhead for processing the analog information fed to inputs 138a- f and to further reduce the power requirements for that function. Without the multiplexer 106 , a separate normalization amplifier and A / D converter stage 108 would have to be provided for each of the inputs 138 a to f. As a result, the use of the multiplexer 106 reduces the current drain from the voltage source 126 ; At the same time, this reduces the circuit complexity for the pacemaker 12 .

The microprocessor 100 applies a normalization control signal to the normalization amplifier and A / D converter stage 108 via a line 116 . This affects the gain of the amplifier 108 forming part of the stage 108 to accommodate the different amplitudes of the signals going to the inputs 138a- f of the multiplexer 106. *** " For example, the output voltage of voltage source 126 may be on the order of 1.3 to 6 volts (initially), while the cardiac activity signals derived from atrial 40 and chamber 42 may have a voltage of the order of 1 to 20 millivolts, for example. The output of the amplifier and A / D converter stage 108 is a sequence of digital signals which are stored in the microprocessor 100 , specifically in the registers of the microprocessor 100 . According to a preferred embodiment of the invention, the microprocessor 100 is implemented in CMOS technology with a low threshold, which ensures a relatively low current drain from the voltage source 126 .

An essential component of the pacemaker 12 is the memory 102 , which can expediently have a read-only memory (ROM) 102 a and a memory part 102 b with direct access (RAM). The basic memory part 102 a stores the basic steps of each of a plurality of pacing modes (or other processes). On the other hand, a plurality of parameters or complete programs in the RAM portion 102 b stored; this part can be reprogrammed at a later time depending on the changing condition of the patient. The memory 102 may be programmed at the time of manufacture, prior to implantation in the patient's body 14, or via an external storage loading interface 104 coupled to the memory 102 via a RF link or connection 105 . As interface 104 , known devices (US-PS 38 33 005 and US-PS 40 66 086) can be used. In this connection, for example, a receiver filter may be provided which detects sequences of RF pulses transmitted by an external transmitter and which are encrypted such that a program stored in the memory 102 is reprogrammed or alternatively a parameter is changed is stored in a memory location of the memory 102 .

Therefore, if after the implantation of the pacemaker 12 in the body 14 of the patient, the physician observes a change in the patient's condition, the program or special variables of a program stored in the RAM portion 102 b may be reprogrammed to provide for pacing of the heart which is best suited for the changed condition. In the context of the stimulation, various parameters occur, such as the pulse width of the stimulus pulse, the rate or frequency of the pulse delivery, the time between the application of a pulse signal and the detection of the resulting cardiac activity, during which the measuring device is rendered ineffective, and the pulse amplitude. Typically, each of these parameters is determined, for example, in the form of an 8-bit word which is stored in a word location of the RAM portion 102 b of the memory 102 . Thus, if it is desired to change the pulse width, the physician need only enter a new 8-bit word via the interface 104 and link 105 into a known addressable word space within the RAM portion 102 b, which is indicative of the new one Pulse width is to work with the pacemaker 12 . A new type of stimulation may be programmed into the RAM part 102 b also by the respective steps of the new process are input via the interface 104th Alternatively, a mode change may be effected by inputting the initial location of the desired program from the RAM portion 102b to the address counter 107 of the microprocessor 100 to initiate the addressing of the next program within the ROM portion 102a of the memory 102 . For example, if the initial mode of operation of the pacemaker 12 is a ventricular pacing and it is found desirable to post AV follow-up stimulation, the physician enters the new start-up address for the AV Follow-Up type of interface via the interface 104 to gain access to another portion of the ROM Part 102 a, whereby the microprocessor 100 starts to operate in the next mode.

As will be explained in more detail below, it is expedient to keep the energy of each stimulus pulse supplied to the patient's heart constant, even if the voltage level of the energy source 126 , for example a battery, decreases over time. Referring to FIG. 2, the multiplexer 106 periodically applies the battery voltage V _s to the microprocessor 100 via the input 138c , which under the influence of a program stored in the memory 102 compares the measured voltage with various predetermined voltages present in the ROM portion 102 a or the RAM part 102 b are stored. In this way, an adjustment of the pulse width of the stimulus pulse in order to keep the energy content, ie the area below the stimulus pulse curve, substantially constant.

The memory 102 may be loaded with a program that makes a self-selection. In other words, such a program may be responsive to cardiac signals which are applied to the inputs a and b 138, to determine the condition of the heart and to select a function of the detected state is one of several programs. The distinguishing characteristics of the input signals due to the atrial P-wave and the ventricular R-wave are described in the publication "Electrocardiac Electrograms and Pacemaker Sensing" by P. Hoezler, V. de Caprio and S. Furman in "Medical Instrumentation" Volume 10, No , 4, July / August 1976, discussed in detail. The criteria by means of which these heart signals are to be recognized and compared are stored in the memory 102 . If a change is detected, the microprocessor may automatically select another pacing mode suitable for the changed conditions of the patient's heart without requiring external intervention by a physician via the external memory loading interface 104 .

In accordance with another mode of operation, the memory 102 of the pacemaker 12 may be programmed to function as an automatic threshold post-arrhythmia, whereby the energy of the pacing pulses applied to the chamber 42 (or atrial 40 ) may be progressively lowered until no more entrainment occurs, ie until the stimulus pulses no longer trigger a chamber contraction which is manifested by an R-wave detected within a measuring or monitoring period. In this mode, when the R-wave is detected within the measurement period, a control signal is generated on the basis of which the pulse energy is lowered by a predetermined amount. This is preferably done by decreasing the pulse width until no pacing R-wave is detected. Then the program increases the pulse width until the R-wave reappears. In this way, the removal of energy from the voltage source 126 is minimized because the pulse width is set to a value just sufficient to sustain the entrainment of the heart.

The control output signals of the microprocessor are applied in the circuit design of Fig. 2 via lines 131 to latches 134 and via a bus 132 to corresponding selector switch 130 , which suitably in accordance with the memory 102 stored processes pacemaker pulses via the lines 17 and 19 (or 29 ) enter the atrium 40 and / or the chamber 42 of the heart. The line 131 a to a first chamber or driver (or amplifier) 134 a is coupled, in turn, is connected to its own group of bipolar / unipolar select switches 130 a. The driver amplifiers 134 b, c and d are each assigned a corresponding group of selector switches. For example, the output of the driver 134 b is connected to selectors 130 b to drive the forecourt via conductors 17 a, 17 b and 17 c. The drivers 134 a to 134 d can voltage boosting levels, z. Voltage doubler or threefold, to raise the output voltage level to the level necessary to effectively stimulate the heart tissue at a predetermined voltage of the energy source. The selector switch 130 are controlled by means of signals coming from the microprocessor via the bus 132 to either the output of the first driver 134 a to predetermined ones of the outputs 19 a, 19 b and 19 c apply. The switches 130 are connected to the ventricular lead 19 , which may be formed in a known manner (US-PS 40 10 758) as a coaxial line, which may be connected via the conductor 19 a with a tip electrode and the conductor 19 c with a ring electrode , In addition, a conductor 19 b is present, which is connected to a plate, which is formed by the metal container or housing 13 , within which the pacemaker 12 is housed. During normal bipolar operation, the selector 130 can be the negative and positive stimulus pulses via the conductors 19 a and 19 c of the coaxial line to the tip electrode and the ring electrode arrive. If it is desired to carry out the stimulus impingement in conventional unipolar operation, a negative voltage is applied via the conductor 19 a to the tip electrode, while a positive voltage through the conductor 19 b goes to the plate. The ring electrode is not connected.

It is not only desirable to be able to operate in bipolar or unipolar operation, but also to provide a pacemaker insensitive to perturbation in the event of detection of defective conduction due to improper connection of an electrode lead to the heart tissue or to breakage or damage One line of microprocessor 100 provides appropriate control signals over bus 132 to selector switches 130 , thereby selectively coupling another combination of lines (or conductors within the lines) to supply the pacing pulses to chamber 42 . The selector switch 130 may for example be arranged so that the conductors 19 a and 19 c can be interconnected. Alternatively, the selector switch 130 is selectively closed so that cardiac pulses between the conductor 19 a or the conductor 19 b and the conductor 19 c are applied. If one of the conductors 19 a or 19 b fails, then the other can readily take its place to continue to supply the pulse to the heart in two places.

The failure of one of the lines 17 or 19 can be determined by loss of capture, ie the fact that no heart activity signal appears at the input 138 b after the impulse is applied to the ventricle. Alternatively, the measurement of a high impedance between the conductors 19 a and 19 b of the coaxial line 19 indicates a line failure due to the formation of scar tissue between the tip or ring electrode and the ventricle 42 or the breakage of one of the conductors can be. Upon detecting such failure, the microprocessor 100 selects another process or other program stored in memory 102 to supply signals to selector switch 130 and cause re-connection of line 19 (or 29 ) in the manner described above.

To be an output signal of the microprocessor goes to a second or atrial drive amplifier 134 b whose output is connected to another set of selector switches 130 to a corresponding group of conductors or wires 17 to the atrium 40 of the patient (Fig. 1) is coupled , Furthermore, backup amplifiers 134 c and 134 d are present, receive the output signals of the microprocessor 100 and are connected to other groups of selectors 130 . Such groups of selectors 130 may be connected to the patient's heart via redundant lines. For example, the outputs of the amplifiers 134c and 134d may also be connected in redundant fashion to the chamber 42 and the vestibule 40 . If one of the leads 19 or 17 should break or the resistance between the associated electrode and the heart becomes excessively high, a redundant lead between the microprocessor 100 and the heart may be turned on by appropriate actuation of the respective selector switch group 130 . In order to measure the impedance of one of the lines 17 and 19 , the line in question is connected to an output stage, which is explained in connection with FIG. 3 and which has a charging capacitor. The charging time of this capacitor is indicative of the impedance formed by the associated line. During operation, the output capacitor is charged. After charging, the output stage is actuated to cause a discharge of the capacitor. This will give a stimulus pulse to the heart via the associated lead. The time required for charging the output capacitor can be determined in time by a counter of the memory 102 is started via a program. The counting is continued until the charging voltage at the output capacitor reaches a predetermined value. The voltage level of the capacitor is repeatedly measured under the influence of the microprocessor 100 ; if the predetermined level is not exceeded, the counting is continued. When the charging voltage of the capacitor has reached the predetermined value, the counting stops; the relevant count value is used as a characteristic for the impedance of the line. When the line is broken, the line impedance is high, resulting in a longer charging time. On the other hand, if there is a short circuit in the line, the charging time is relatively short. First and second time limits are specified to determine if the line is shorted or if the line impedance is too high due to a line break. In any case, these limits, which take the form of time counts, are checked; if they are exceeded or fallen short of, the defective line is replaced by a redundant second line.

The reserve drivers 134c and d may be provided to provide for stimulation at several different locations, e.g. B. five points, in order to interrupt arrhythmias in this way, the pacemaker 12 detects if necessary. Alternatively, such additional driver 134 c and d use in order to eliminate a bias voltage on the lines 17 and 19 after the Reizimpulsbeaufschlagung, or to charge the output capacitor rapidly in the case of operating at a high frequency pacemakers. Arrhythmias can be detected by measuring the time delay between the electrical activity of a first site of the heart, e.g. B. the atrium and the detection of cardiac activity at a second location, eg. B. the ventricle is measured. If the delay falls short of a predetermined period of time, for example 100 to 200 ms, this is an indication of a possible arrhythmia. Arrhythmias are primarily caused by the appearance of a second competing ectopic focus in the patient's heart that competes with the primary focus, which typically appears in the atrium. The two beating centers compete with each other to form an arrhythmia, which makes the heart activity erratic and blood is no longer effectively pumped. According to an expedient embodiment, a plurality of electrodes, each of which is connected to a driver amplifier 134 and a selector switch 130, are coupled to a corresponding number of selected locations of the patient's heart. Such a lead is selected to deliver stimulus pulses to the heart, while the remainder of the leads detect the resulting cardiac activity at the other sites. By means of a program stored in the memory 102 , time windows are specified for each of the four lines within which cardiac activity signals are received. If the signals do not appear within the respective time window, this is an indication of a possible arrhythmia. If a detected signal does not occur within its assigned time window, another of the multiple lines is selected to supply the stimulus pulses. The remaining lines detect the resulting cardiac activity signals. If the detected signals do not appear in the associated time windows after the new stimulus line has been selected, another line is again determined. In this way, if the arrhythmia is not controlled, the program is designed to deliver stimulus to all leads in order to control cardiac activity. The durations within which the cardiac activity signals are to be received are predetermined, as explained below in connection with FIGS. 4 and 5.

The pacemaker 12 in this way forms a highly flexible and adaptive device that allows to correct or compensate for a variety of factors. These include difficulties in the detection of measured values, temporal fluctuations in the voltage delivered by the energy source and unforeseen interference signal sources. For example, processes or programs are entered into the memory to detect the R-waves based on major features such as the slope of the ECG signal, the R-wave pulse width from the ventricle 42 , the amplitude of the R-wave, the similarity of the R-wave. Wave with a previous ECG complex and the like. In addition, the memory 102 is programmed to ignore external AC sources of interference or neglect or filter out nonessential muscle signals. The advantages of such an adaptive pacemaker 12 are that a single pacemaker can be provided which is programmable according to a variety of operations and which can be constantly reprogrammed as technology changes. From the manufacturer's point of view, it is no longer necessary to modify any hardwired circuit to develop separate hybrid circuits which differ from one another by relatively minor features, such as a change in input filter, pulse width or pulse frequency. Another advantage of the pacemaker 12 of Figure 2 is that it eliminates a major source of error in known hardwired pacemakers, namely, the frequency and pulse width determining timer capacitors. Currently, hard-wired pacemakers use RC charging to perform the desired timing functions, such as to determine the pulse width, pulse frequency, and refractory duration. Experience teaches that capacitors in such circuits can be a major cause of failure.

As shown in Fig. 2, each of the drivers 134 is connected to its own group of selectors 130 , whereby a stimulus pulse is applied to one of the leads 17 or 19 to a corresponding part of the heart. In addition, the multiplexer 106 applies a select signal derived from the chamber 42 and the atrium 40 via the lines 19 and 17 to the microprocessor 100 . Fig. 3A shows an exemplary embodiment of the arrangement of the driver amplifiers 134 and the selector switch 130 for supplying the stimulation pulses via the line 19 to the ventricle 42 in order to provide a chamber demand stimulation. The relevant timing intervals are illustrated in FIG. 4A. The pacemaker output stage consists of an output transistor Q _V , via which the voltage applied to a capacitor C _V voltage via line 19 is selectively coupled to the chamber 42 . An output control signal T _{WV of} the microprocessor 100 is supplied via the line 131 a, the amplifier 134 a and a resistor R _{V2 of} the base of the transistor Q _V , thereby making it conductive. As a result, the previously charged capacitor C _{V is} discharged to ground; Via the line 19 , a stimulus pulse with a pulse width corresponding to that of the signal T _WV is applied to the chamber 42 of the patient. The selector 130 a is closed for a predetermined duration by means of a control signal T _CV which is supplied via the bus 132 to recharge the capacitor C _V in the interval between successive control signals T _WV . The control signal T _WV thus makes the transistor Q _V selectively conductive and non-conductive, whereby a corresponding sequence of stimulus pulses via the line 19 to the chamber 42 goes. In unipolar pacing, the plate or housing 13 of the pacemaker 12 is connected to the other terminal of the battery.

As is apparent from Fig. 3A, the chamber line 19 is further connected via the conductor 138 a to the multiplexer, in particular to a switch 106 a ', which closes in response to a time window signal T _S. In this way, a signal indicative of chamber activity is applied to the microprocessor 100 via the amplifier and A / D converter stage 108 . The chamber line 19 is connected via the line 138 a, a capacitor C1, resistors R1 and R2 and an amplifier 139 to the multiplex switch 106 a '. When comparing the functional block diagram of Fig. 2 with the circuit design of Fig. 3A (as well as Figs. 3B and C), it should be noted that there is no exact correspondence between the components of these figures. Although it is stated that certain switches, in particular the switch 106a ', constitute part of the multiplexer 106 , a circuit-type difference is that in the circuit of Figs. 3A (and 3B and C) sense amplifiers, e.g. The chamber amplifier 139 , while the multiplexer 106 of FIG. 2 connects a particular one of a plurality of analog inputs to a single amplifier 108 . Therefore, it should be understood that the switching functions illustrated by way of example in FIG. 3A (as well as FIGS. 3B and C) may be performed in different ways. For example, the multiplex switch 106a 'may be replaced or supplemented by a selector switch 130 . The junction between the resistors R2 and R1 is connected to ground via a capacitor C2 in connection. As is apparent from Fig. 4A, it is desirable to ground (clamp) the amplifier 139 during certain periods of time, the refractory period within which no chamber signal is to be detected. For this purpose, a timing signal T _{CIV is applied} via line 120 to selector switch 130 c, thereby grounding the junction between resistors R2 and R1 during the refractory period. The circuit formed by the resistors R1 and R2 and the capacitors C1 and C2 serves as a coupling circuit between the Kammermeßverstärker 139 and the heart. When multiplex switch 106a 'is closed and the input of chamber amplifier 139 is grounded, it is desirable to provide isolation between ground and the heart because otherwise the heart could be severely damaged. For this purpose, the resistor R1 and the capacitor C1 are inserted between ground and the heart. The capacitor C2 also serves as a low-pass filter to filter out spurious signals that may be present on the line 19 , and to dampen the closing action of the selector switch 130 c. The chamber measuring amplifier may take the form of a known operational amplifier. The resistor R2 is connected to the input of the amplifier to adjust its gain in a known manner.

Fig. 4A shows a flow chart for the chamber demand stimulation corresponding to the output / input connections of Fig. 3A to apply stimulation pulses to the chamber 42 by means of the arrangement of Fig. 2. At time t₀, a ventricular stimulus has just been applied via lead 19 to the patient's chamber 42 . Thereafter, the RV amplifier 139 is clamped by closing the selector switch 130 c for the refractory period of t₀ to t₁ to ground. During the refractory period the capacitor CV is recharged by the control signal T _CV is applied to close the selection switch 130 a. Thereby, the voltage V _s for recharging the capacitor C _{V is} applied. At the time of implantation of pacemaker 12 and with fresh battery 126 , the refractory period is typically on the order of 325 ms. During the refractory period, the cardiac activity of the chamber 42 is not detected because various extraneous or extraneous signals may be present in the ventricle 42 that are not desired to be picked up. After the refractory period starting from the time t₁ of the selector switch 130 c is opened, while the switch 106 a 'closes. When the heart generates an R-wave signal which passes through line 19 , conductor 138a and chamber amplifier 139 to closed switch 106a ', microprocessor 100 responds thereto by resetting the timing cycle to t₀. The appearance of the R-wave signal from ventricle 42 indicates that heart activity is normal and that it is not desirable to deliver a competitive ventricular stimulus signal. Therefore, as long as the patient's heart generates an R-wave signal, the pacemaker 12 does not deliver a ventricular pacing signal. However, if the measurement period of t₁ to t₂ has expired without an R-Wqelle was detected, the microprocessor 100 generates a timing signal T _WV , via the conductor 131 a, the amplifier 134 a and the resistor R _V2 to the base of the transistor Q _V goes. As a result, the transistor Q _{V is made} conductive. The capacitor C _V discharges rapidly across the heart (represented by the resistor R₃) so that a stimulus pulse is applied to the chamber 42 via the line 19 and the housing 13 . During the stimulus period of t₂ to t₃ the chamber amplifier 139 is held by means of the closed switch 130 c to ground. Due to the above discussion, it is understood that the different periods corresponding to the pulse width of the ventricular pulse between the times t₂ and t₃ and the refractory period between t₀ and t₁, can be set or reprogrammed by adding new 8-bit words as shown in FIG be entered into the memory 102 .

FIG. 5 shows a flow chart for the steps taking place during the stimulation of the pacemaker during demand stimulation. The flow chart of FIG. 4A belongs to this flowchart; the connections of the output and input stages to the pacemaker 12 of Fig. 2 correspond to those of Fig. 3A. According to one embodiment of the invention the microprocessor 100 includes a plurality of pointer registers for storing pointers or addresses of word locations in the ROM part 102 b of the memory 102nd In this embodiment, the microprocessor 100 includes the following registers for storing the specified pointers:

R (0) = program counter (PC)
R (3) = loop counter (LC)
R (4) = time counter (TC)
R (A) = reference address for output status table (QP)
R (B) = pointer for time table (TP)
R (C) = reference point for voltage transition point table (VP)
R (D) = reference for refractory duration (TR)
R (E) = input instruction address (VDD)

Further, as explained with reference to Figs. 7A and 7B, the micro-processor is supplied with the flag input signals for the reed switch (EF2) and the R-wave (EF1). The notation for the flag inputs and the pointers as well as the counters will be used in the whole program list below. As is conventional with microprocessors, the microprocessor 100 includes the address counter 107 which, for each step of the program, while under the influence of the microprocessor 100 , advances one to designate the next location in the memory 102 from which information is to be read. The steps to be explained with reference to FIG. 5 in connection with a chamber demand stimulation were carried out using an RCA COSMAC microprocessor by the following machine instructions:

Fig. 5 shows a flow chart of the steps representing the above compiled commands. The corresponding step for the associated commands can be found under the heading "Step memory location". The program starts with the start step 200 and then proceeds to step 202 where the loop counter LC formed by the register R (3) is set to zero according to the command stored at the memory address 04. As is apparent from Fig. 4A, in the operating mode chamber stimulation a refractory condition corresponding to the refractory period, during which the Kammerver stronger 139 is clamped, a measurement or monitoring period during which the electrical chamber activity is detected and evaluated, and a pulse width state provided during which the ventricular stimulus pulse is applied to the ventricle 42 of the patient. The program loops through the steps of Figure 5 three times for each of the three states mentioned above, reducing the loop counter LC at the completion of each loop to indicate that the process has proceeded to the next state.

First, the loop counter LC is set to zero at step 204 . The process now proceeds to step 206 , within which the above-defined pointers VP, QP, TP and TR are set to their starting points. For example, VP is the pointer to the voltage transition point table. In step 206 , the register R (C) is set to the first place in the transition point table, which specifies the voltages with which the output voltage V _{s of} the voltage source 126 is to be compared. The pointer QP for the output state table stored in register R (A) indicates the location within the output state table indicating which of the states of Fig. 4A the processor is in, ie, the refractory period, the measuring or monitoring period, or the pulsing or pulse width period. The initial state table looks like this:

In step 208 then instructs the microprocessor 100, the A / D converter 108 to read a digital characteristic for the supply voltage V _s . In step 210 , the output state QP stored in the microprocessor register R (A) is incremented by one, ie brought to the next output state. At this point, register R (A) thus indicates that the process is in the initial refractory period. At step 212 , the voltage V _{s is} compared with the transition point voltage (VP) indicated by the voltage transition point table pointer stored in register R (C). If the voltage V _{s is} greater than the voltage transition point, the process proceeds to step 216 . If not, a transition is made to step 214 where the voltage transition point table reference address VP is incremented by one to indicate the next location of the table and to obtain the next lower value of the transition point voltage. The time TP address pointer TP is incremented by two to indicate the next two locations within the time duration table.

The next value of the voltage transition point will be the obtained below voltage transition point table:

The next value group for the monitoring duration and the Im pulse width is obtained from the time table below:

As can be seen are found in two places first, a duration for the monitoring period and then the pulse width for a given voltage transition point, ie a reference value, with which the voltage V _{s is} to be compared. The program thus adjusts the pulse width of the chamber stimulus so as to maintain a constant energy for the chamber stimuli; moreover, the monitoring period is increased abruptly when the voltage V _{s of} the voltage source 126 drops to provide a slowing down of the pacing rate at the end of the life of the battery.

In step 214 , the voltage transition point is switched from V1 to V2, for example from 5.2 to 4.8V. Again, the value of V _{s is} compared to the voltage transition point (VP) if it is greater (yes), then the program proceeds to step 216 where the value "three" is input to the loop counter LC to indicate that the oscillator in the refractory period. Thereafter, the A / D converter 108 is queried to read the supply voltage V _s . In step 220 , the value TR of the refractory period stored at the location TR is read out and stored in the time counter TC (register R (4)).

Thereafter, the process proceeds to step 222 , where the value stored in the time counter (TC) is decremented by one and the time control of one period is initiated to go through step 222 until the value stored in the time counter (TC) is decremented to zero is. Next, at step 224, a decision is made as to whether the value of the time counter TC is zero, ie, the timer function is completed. If not, the process proceeds to step 226 , where a decision is made to determine if the loop counter LC is at two, indicating whether the loop counter LC is at two, indicating whether or not the process is in the monitoring state corresponding to the RV measurement period. If this is not the case, as is the case here, steps 222 , 224 , 226 are sequentially executed until the initial count value (corresponding to the refractory period) set in the time counter TC is returned to zero by step 222 , which is determined in step 224 . This terminates the refractory period. At this point, step 224 transfers the process to step 232 , where the loop counter LC is decremented by one, thereby indicating that the process is in the monitor state, ie, LC is equal to two. Thereafter, the process returns to step 204 . At this point, the loop counter LC is not zero; the process proceeds to step 234 . There, the reference address QP for the output state table is incremented by one, while now the process goes to the measurement or monitoring state. Then, during step 236, the value obtained from the time-table is input to the time counter TC. The hint address (TP) for the time table is incremented by one to address the next largest pulse width within the time duration table.

Thereafter, the process proceeds to step 222 to decrease the count value inputted to the timer counter TC by one. If the value zero is not reached in step 224 , the program proceeds to step 226 . If the monitor state is present, which is true in this case, the process proceeds to decision step 228 to determine if an R-wave is being applied to the multiplexer 106 . If the R-wave is not detected within the time period of a single count-back step, the process returns to cycle again. At step 222, the count corresponding to the monitor period is decremented until the count is zero, which is determined at step 224 . If an R-wave is detected in step 228 , the process proceeds to step 230 to check the state of the reed switch 23 . If the reed switch is open, according to FIG. 4A, the process is reset to t₀, ie to step 202 , where the loop counter LC is set to zero and the process is initiated again. The reed switch 23 is a magnetically actuated switch housed inside the pacemaker 12 . After implantation, the physician may actuate the reed switch 23 by bringing an external magnet into proximity with the implanted pacemaker 12 . As a result, the reed switch 23 is closed; the asynchronous operating mode is initiated. If the reed switch 23 is closed, indicating that it is to operate in asynchronous operation, the process continues by looping, returning to step 222 to again decrease the time count TC even if an R-wave has been detected. In this way, the detection of an R-wave is ignored; The pacemaker 12 causes a stimulus pulse in asynchronous operation, without being reset when determining the R-wave.

After the second monitoring period has elapsed, that is, when the count stored in the time counter TC is counted down to zero in accordance with the indication in step 224 , the process again proceeds to step 232 where the loop counter LC is reset by one. The value stored there is now equal to one, indicating that the process is entering its third loop and returning to step 204 . Because the count in loop counter LC is not equal to zero, the process transfers to step 234 , incrementing the output state value QP by one, indicating that the process is now in the pulse width state. Next, in step 236 , addressing and access to the value of the time duration from the timeout table is performed; this value is stored in the time counter TC. The value of the pointer TP for the period of time is incremented by one to point to the next location in the time-table in the manner discussed above. At this point, the process begins with a sequence of cycles within which the count in time counter TC is decremented by one in step 222 . If the count is not equal to zero, a transition is made to step 226 . Since the process is not in the monitoring period, it goes back to provide a new reduction in step 222 . The process repeats until the count in the time counter TC is reduced to zero, a corresponding decision is made by step 224 . At this time, the process reverts to step 232 , within which the loop counter LC is again decremented by one so that the value now equals zero. The process proceeds to step 204 and starts from scratch with the initialization of the values of VP, QP, TP and TR in step 206 .

In the foregoing, the manner in which the pacemaker 12 performs the ventricular pacing program stored in the memory 102 is discussed, successively passing through the refractory period, then the monitor period, and finally the pacing or pulse width period before a new cycle begins. The length of the refractory period and the pulse width period is determined by the voltage V _{s of} the voltage source 126 . These periods, particularly the pulse width period, increase as the voltage V _s decreases to maintain the energy content of the ventricular stimulus substantially constant.

As noted, the memory 102 may be programmed with any of a variety of heart stimulation modes, with the particular program depending on the condition of the patient or a change in state following implantation of the pacemaker. For example, as shown in FIG. 4B, the pacemaker 12 may operate in an AV follow-up mode, with pacing pulses delivered to both the chamber 42 and the atrium 40 . After appropriate refractory periods, the chamber activity is monitored. If a chamber signal occurs after the chamber or the atria have been stimulated, the pacemaker is reset. The output and input terminals of the pacemaker 12 of Fig. 2 are selected as shown in Fig. 3B. As is apparent from FIGS . 3B and 4B, the chamber 42 is a pulse un indirectly supplied before the time t₀ by a stimulus signal is applied via the line 19 . After t₀ the Kammermeßverstärker 139 is clamped by the signal T _{C1 is applied} to the selector switch 130 c. Characterized the input of the amplifier 139 is connected to ground for a first refractory period of t₀ to t₁. During the first refractory period, the ventricular output capacitor C _V is recharged by the selector switch 130 a, the control signal T _{CV is} supplied. As a result, the supply voltage V _s to charge the Kon capacitor C _{V is} applied. In the period from t₁ to t₂, the switch 106a 'is closed by means of a coming from the microprocessor 100 control or clock signal T _S1 . As a result, a ventricular R-wave, if any, is applied through the chamber amplifier 139 and the multiplexer 106 to reset the timing operations of the microprocessor 100 .

If at t₂ no ventricular R-wave has been detected, the pacemaker 12 causes a stimulus pulse via the line 17 to the atrium 40 goes. In this case, a pulse control signal T _{WA is applied} via the driver amplifier 134 b and a resistor R _A2 to the base of a Vorhofausgangstransistors Q _A. The transistor Q _A is made conductive, so that an atrial output capacitor C _A discharges through the atrium 40 and this irritates. Starting with the time t₂ the time control signal is applied to the selector 130 c. The input of the chamber amplifier 139 is grounded, thereby disregarding any signal due to atrial stimulation. Beginning with the time t₃ the Vorhofausgangskondensator C _A is recharged by the timing signal T _{CA is} supplied to close the selector switch 130 b and the supply voltage V _s to the capacitor C _A apply. In the period between t₄ and t₅ in turn, the chamber activity is monitored. A timing signal from the microprocessor 100 closes the switch 106a 'so that the ventricular R-wave can be applied to the microprocessor 100 via the enabled chamber amplifier 139 and the closed switch 106a '. If during this second, ranging from t₄ to t₅ monitoring period, the ventricular R-wave is detected, the timer period is reset to t₀. If no R-wave appears within the period from t₄ to t₅, a timing pulse T _{WV is applied} by the microprocessor 100 through the ventricular driver 134a and the resistor R _V2 to make the chamber output transistor Q _V conductive. As a result, the charged condensate capacitor C _{V is} grounded. The capacitor C _V discharges. Via the line 19 , a stimulus pulse goes to the chamber 42 . Typical values for the period TA ranging from t₀ to t₂ and the period TV from t₀ to t₅ are given below:

TV (ms) TA (ms) 2000 1700 1000 750 850 700 850 650 750 600 750 500 650 300 550 425

For example, the AV sequential simulation method of FIG. 4B may be programmed similar to FIG. 5, except that the six output states and their corresponding time periods as shown in FIG. 4B are set by counter values derived from a corresponding table stored in memory 102 become. Thus, initially, typical values of TV and TA are programmed for a particular patient by accessing certain locations in the respective tables, one space at a time for each of the six periods. After a count is entered into the time counter, subsequent cycles are performed until the count is decremented to zero to provide an appropriate timing of that period.

Figure 4C shows the flow chart of an atrial synchronous paced mimic (ASVIP) in which both ventricular and atrial activity of the heart is detected to reset the timing period. Such a mode of operation is typically provided to a younger patient whose atria beat normally but whose chambers may be defective. It is desirable to accelerate the beating of the atria and thereby stimulate ventricular activity. A detected atrial P-wave triggers a timing cycle. However, if there is a disturbance in the transition of this signal to the chamber, the chamber 42 is in any case supplied with a stimulus signal. It is desirable to exploit the rate of beating atria to synchronize the pacing of the chambers which may be compromised as a result of myocardial infarction or otherwise defective cardiac conduction system. As shown in Fig. 4C, the cycle starts at time t₀ with the detection of the atrial P wave. Referring to Fig. 4C, a single cycle is divided into six time periods (and states). During the first time period from t₀ to t₁ (as well as during the second and third time period to t₄) the atrial amplifier 141 is clamped by a time control signal to ground potential; by means of this signal, the switch 130 d is closed. During the initial period of the approved Kammermeßverstärker 139 applies an optionally coming from the chamber 42 R-wave signal via the line 19 to the switch 106 a ', which is closed by means of an RV control signal. If an R-wave signal is detected during the initial period from t₀ to t₁, the time cycle is reset to t₀. In the second or impulse delivery period from t₁ to t₂, the atrial amplifier 141 remains clamped to ground. The switch 130 d is closed. A timing pulse T _WV goes through the driver amplifier 134 a and the resistor R _V2 to the base of the ventricular output transistor Q _v . The previously charged ventricular output capacitor C _V discharges via the transistor Q _V , the line 19 and the chamber 42nd During the second period (and also into the periods three and four into the time point t₄) of the chamber amplifier 139 is clamped by means of a switch 130 c to ground. The switch 130 c is a Kam merklemmsignal TC1 supplied. This ignores cardiac activity occurring in the post-ventricular pacing period. In the fourth and fifth period from t₃ to t₅ the chamber amplifier 141 is released, so that the atrial P-wave signal can be applied via this amplifier and a closed selector switch 106 b 'to reset the timing of the process to t₀. From t₃ to t₅ a monitoring time signal RA is applied, by means of which the switch 106 b 'is closed. In normal operation, an atrial P-wave signal during the fourth and fifth time period from t₃ to t₅ can be measured, whereby the timing cycle is reset to zero. However, if no P-wave is detected, the chamber is re-excited by giving a control pulse T _WV to the base of the chamber output transistor Q _V. As a result, a pulse is applied via the line 19 to the chamber 42 of the patient in the manner described above.

For example, the ASVIP pacing method may be programmed similar to that of FIG. 5, with six periods or initial states defined in a similar manner, and each of the six time periods being provided by addressing pointers to corresponding tables. In this way, varying values of the periods are input to a time counter whose count value is decreased as the process is executed through each of the six loops.

Fig. 6 shows a modified embodiment of the adaptive, programmable pacemaker, wherein corresponding components and circuit stages are denoted by like reference numerals as in Fig. 2, but which are in the hundreds of hundreds series. The microprocessor or central processing unit (CPU) 300 is coupled to a multiplexer 306 , whereby one of the inputs 338 a, b, e, or f is communicated to the microprocessor 300 in the form of a flag via a bus 318 . The microprocessor selectively addresses, via an address bus 312, a memory 302 having, for example, a plurality of sections 302-1 to 302-16 . According to FIG. 6, the memory 302 can be designed as a regeneration memory, for example as a memory with direct access, or as a programmable read-only memory (PROM) or as an erasable read-only memory (EROM). The addressed data is read from the memory 302 and supplied to a data bus 310 which interconnects the memory 302 , the microprocessor 300 , a decoder 342 and an A / D converter 308 . The A / D converter 308 converts the analog value of the supply voltage V _s into a digital form. The signal in question is input to the microprocessor 300 via the data bus 310 . It is understood that the other analog values, such as the P and R waves, are also converted to digital form and normalized. The A / D converter and normalization stages are coupled to the multiplexer 306 . They are constructed similarly as explained above and not shown in Fig. 6. The microprocessor 300 provides timing signals over an N bus 352 , thereby commanding the decoder to initiate decryption of the signals appearing on the data bus 310 . Due to the output of the microprocessor 300 , the decoder 342 selects one of a plurality of switches 1 through 16 within the block 330 . Each switch of block 330 is assigned its own latch in block 340 , which is set by the output of decoder 342 . The switches are in turn connected in the manner explained above with an amplifier and output driver circuit. In this way, a sufficient flexibility is ensured in order to provide a plurality of output circuits can be coupled via lines with different parts of the heart. In addition, the output driver circuits can be recharged. Access to data at various points either on the heart or on other parts of the patient's body is possible. In this way, a telemetry system is provided to communicate data to or from the programmable pacemaker of FIG. 6.

In accordance with another feature of the embodiment of FIG. 6, a self-resetting oscillator circuit 344 is provided to reset an address counter 307 within the microprocessor 300 . The address counter 307 is incremented for each processed step to address the next word location within the memory 302 . It has been found that spurious signals, such as those generated by a defibrillation pulse or other source, could cause the address counter 307 to address a meaningless or erroneous location within the memory 302 . As a result, the process would hang in a meaningless place. If the address is affected by spurious signals to address a meaningless location, the self-resetting oscillator circuit 344 periodically resets, for example, 0.5 s, the address to an initial output address for the program being executed. If the address counter 307 is operating normally, an output signal is derived from the data bus 310 and applied via a line 346 to reset the circuit 344 and thus disable the regular reset output.

According to a further feature of the invention, the multiplexer 306, an additional set of inputs 339 a to 339 d for receiving a binary start address, which is to be introduced into the address counter 307, so that each of the plurality of blocks 302-1 to 302- 16 can drive. A plurality of pacing modes may be stored in memory 302 . The storage of each mode is done in a separate block. The associated starting point can be addressed by a binary number via the inputs 339 a to 339 d and an external connection 341 is input, which, as explained above, can be designed as a Hf connection or acoustic connection.

In addition, self-checking programs or data acquisition programs may be stored in certain blocks of the memory 302 . Fig. 3A shows how, for example, a self-test program can be performed to check the operability of the Kammermeßverstärkers 139 . Another selector 130 g can be closed in response to a test signal T _t , which is generated by means of such stored in memory 102 Selbstprüfprogramms to apply a reference voltage V _{ref of} the order of 1 mV to the input of Kammermeßverstärkers 139 . The amplified output signal is in turn supplied to the microprocessor 300 via the multiplexer 106 , the amplified voltage being compared to a reference value to determine if the amplifier 139 is operating properly. If this is not the case, another output stage and another measuring amplifier can be connected to replace the defective measuring amplifier.

In accordance with another mode of operation, a program may be stored in one of the blocks of memory 302 to effect detection and communication of data supplied to the implanted pacemaker via respective leads. For example, the leads may be connected to cardiac tissue, other tissue, or transducers to detect the patient's ECG, pulse rate, pulse width, de polarization time between the atrium and the chamber, and the like. The transmission time of a depolarization signal is considered to be indicative of the state of the heart, and a time window corresponding to a normal transition duration is determined by means of a measurement program. If the received signal is outside the limits of such a time window, an indication for it is transmitted externally. As part of a data acquisition operation, the latches associated with the lines leading to the respective sites of the heart, other tissue or transducers can be individually coupled one at a time by selectively closing the corresponding selector switch 330 , such that the data in question is via the external connection 341 are transmitted to an external monitoring device.

In addition, an input 338 f is provided, which is connected to the tongue switch 23 , which can be closed by means of an external magnet to change the operation of the pacemaker of FIG. 6. By opening and closing the switch 23 , a sequence of signals can be generated; in this way, the external link 341 is enabled to receive or transmit data to or from the pacemaker 12 ' . For example, a new address is input to the address counter 307 to address the starting location of the next block of the memory 302 , thereby performing another mode.

Fig. 7A shows a more detailed schematic circuit diagram of the blocks of a first embodiment of the apparatus of Fig. 6. The multiplexer 306 has a sequence of sixteen inputs 0 to 15 . The multiplexer 306 outputs an output to the A / D converter 308 . An embodiment of this converter is explained below with reference to FIGS. 8, 9 and 10. The A / D converter 308 is connected to the microprocessor 300 via the data bus 310 and further connected to a latch 309 , whereby one of the sixteen inputs of the multiplexer 306 is selected to provide analog data to the A / D converter 308 . The N-timing bus 352 is in the form of a bundle of lines 352a- d; it is connected to the decoder 342 , which consists of a plurality of gates. The outputs of two of the gates are connected via lines 356 to a conversion command input and to a tristate output. The translation command input causes the A / D converter 308 to accept data from the multiplexer 306 , while causing the A / D converter 308 via the tristate output to apply the data converted to digital form to the data bus 310 . Furthermore, sampling pulses 1 and 2 from lines 354 a and b are derived; these sampling pulses go latch circuits 342 a and 342 b, whereby data applied to the data bus 310 a can be supplied from a plurality of switches selectively that are present in the blocks 330 a and 330 b. The blocks 330a and 330b each include four solid state select switches through which output signals go to selected output driver circuits. In the embodiment illustrated in FIG. 7A, the sensed R-wave signal is also applied to the input of the microprocessor 300 while the Tongue Switch input is applied to the input of the microprocessor 300 . In this embodiment, the microprocessor operates as its own multiplexer to selectively access signals given to these inputs and to respond to those signals in the desired order. The microprocessor 300 also provides addresses to the memory 302 via the address bus 312 , whereby data can be read out and applied to the data bus 310 .

Fig. 7B shows a detailed schematic circuit diagram of a second embodiment of the pacemaker of Fig. 6. The components of Fig. 7B are given the same reference numerals as corresponding components of Fig. 6, but in the five hundreds series. The R-wave, the P-wave and the reed switch output signal corresponding input signals are applied to the inputs, and the microprocessor 500 . In this embodiment, the microprocessor 500 executes multiplexing functions so that each one of these values is processed. Typically, such input signals are in analog form; they must be converted to digital form by circuits summarized in dashed block 508 . The A / D converter has a circuit component and receives input signals from operational amplifiers 511 to which a reference signal formed by Zener diodes 513 is supplied. A clock signal is supplied to an input of the converter 515 via a flip-flop 509 and a field effect transistor 517 . The memory 502 is connected to outputs of the microprocessor 500 and consists of two blocks. Microprocessor 500 provides commands via N-Bus 552 to a decoder 542 . The decoder 542 executes decoding functions for the output of the memory 502 under the influence of the timing signals sent via the N bus 552 . The output signals of the decoder 542 are applied to two latch stages 540 a and 540 b. The decoder 542 selects a latch, which closes a corresponding selector switch within the switch groups 530 a and 530 b. The selector switch groups may consist of integrated circuits.

FIG. 8 shows a preferred embodiment of a low energy A / D converter 308 as provided in the pacemaker of FIG . Referring to Fig. 8, an analog voltage V (X) to be converted to digital form is applied via an input line 404 to a switch (S₁) 407 which in a first position (up) the analog voltage V (X) to the input (V _in ) of a voltage controlled Oscillator (VCO) 402 feeds, whose output is connected to the input of Akkulumatorzählers 400 . As indicated by the inputs of the counter 400, the accumulator counter 400 can either count up (on) or reverse (ab). An output of the counter passes through a gate 414 to an input 1500500070 552 001000280000000200012000285911489400040 0002002929498 00004 14886 of an N output counter 412 . A clock signal is applied via an input line 418 to a control logic 408 and in particular to a divide-by-n circuit 410 , by means of whose output signal the switch 407 can be brought into a second position (down). As a result, a reference voltage is given via a line 406 to the input of the Os cillators 402 . At the same time, an ab command signal passes through a gate 418 ' to the ab input of the accumulator counter 400 , which then causes it to count down. At the same time, an output signal from the control logic 408 also goes to the reset input of the N output counter 412 .

The A / D converter 308 of Fig. 8 operates as follows. An unknown voltage V (X) is applied to the oscillator 402 via the switch 407 during a fixed period T _up . During this period T _up, the accumulator counter 400 counts out the output signal of the oscillator 402 in the forward direction. The accumulator counter 400 operates very much like an analog integrator in that the count of the accumulator counter 400 builds up at a linear rate for a given voltage level of V (X).

The time T _up depends on the clock frequency supplied via the line 418 , the control logic 408 and the circuit 410 . At the end of the time period T _up , the switch S 1 is brought into the second position in order to connect the input of the oscillator 402 to the reference voltage E _ref . Simultaneously with this switching to the reference voltage, the "A" accumulator counter 400 is switched to downcounting. During this countdown timer, a proper circuit stage checks when the accumulator counter 400 is at a predetermined count, e.g. B. zero, has counted back. The time required to count down the reference voltage to zero is proportional to the average of the input voltage V (X). While the accumulator counter 400 is being counted down to zero, the clock frequency F _{CLK is} counted by the N output counter 412 . Counts accumulated in the N output counter 412 are in digital form and are directly proportional to the initially unknown voltage V (X). This leads to a voltage / frequency conversion.

The basic equations for operating the A / D converter 308 are:

A _on = K _VCO T _up (1)

A _ab = K _VCO E _ref T _x (2)

Equations (1) and (2) indicate the forward and backward counts of the accumulator counter 400 as a function of the unknown voltage and the reference voltage and the time duration during which this voltage is supplied to the oscillator 402 . The count-up and count-down counts of counter 400 are the same because counter 400 starts from zero and returns to zero at the end of a cycle. If one equates these two equations, the scale factor K _VCO for the voltage-controlled oscillator drops out, ie this factor has no influence on the output signal of the A / D conversion. Equation (3), which indicates the accumulated count N (X) of the output counter as a function of the clock frequency F _CLK and the time required to bring the accumulator counter back to zero, ie T _X , is as follows:

N (X) = T _X F _CLK (3)

Equation (4), which gives the up-count duration T _up as a function of the "n" counter and the clock frequency, has the following form:

T _up = n / F _CLK (4)

Equation (5), which shows that the count N of the output counter proportional to n and divided by the unknown voltage through the reference voltage is:

Equation (5) shows that the digital output counter N (X) is independent of the clock frequency F _CLK , the sampling frequency and, which is of particular interest, also independent of the scale factor of the voltage controlled oscillator. For example, if the unknown voltage V (X) is 2 volts, the reference voltage is equal to 2 volts and the n counter is at 64, then at the end of each conversion in the output counter N is a count of 64. This particular feature of the A / D Converter allows to put in series with the switch S 1 and the voltage controlled oscillator 402 an amplifier, we sentlichen without that affects the output count. This is true even if the gain varies or varies from unit to unit, provided that the gain remains constant during a conversion cycle. In other words, because, as shown in FIG. 8, a single voltage controlled oscillator 402 is used to process both the analog input voltage V (X) and the reference voltage E _ref , the scale factor imposed by the oscillator 402 has on the digital output of the counter 412 no influence. Further, because the same clock signal F _{CLK is} used to specify both the clock for the accumulator counter 400 during the count back period T _X and the clock for the N output counter 412 during the same period, the frequency of the clock signal F _CLK affects the digital output of the clock Counter 412 , which is indicative of the amplitude of the analog input signal V (X). The clock used for the delivery of the clock signal F _CLK therefore requires no high accuracy Ge and thus no relatively high power consumption. Rather, the clock can be designed so that it takes the power source, ie the battery of the pacemaker, only to a minimal extent power.

Fig. 10 shows a detailed circuit diagram of the A / D converter 308 of FIG. 8. The input signal is a bidirectional switch in the form of the switch 407 supplied, the output signal goes to the voltage controlled oscillator, which is included in a circuit with phase locked loop. The output signal from the voltage-controlled oscillator is supplied to the accumulator counter 400 , which consists of four up / down counters. The clock frequency F _CLK is applied together with the sampling pulse via lines 418 and 420 , respectively, in order to set the output signal of the accumulator counter 400 in time to the output N output 412 . A crucial part of the illustrative embodiment of the A / D converter 308 is the design of the control logic 408 which, as shown in FIG. 10, has a counter 409 in the form of a 4-bit ring counter. This counter 409 forces the A / D converter 308 to one and only one of four possible modes according to its four output states 0, 1, 2, and 3. These four modes of the A / D converter 308 of FIG. 10 are: (1 ) Waiting; (2) presetting; (3) count up and (4) count down.

The waiting mode represents an idle state for the A / D converter 308 , in which the voltage controlled oscillator 402 is switched abge, the unknown voltage and the reference voltage via the bidirectional switch S 1 are separated from the oscillator 402 and the last converted digital word in the counter 402 is a digital, parallel 8-bit word. Translator 308 will remain in the wait state until it receives a strobe pulse that causes the transition to preset mode. When waiting, the A / D converter 308 consumes very little energy.

The preset state following the wait state is used to set the accumulator consisting of the counters 400 a, 400 b and 400 c via a spurious input to a binary word of one. The counter 412 is reset during this mode. The maximum available time for the pre-adjustment is half a clock period.

During the count up the output of the divider 3 is brought to logic 1 409, whereby the accumulator counter 400 a, 400 b and 400 c are forced to include in the forward mode. During this mode, the bi-directional switch S 1 outputs the unknown analog input signal to the input of the voltage controlled oscillator 402 . The n counter 410 begins to determine the amount of time during which the unknown voltage is applied by counting the reference clock frequency up to the preprogrammed count value which causes the output 9 of an AND circuit 425 to logic 1. During this phase count values in the counters 400 are a, 400 b and 400 c accumulated. When the output 9 of the AND circuit 425 jumps to logic 1, indicating that the count-up period has been reached, the outputs 8 and 9 are both at logical 1; a command to advance the ring counter 409 goes to a pulse stretch gate 427 . When the next clock pulse reaches logic 1, the ring counter 409 is switched to the next state corresponding to the count down.

A countdown operation is effected by setting the output 7 of the ring counter 409 to logic 1. This condition forces the accumulator counter 400 to count down. In addition, the reference voltage is applied to the voltage-controlled oscillator 402 . The clock frequency is supplied to the input of the N counter 412 . Therefore, when the count values are driven out of the accumulator counters 400 a, 400 b and 400 c, clock pulses are accumulated in the N counter 412 . When the accumulator counter string is controlled to logic 0 in all states, the output of an AND gate 429 jumps to logic 1. The ring counter 409 is made to wait via the above-described burst network. The completion of this cycle causes the unknown input voltage V (X) to be digitized and held in the output counter 412 at the scale factor discussed above.

The A / D converter 408 of FIGS. 8 and 10 is particularly useful with the pacemaker 12 of FIG. 1. It is critical to provide circuit components in the pacemaker that are responsive to the energy source of the pacemaker, e.g. B. in the form of the pacemaker battery, draw a minimum of power ent. For this purpose, the circuit arrangement of FIG. 10 can be implemented in CMOS technology. Furthermore, to provide an output signal, the oscillator 402 is powered only during those periods during which an analog input signal V (X) must be digitized. At other times, the voltage controlled Os cillator 402 is de-energized. The feeding of the oscillator 402 is done under the influence of the control logic 408 and in particular the ring counter 409th In addition, the A / D converter 308 can be adjusted by providing different values of "n" in the counter 410 . The A / D converter 308 is therefore suitable for detecting input voltages of varying amplitudes. In the various embodiments of the pacemaker discussed above, it is convenient to translate both the relatively high voltage V _{s of} the battery and the relatively small voltage signals derived from the patient's chamber and atrium. Referring to FIG. 10, the preselected count- _{up period} T _{up is} determined by the value "n" which is input to the "n" counter 410 . The value of "n" may be adjusted according to an embodiment of the invention by connecting one of the multiple outputs Q 4 , Q 5 , Q 6 and Q 7 of the "n" counter 410 . A switching stage (not shown) may be provided between one of the outputs of the counter 410 and the AND circuit A 9 to subject the value of "n" of FIG. 7A to control by the microprocessor 300 . In addition, a per se known, programmable counter may be provided instead of the present counter 410 , which makes it possible to vary a binary word stored in the counter under the influence of the microprocessor. The value of "n" can thus be changed depending on which analog input signal is to be converted to digital form. The value "n" is varied as a function of the amplitude of the respective input voltage V (X), larger values of "n" being provided for smaller amplitudes. In practice, it is desirable to obtain a count from the output counter 412 which approximates the known counting capacity to thereby ensure the maximum resolution for an input signal of given amplitude. A single analog-to-digital converter 308 can thus be used for different input signals of varying amplitude, ensuring the accuracy of the binary output signal by varying the value of "n". It is understood that the converter 308 is not limited to the specific application described above.

Claims (18)

1. Microprocessor-controlled implantable pacemaker which can be coupled via a line arrangement to be stimulated body weight, characterized in that the line arrangement ( 17, 19, 29 ) has a plurality of lines or line combinations connected to the same and / or under different locations of the body tissue be provided that one of the microprocessor ( 100, 300, 500 ) with associated memory ( 102, 302, 502 ) controlled evaluation is provided on the input side via a controlled by the microprocessor multiplexer ( 106, 306 ) and the output via a likewise from the Microprocessor controlled selector switch device ( 130, 330, 530 ) is connected to the line arrangement, that the evaluation device is constructed and programmed to determine based on detected in the course of pacemaker characteristics, which line or line combination for the implementation of the respective Stimula tion and / or measuring task is most appropriate, and by appropriate control by the microprocessor via the selector automatically the line or line combination on the one hand for the transmission of input signals from the body tissue to the evaluation and on the other hand for the transmission of stimuli to the body tissue effective, and that a common combined normalization amplifier and A / D converter ( 108, 308 ) is connected between the multiplexer and the microprocessor, common to all the multiplexer analog input signals. 2. A pacemaker according to claim 1, characterized in that one ( 138 c) of the inputs of the multiplexer ( 106 ) is acted upon by a signal which is indicative of the output voltage of a part of the pacemaker forming voltage source ( 126 ), and that the microprocessor ( 100 ) modifies the performance of the pacer in response to that signal. 3. A pacemaker according to claim 2, characterized in that the microprocessor ( 100 ) with decreasing output voltage of the voltage source ( 126 ) causes an automatic increase in the stimulus pulse width such that the energy of the stimulus Impulsim remains largely constant. 4. A pacemaker according to one of the preceding claims, characterized in that the memory ( 102, 302 ) a plurality of memory sections ( 302-1 to 302-16 ), in each of which a program for one of several different pacemaker modes is stored, that the microprocessor ( 100, 300 ) is associated with an addressing device ( 107, 307 ) for addressing the programs stored in the memory sections, and that the multiplexer ( 106, 306 ) is provided with at least one additional input ( 138 f; 339 a to 339 d) for signals for Driving the addressing device via the microprocessor for the purpose of selecting the respective desired program is provided. 5. A pacemaker according to claim 4, characterized in that the at least one additional input ( 339 a to 339 d) of the multiplexer ( 306 ) to the output of a part of the pacemaker forming the receiver ( 341 ) is connected, for the purpose of selecting the respectively desired Program receives encrypted control signals from outside the patient's body arranged transmitter ( 343 ). 6. A pacemaker according to claim 4, characterized in that the additional input gang ( 138 ) of the multiplexer ( 106 ) to a part of the pacemaker forming switch ( 23 ) is connected, which is actuated for the purpose of selecting the respective desired program by means of an external magnet , 7. A pacemaker according to any one of claims 4 to 6, characterized in that connected to the microprocessor ( 300 ) is a reset means ( 344 ) for periodically generating a reset signal, which resets the addressing means ( 307 ) to a predetermined output address. 8. A pacemaker according to claim 7, characterized in that the restoring device ( 344 ) is locked in perfect working of the addressing device ( 307 ). 9. A pacemaker according to one of the preceding claims, characterized in that in the memory ( 102 ) a program is stored, which causes the microprocessor ( 100 ) based on the detected by the evaluation in the course of pacemaker characteristics automatically one of several in the Memory ( 102 ) programs stored for each a different pacing mode selects. 10. pacemaker according to one of the preceding claims, characterized in that in the memory ( 302 ) self-test and data acquisition programs for testing the functionality of multiple functional units ( 139 ) of the pacemaker and for automatically coupling one of the other radio tion units upon detection of a defect of checked functional unit are programmed. 11. A pacemaker according to one of the preceding claims, characterized in that the selector switch device ( 330, 530 ) responsive to the output from the memory ( 302, 502 ) signals responsive to and controlled by the microprocessor ( 300, 500 ) decoding means ( 342, 542 ) for selecting individual selector switches of the selector device and a latch assembly ( 340, 540 ) are connected upstream, which holds in response to the signal of the decoder closed the selected selector switch. 12. A pacemaker according to one of the preceding claims, characterized in that the content of the memory ( 102 ) after implantation by means of encrypted signals is changeable, which are transmitted from an external device ( 10, 16 ). 13. A pacemaker according to any one of the preceding claims, characterized in that the combined normalization amplifier and A / D Umstzer ( 308 ) is provided with

• - An oscillator ( 402 ) which outputs an output signal whose frequency depends on the oscillator input signal,
• a signal generator for generating a reference signal,
• a switch ( 407 ) coupled to the input of the oscillator ( 402 ) and capable of being brought from a first position in which it supplies the analog input signals to the oscillator input to a second position in which it supplies the reference signal to the oscillator input,
• a first counter ( 400 ), which is acted upon by the oscillator output signal and which counts up in accordance with the frequency of the oscillator output signal in one operating mode to form an output signal and counts backwards in a second operating mode,
• - a selectively the output of the first counter ( 400 ) receiving the second counter ( 412 ) to form a corresponding digital output signal,
• a clock for supplying a clock signal and
• - a clock receiving controller ( 408 ) for providing a control signal upon receipt of a selected number (n) of clock oscillations, said switch ( 407 ) responsive to the control signal transiting from the first to the second position, the first counter ( 400 ) in response to the control signal, the first mode of operation terminates, so that at this time the oscillator output signal represents a first count indicative of the analog input signal and the first counter ( 400 ) in the second mode of operation begins to operate from the first count value counting from the reverse, further wherein the second counter ( 412 ) starts the control signal in response to the counting of the clock signal oscillations, and when the output of the first counter ( 400 ) reaches a second predetermined count, counting the clock signal oscillations to form the digital output signal ended, regardless of the tak tsignal frequency is indicative of the analog input signal.

14. A pacemaker according to claim 13, characterized in that the controller ( 408 ) has a third counter which counts n oscillations of the clock signal and thereafter outputs the control signal and which is provided with means for a changeable setting of the value of n. 15. A pacemaker according to claim 14, characterized in that the third counter ( 410 ) comprises means for receiving and storing a characteristic value for n. 16. A pacemaker according to claim 13, characterized in that the controller ( 408 ) comprises an activating means which activates the sampling signal indicative of the presence of an analogue input signal to be converted in response to the oscillator ( 402 ) for a period corresponding to the period of time required to operate the first counter ( 400 ) in the first and second modes to convert the analog input signals to the corresponding digital output signals. 17. A pacemaker according to claim 16, characterized in that the activation means comprises a ring counter having a first output indicative of the period of time within which the oscillator ( 402 ) is deactivated, a second output indicative of the first mode of operation of the first counter ( 400 ), and has a third output indicative of the second mode of operation of the first counter. 18. A pacemaker according to any one of claims 13 to 17, characterized in that the combined normalization amplifier and A / D converter ( 308 ) is constructed of CMOS components.