DE2954642C2 - - Google Patents

Abstract

A multi-mode pacemaker includes a microprocessor 100 and a memory 102 programmable with a variety of processes for stimulating a heart and/or a sensing and transmitting to an external device conditions of the heart or pacemaker. The microprocessor controls a multiplexer 106 to input via a scaling amplifier and a/d converter 108 signals from atrial and ventricular leads 17, 19, the power source 126, a reed switch 23 operable by an external magnet, or redundant leads on lines 138d,e. The output comprises latch drivers 134 a-d with respective output select switches 130 a-d selectively operable to supply stimulation pulses to the leads or allow sensing. External apparatus 104 may transmit coded information to change the stored program or operation of the reed switch may select a different program starting address. Pulse width, rate and amplitude may be controlled in response to sensed heart activity or power source level and different pacing modes (demand, asynchronous, etc.) or multi-site pacing to disrupt arrhythmias may be selected automatically or externally. In an aid converter 308 (Figure 8), counter 400 counts up the output of VCO 402 controlled by unknown signal V(X) and then counts down to zero the output of VCO 402 then controlled by reference EREF and during such countdown a counter 412 counts clock pulses so that when counter 400 reaches zero the output of counter 412 depends on V(X) but not on the scale factor of VCO 402. <IMAGE>

Description

The invention relates to a device for converting analog input signals into corresponding digital output signals with:

• (a) an oscillator with an output for supplying a first output signal, whose frequency depends on the signal fed to its input,
• (b) a reference signal generator for generating a reference signal,
• (c) a switch coupled to the input of the oscillator and consisting of a first Position in which he the analog input signals to the input of the oscillator leads, can be brought into a second position in which it the input of the oscillator Feeds reference signal,
• (d) a first counter which receives the first output signal and which corresponds to the Frequency of the first output signal to form a second output signal counts up in a first mode and counts down in a second mode counts
• (e) a clock generator for supplying a clock signal and
• (f) a controller receiving the clock signal for supplying a control signal after receiving a selected number of oscillations of the clock signal, where at the switch responsive to the control signal from the first to the second Position passes, the first counter in response to the control signal working ended in the first mode so that at this time the second output signal represents a first count characteristic of the analog input signal sets, and the first counter with the second mode begins to work from count down from the first count.

In a known device of this type (US 36 68 690), the output signal of the oscillator has a fundamental frequency f _o when there is no signal or a zero voltage signal at the input of the oscillator. As long as the switch is in the first position, the frequency of the oscillator output signal is equal to the sum of the fundamental frequency f _o and an unknown frequency f _x , which is due to the analog input signal. In the second position of the switch, the oscillator emits a signal with the basic frequency f _o . The first counter is caused to count the pulses of the signal with the frequency f _o + f _x during a given by the clock before given first period of time with the switch in the first position in the forward counting mode. During a subsequent second time period, which is also determined by the clock and has the same length as the first time period, the first counter counts when the switch is in the second position, starting from the count value reached in the first time period in the downward counting mode Pulses of the signal with the frequency f _o . As a result, the count value at the end of the second time period in the first counter is a measure of the amplitude of the analog input signal. However, this count value is also dependent on the clock frequency of the clock signal and on the characteristic values of the oscillator.

It is also an analog-to-digital converter with a switch, an oscillator, a Reference signal generator, a first counter and a logic control circuit known (DE 24 27 800 A1), in which the control circuit contains further counters. Doing so however, the first counter does not directly apply the oscillator output signal strikes. Rather, the oscillator output signal is only via a counter and a Phase detector passed, which additionally via a further counter and a Be train oscillator is supplied with a reference signal. This translator requires one relatively large circuit effort.

The invention has for its object to provide an A / D converter that knows Test independent of changes to one used in the course of the conversion Clock and / or sampling frequency and also independent of fluctuations in characteristic values or - Scattering of the modules used is as well as with a relatively low scarf effort.

This task is based on a device of initially mentioned type solved by the invention

• (g) a second counter receiving the second output signal to form a corresponding third digital output signal,
  wherein the second counter in response to the control signal begins with the counter of the oscillations of the clock signal and, when the second output signal reaches a second predetermined count value, ends the counting of the oscillations of the clock signal to form the third digital output signal, which is characteristic of the analog input signal and is independent of the frequency of the clock signal.

Preferred further developments of the invention result from the subclaims chen.  

The measures of claims 2 and 3 allow simple adaptation of the AD Converter to input signals of different amplitudes.

With the measures of claims 4 to 6, the energy consumption of the A / D Keep the converter particularly low.

A preferred embodiment of the A / D converter according to the invention is according to standing explained with reference to the drawings. It shows

Fig. 1 is a functional block diagram of the A / D converter,

Fig. 2 is a graph showing the operation of the up / down counter provided in the converter of Fig. 1, and

Fig. 3 is a diagram of the A / D converter of FIG. 1.

In the low-energy A / D converter 308 shown in FIG. 1, an analog voltage V (X) to be converted into digital form is applied via an input line 404 to a switch (S 1) 407 which, in a first position (up), the analog voltage V (X) supplies the input (V _in ) of a voltage controlled oscillator (VCO) 402 , the output of which is connected to the input of an accumulator counter 400 . As indicated by the inputs of the counter 400, the accumulator counter 400 either forward (up) or back (down) can count. An output signal of the counter goes via a gate 414 to an input of an N-output counter 412 . A clock signal f _clock is applied via an input line 418 to a control logic 408 and in particular to a circuit 410 dividing by n (hereinafter also referred to as n counter), by means of whose output signal the switch 407 can be brought into a second position (down) . A reference voltage E _ref is thereby given to the input of the oscillator 402 via a line 406 . At the same time, a down command signal passes through a gate 418 'to the down input of the accumulator counter 400 , which then causes a countdown. At the same time, an output signal from control logic 408 also goes to the reset input of N output counter 412 .

The A / D converter 308 shown in FIG. 1 operates as follows. An unknown voltage V (X) is applied to the oscillator 402 via the switch 407 for a fixed period of time T _up . During this period T _up, the accumulator counter 400 counts the output signal of the oscillator 402 in the forward direction. The accumulator counter 400 operates similarly to an analog integrator in that the count value of the accumulator counter 400 builds up at a linear speed for a given voltage level of V (X).

The time T _up depends on the clock frequency f _clock , which is supplied via the line 418 , the control logic 408 and the circuit 410 . At the end of the period T _up , the switch S 1 is brought into the second position in order to connect the input of the oscillator 402 to the reference voltage E _ref . Simultaneously with this switching to the reference voltage, the "A" accumulator counter 400 is switched to counting down. During this countdown, an appropriate circuit stage checks when the accumulator counter 400 is at a predetermined count, e.g. B. zero, has counted down. The time required for counting down the reference voltage to zero is proportional to the mean value of the input voltage V (X). During the accumulator counter is decremented to zero 400, the clock frequency f _clock by means of the N-output counter is counted 412th Count values obtained in the N output counter 412 are in digital form and are directly proportional to the initially unknown voltage V (X). This leads to a voltage / frequency conversion.

The basic equations for operating the A / D converter 308 are:

A _Auf = K _VCO V (X) T _up (1)

A _Ab = K _VCO E _ref T _X (2)

Equations (1) and (2) indicate the up and down count of the accumulator counter 400 as a function of the unknown voltage V (X) and the reference voltage E _ref and the time periods during which these voltages are supplied to the oscillator 402 . The up count and down count of counter 400 are the same because counter 400 begins at zero and returns to zero at the end of a cycle. If these are equated to one another in the equations, the scale factor K _VCO for the voltage-controlled oscillator 402 falls out, ie this factor has no influence on the output signal of the A / D conversion. Equation (3), which gives the accumulated count N _{(X) of} the output counter as a function of the clock frequency f _clock and the length of time required to bring the accumulator counter back to zero, ie T _X , is as follows:

N _(X) = T _X f _clock (3)

Equation (4), which specifies the _up counting time T _up as a function of the n counter and the clock frequency, has the following form:

T _up = n / f _cycle (4)

Equation (5), which shows that the count value N of the output counter ( 412 ) is proportional to n and the unknown voltage divided by the reference voltage is:

Equation (5) shows that the digital output count N _{(X) is} independent of the clock frequency f _clock , the sampling frequency and, which is of particular interest, also independent of the scale factor of the voltage-controlled oscillator 402 . For example, if the unknown voltage V (X) is 2 volts, the reference voltage E _ref is 2 volts, and the n-counter is at 64, there is a count of 64 in the output counter 412 at the end of each conversion. This special property of the A / D converter 308 allows an amplifier to be placed in series with switch S 1 and voltage controlled oscillator 402 , essentially without affecting the output count. This is true even if the gain changes or differs from unit to unit, provided that the gain remains constant during a conversion cycle. In other words, because according to FIG. 1 a single voltage controlled oscillator 402 is used to process both the analog input voltage V (X) and the reference voltage E _ref , the scale factor due to the oscillator 402 has on the digital output of the counter 412 no influence. Furthermore, because the same clock signal f _{clock is} used to specify both the clock for the accumulator counter 400 during the down count period T _X and the clock for the N output counter 412 during the same period, the frequency of the clock signal f _clock affects the digital output of counter 412 , which is indicative of the amplitude of the analog input signal V (X). The _clock used for the delivery of the clock signal f _clock therefore does not require high accuracy and therefore also does not require a relatively high current consumption. Rather, the clock can be designed so that it supplies the A / D converter with energy source, for. B. a battery, takes power to a minimal extent.

FIG. 3 shows a detailed circuit diagram of the A / D converter 308 according to FIG. 1. The input signal V (X) is fed to a bidirectional switch in the form of the switch 407 , the output signal of which goes to the voltage-controlled oscillator 402 , which is in a circuit with a phase-locked loop is included. The output signal of the voltage controlled oscillator 402 is supplied to the accumulator counter 400 , which consists of up / down counters CD4029A. The clock frequency f _clock is put together with a sampling pulse via lines 418 and 420 , in order to set the output signal of the accumulator counter 400 to the N-output counter 412 . A crucial part of the illustrated embodiment of the A / D converter 308 is the design of the control logic 408 , which according to FIG. 3 has a counter 409 in the form of a 4-bit ring counter. This counter 409 forces the A / D converter 308 to one and only one of four possible operating modes according to its four output states 0, 1, 2 and 3. These four operating modes of the A / D converter 308 according to FIG. 3 are: (1 ) Waiting; (2) preset; (3) count up and (4) count down.

The wait mode represents a quiescent state for the A / D converter 308 , in which the voltage-controlled oscillator 402 is switched off, the unknown voltage V (X) and the reference voltage E _ref are disconnected from the oscillator via the bidirectional switch 407 (S 1 ) and the last converted digital word is in the counter 412 as a digital, parallel 8-bit word. Converter 308 remains in the wait state until it receives a strobe pulse that causes the transition to preset mode. In the waiting state, the A / D converter 308 absorbs very little energy.

The presetting process following the waiting state is used to preset the accumulator counter 400 consisting of the counters 400 a, 400 b and 400 c to a binary word of one. The counter 412 is reset during this mode of operation. The maximum time available for the presetting is half a cycle period.

During the counting up, the output 3 of the ring counter 409 is brought to logic 1, whereby the counters 400 a, 400 b and 400 c are forced to count in the forward mode. During this operating mode, the bidirectional switch 407 (S 1 ) outputs the unknown analog input signal V (X) to the input of the voltage-controlled oscillator 402 . The n counter 410 begins to determine the period of time during which the unknown voltage is applied by counting the reference clock frequency up to the preprogrammed count that brings the output of an AND circuit 425 to logic 1. During this work phase, count values are accumulated in the counters 400 a, 400 b and 400 c. When the output of the AND circuit 425 jumps to logic 1, which indicates that the up-count period has been reached, outputs 8 and 9 are both at logic 1; an instruction to advance the ring counter 409 is sent to a pulse stretch gate 427 . When the next clock pulse reaches logic 1, the ring counter 409 is switched to the next state, which corresponds to the countdown.

A down counting operation is brought about by bringing the output 7 of the ring counter 409 to logic 1. This condition forces the accumulator counter 400 to count down. In addition, the reference voltage is applied to the voltage controlled oscillator 402 . The clock frequency f _clock is fed to the input of the N counter 412 . Therefore, when the count values are driven out of the counters 400 a, 400 b and 400 c, clock pulses are accumulated in the N counter 412 . When the accumulator counter chain is controlled to logic 0 in all states, the output of an AND circuit 429 jumps to logic 1. The ring counter 409 is brought to the waiting state via the pulse trapping network described above. The completion of this cycle causes the unknown input voltage V (X) to be digitized and held in the output counter 412 with the scale factor discussed above.

The A / D converter 308 shown in FIGS . 1 and 3 is particularly suitable for applications where it matters, the associated energy source, for. B. an operating voltage V _s battery to withdraw a minimum of Lei stung. For this purpose, the circuit arrangement according to FIG. 3 can be implemented in CMOS technology. Furthermore, the oscillator 402 is only supplied with energy for the purpose of supplying an output signal during those periods in which an analog input signal V (X) has to be digitized. At other times, voltage controlled oscillator 402 is de-energized. The oscillator 402 is supplied under the influence of the control logic 408 and in particular the ring counter 409 . In addition, the A / D converter 308 can be set by providing different values of "n" in the counter 410 . The A / D converter 308 is therefore suitable for detecting input voltages of widely differing amplitudes. According to FIG. 3, the preselected Vorwärtszähldauer T _up is determined by the value of "n", which is introduced into the n-counters 410th The value of "n" can be set according to one embodiment of the invention by connecting one of the multiple outputs Q 4 , Q 5 , Q 6 and Q 7 of the n counter 410 . A switching stage (not shown) can be provided between one of the outputs of the counter 410 and an AND circuit A 9 in order to subject the value of "n" to control by a microprocessor. In addition, a programmable counter known per se can be provided instead of the present counter 410 , which makes it possible to vary a binary word stored in the counter under the influence of the microprocessor. The value of "n" can thus be dependent change which analog input signal is to be converted into digital form. The value "n" is varied depending on the amplitude of the input voltage V (X) in question, larger values for "n" being provided for smaller amplitudes, in practice it is desirable to achieve a count value in the output counter 412 which is the Known counter capacity comes close to ensure the maximum resolution for an input signal of a given amplitude in this way. A single analog-to-digital converter 308 can thus be used for different input signals of varying amplitude, the accuracy of the binary output signal being ensured by varying the value of "n".

Claims (8)

1. Device for converting analog input signals into corresponding digital output signals with:

• (a) an oscillator ( 402 ) with an output for supplying a first output signal, the frequency of which depends on the signal supplied to its input,
• (b) a reference signal generator for generating a reference signal,
• (c) a switch ( 407 ) which is coupled to the input of the oscillator ( 402 ) and can be brought from a first position in which it supplies the analog input signals to the input of the oscillator into a second position in which it is connected to the input of the oscillator supplies the reference signal,
• (d) a first counter receiving the first output signal ( 400 which counts up in accordance with the frequency of the first output signal to form a second output signal in a first operating mode and counts down in a second operating mode,
• (e) a clock generator for supplying a clock signal and
• (f) a controller ( 408 ) receiving the clock signal for supplying a control signal after receiving a selected number of oscillations of the clock signal, the switch ( 407 ) in response to the control signal changing from the first to the second position, the first counter ( 400 ) in response to the control signal, the work in the first operating mode is ended, so that at this point in time the second output signal represents a first count value characterizing the analog input signal, and the first counter with the second operating mode starts to work from the first Count down from counting down,

marked by

• (g) a second counter ( 412 ) receiving the second output signal to form a corresponding third digital output signal,

wherein the second counter ( 412 ) in response to the control signal begins counting the oscillations of the clock signal and, when the second output signal reaches a second predetermined count value, stops counting the oscillations of the clock signal to form the third digital output signal, which is indicative of the analog input signal and is independent of the frequency of the clock signal. 2. Apparatus according to claim 1, characterized in that the controller ( 408 ) has a third counter ( 410 ) which counts n oscillations of the clock signal and then outputs the control signal and which has a device for a changeable setting of the value of n is provided. 3. Apparatus according to claim 2, characterized in that the third counter ( 410 ) has a device for recording and storing a characteristic value for n. 4. Device according to one of the preceding claims, characterized in that the controller ( 408 ) has an activation device which, in response to a scanning signal characterizing the presence of an analog input signal to be converted, activates the oscillator ( 402 ) for a time period which corresponds to the time period, which is required to make the first counter ( 400 ) operate in the first and second operating modes in order to convert the analog input signals into the corresponding third digital output signals. 5. The device according to claim 4, characterized in that the activation device a ring counter with a first output, which is characteristic for the period within which the oscillator ( 402 ) is deactivated, a second output, which is characteristic of the first mode of operation is first counter ( 400 ), and has a third output, which is characteristic of the second operating mode of the first counter. 6. Device according to one of the preceding claims, characterized records that the device parts designed as CMOS components are.