SE411813B - Sett att framstella en halvledaranordning och enligt settet framstelld halvledaranordning - Google Patents
Sett att framstella en halvledaranordning och enligt settet framstelld halvledaranordningInfo
- Publication number
- SE411813B SE411813B SE7513565A SE7513565A SE411813B SE 411813 B SE411813 B SE 411813B SE 7513565 A SE7513565 A SE 7513565A SE 7513565 A SE7513565 A SE 7513565A SE 411813 B SE411813 B SE 411813B
- Authority
- SE
- Sweden
- Prior art keywords
- semiconductor device
- settlement
- manufacture
- semiconductor
- settlement semiconductor
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 2
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL7415841A NL7415841A (nl) | 1974-12-05 | 1974-12-05 | Werkwijze voor het vervaardigen van een half- geleiderinrichting en halfgeleiderinrichting, vervaardigd volgens de werkwijze. |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| SE7513565L SE7513565L (sv) | 1976-06-08 |
| SE411813B true SE411813B (sv) | 1980-02-04 |
Family
ID=19822593
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SE7513565A SE411813B (sv) | 1974-12-05 | 1975-12-02 | Sett att framstella en halvledaranordning och enligt settet framstelld halvledaranordning |
Country Status (10)
| Country | Link |
|---|---|
| JP (1) | JPS5182569A (en, 2012) |
| AU (1) | AU499832B2 (en, 2012) |
| CA (1) | CA1042114A (en, 2012) |
| CH (1) | CH595698A5 (en, 2012) |
| DE (1) | DE2552430A1 (en, 2012) |
| FR (1) | FR2293794A1 (en, 2012) |
| GB (1) | GB1525400A (en, 2012) |
| IT (1) | IT1051815B (en, 2012) |
| NL (1) | NL7415841A (en, 2012) |
| SE (1) | SE411813B (en, 2012) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2340620A1 (fr) * | 1976-02-06 | 1977-09-02 | Ibm | Procede de fabrication d'un dispositif integre a grande echelle ayant une surface plane |
| FR2535525A1 (fr) * | 1982-10-29 | 1984-05-04 | Western Electric Co | Procede de fabrication de circuits integres comportant des couches isolantes minces |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3642528A (en) * | 1968-06-05 | 1972-02-15 | Matsushita Electronics Corp | Semiconductor device and method of making same |
| JPS4918268A (en, 2012) * | 1972-06-09 | 1974-02-18 |
-
1974
- 1974-12-05 NL NL7415841A patent/NL7415841A/xx not_active Application Discontinuation
-
1975
- 1975-11-22 DE DE19752552430 patent/DE2552430A1/de not_active Ceased
- 1975-11-27 CA CA240,755A patent/CA1042114A/en not_active Expired
- 1975-12-02 CH CH1566375A patent/CH595698A5/xx not_active IP Right Cessation
- 1975-12-02 AU AU87152/75A patent/AU499832B2/en not_active Expired
- 1975-12-02 IT IT29937/75A patent/IT1051815B/it active
- 1975-12-02 SE SE7513565A patent/SE411813B/xx unknown
- 1975-12-02 GB GB49418/75A patent/GB1525400A/en not_active Expired
- 1975-12-04 JP JP50143433A patent/JPS5182569A/ja active Pending
- 1975-12-05 FR FR7537270A patent/FR2293794A1/fr active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| SE7513565L (sv) | 1976-06-08 |
| NL7415841A (nl) | 1976-06-09 |
| IT1051815B (it) | 1981-05-20 |
| GB1525400A (en) | 1978-09-20 |
| JPS5182569A (en) | 1976-07-20 |
| AU8715275A (en) | 1977-06-09 |
| DE2552430A1 (de) | 1976-06-10 |
| AU499832B2 (en) | 1979-05-03 |
| CH595698A5 (en, 2012) | 1978-02-28 |
| CA1042114A (en) | 1978-11-07 |
| FR2293794B1 (en, 2012) | 1981-08-07 |
| FR2293794A1 (fr) | 1976-07-02 |
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