SE412488B - Halvledarkomponentbricka och sett att framstella densamma - Google Patents
Halvledarkomponentbricka och sett att framstella densammaInfo
- Publication number
- SE412488B SE412488B SE7613202A SE7613202A SE412488B SE 412488 B SE412488 B SE 412488B SE 7613202 A SE7613202 A SE 7613202A SE 7613202 A SE7613202 A SE 7613202A SE 412488 B SE412488 B SE 412488B
- Authority
- SE
- Sweden
- Prior art keywords
- manufacture
- way
- semiconductor component
- component issue
- issue
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thyristors (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05/635,747 US4063272A (en) | 1975-11-26 | 1975-11-26 | Semiconductor device and method of manufacture thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
SE7613202L SE7613202L (sv) | 1977-05-27 |
SE412488B true SE412488B (sv) | 1980-03-03 |
Family
ID=24548955
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SE7613202A SE412488B (sv) | 1975-11-26 | 1976-11-25 | Halvledarkomponentbricka och sett att framstella densamma |
Country Status (6)
Country | Link |
---|---|
US (2) | US4063272A (sv) |
JP (1) | JPS5279655A (sv) |
DE (1) | DE2653297A1 (sv) |
FR (1) | FR2333350A1 (sv) |
GB (1) | GB1553730A (sv) |
SE (1) | SE412488B (sv) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS584814B2 (ja) * | 1976-04-27 | 1983-01-27 | 三菱電機株式会社 | 半導体装置 |
US4180416A (en) * | 1978-09-27 | 1979-12-25 | International Business Machines Corporation | Thermal migration-porous silicon technique for forming deep dielectric isolation |
US4235645A (en) * | 1978-12-15 | 1980-11-25 | Westinghouse Electric Corp. | Process for forming glass-sealed multichip semiconductor devices |
DE3331298A1 (de) * | 1983-08-31 | 1985-03-14 | Brown, Boveri & Cie Ag, 6800 Mannheim | Leistungsthyristor auf einem substrat |
DE3841149A1 (de) * | 1988-12-07 | 1990-06-13 | Asea Brown Boveri | Verfahren zur herstellung einer leistungshalbleiterdiode |
DE4109533C2 (de) * | 1990-09-13 | 1994-06-23 | Eupec Gmbh & Co Kg | Passiviertes Halbleiterbauelement und Verfahren zu seiner Herstellung |
DE4317721C1 (de) * | 1993-05-27 | 1994-07-21 | Siemens Ag | Verfahren zur Vereinzelung von Chips aus einem Wafer |
TW483093B (en) * | 1999-04-22 | 2002-04-11 | Int Rectifier Corp | Chip scale package |
US7683464B2 (en) * | 2005-09-13 | 2010-03-23 | Alpha And Omega Semiconductor Incorporated | Semiconductor package having dimpled plate interconnections |
US20070057368A1 (en) * | 2005-09-13 | 2007-03-15 | Yueh-Se Ho | Semiconductor package having plate interconnections |
US7622796B2 (en) * | 2005-09-13 | 2009-11-24 | Alpha And Omega Semiconductor Limited | Semiconductor package having a bridged plate interconnection |
US8680658B2 (en) * | 2008-05-30 | 2014-03-25 | Alpha And Omega Semiconductor Incorporated | Conductive clip for semiconductor device package |
CN105453250A (zh) * | 2013-08-08 | 2016-03-30 | 夏普株式会社 | 半导体元件衬底及其制造方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1110993A (en) * | 1967-01-09 | 1968-04-24 | Standard Telephones Cables Ltd | Semiconductors |
US3535774A (en) * | 1968-07-09 | 1970-10-27 | Rca Corp | Method of fabricating semiconductor devices |
US3628106A (en) * | 1969-05-05 | 1971-12-14 | Gen Electric | Passivated semiconductor device with protective peripheral junction portion |
NL161301C (nl) * | 1972-12-29 | 1980-01-15 | Philips Nv | Halfgeleiderinrichting en werkwijze voor de vervaar- diging daarvan. |
US3908187A (en) * | 1973-01-02 | 1975-09-23 | Gen Electric | High voltage power transistor and method for making |
US3972113A (en) * | 1973-05-14 | 1976-08-03 | Mitsubishi Denki Kabushiki Kaisha | Process of producing semiconductor devices |
US3904442A (en) * | 1973-10-30 | 1975-09-09 | Gen Electric | Method of making isolation grids in bodies of semiconductor material |
US3979230A (en) * | 1973-10-30 | 1976-09-07 | General Electric Company | Method of making isolation grids in bodies of semiconductor material |
US3896477A (en) * | 1973-11-07 | 1975-07-22 | Jearld L Hutson | Multilayer semiconductor switching devices |
US3982269A (en) * | 1974-11-22 | 1976-09-21 | General Electric Company | Semiconductor devices and method, including TGZM, of making same |
GB1536545A (en) * | 1975-03-26 | 1978-12-20 | Mullard Ltd | Semiconductor device manufacture |
US4010534A (en) * | 1975-06-27 | 1977-03-08 | General Electric Company | Process for making a deep diode atomic battery |
-
1975
- 1975-11-26 US US05/635,747 patent/US4063272A/en not_active Expired - Lifetime
-
1976
- 1976-11-15 GB GB47427/76A patent/GB1553730A/en not_active Expired
- 1976-11-24 FR FR7635356A patent/FR2333350A1/fr active Granted
- 1976-11-24 DE DE19762653297 patent/DE2653297A1/de not_active Ceased
- 1976-11-25 SE SE7613202A patent/SE412488B/sv not_active IP Right Cessation
- 1976-11-26 JP JP51141342A patent/JPS5279655A/ja active Pending
-
1977
- 1977-02-11 US US05/767,946 patent/US4104786A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
FR2333350A1 (fr) | 1977-06-24 |
JPS5279655A (en) | 1977-07-04 |
US4063272A (en) | 1977-12-13 |
SE7613202L (sv) | 1977-05-27 |
GB1553730A (en) | 1979-09-26 |
DE2653297A1 (de) | 1977-06-08 |
FR2333350B1 (sv) | 1982-08-27 |
US4104786A (en) | 1978-08-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
NUG | Patent has lapsed |
Ref document number: 7613202-6 Effective date: 19891114 Format of ref document f/p: F |