SE0001029D0 - Phase-locked loop based clock phasing implementing a virtual delay - Google Patents

Phase-locked loop based clock phasing implementing a virtual delay

Info

Publication number
SE0001029D0
SE0001029D0 SE0001029A SE0001029A SE0001029D0 SE 0001029 D0 SE0001029 D0 SE 0001029D0 SE 0001029 A SE0001029 A SE 0001029A SE 0001029 A SE0001029 A SE 0001029A SE 0001029 D0 SE0001029 D0 SE 0001029D0
Authority
SE
Sweden
Prior art keywords
delay
pll
control loop
signal
phase
Prior art date
Application number
SE0001029A
Other languages
English (en)
Other versions
SE0001029L (sv
SE517967C2 (sv
Inventor
Jonas Jesper Fredriksson
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE0001029A priority Critical patent/SE517967C2/sv
Publication of SE0001029D0 publication Critical patent/SE0001029D0/sv
Priority to AT01904686T priority patent/ATE292859T1/de
Priority to DE60109912T priority patent/DE60109912T2/de
Priority to AU2001232515A priority patent/AU2001232515A1/en
Priority to PCT/SE2001/000174 priority patent/WO2001071920A1/en
Priority to EP01904686A priority patent/EP1277285B1/en
Priority to US09/815,984 priority patent/US6366146B2/en
Publication of SE0001029L publication Critical patent/SE0001029L/sv
Publication of SE517967C2 publication Critical patent/SE517967C2/sv

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/143—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Networks Using Active Elements (AREA)
SE0001029A 2000-03-23 2000-03-23 System och förfarande för klocksignalgenerering SE517967C2 (sv)

Priority Applications (7)

Application Number Priority Date Filing Date Title
SE0001029A SE517967C2 (sv) 2000-03-23 2000-03-23 System och förfarande för klocksignalgenerering
AT01904686T ATE292859T1 (de) 2000-03-23 2001-01-31 Taktphasensteuerung auf phasenregelkreisbasis zur implementierung einer virtuellen verzögerung
DE60109912T DE60109912T2 (de) 2000-03-23 2001-01-31 Taktphasensteuerung auf phasenregelkreisbasis zur implementierung einer virtuellen verzögerung
AU2001232515A AU2001232515A1 (en) 2000-03-23 2001-01-31 Phase-locked loop based clock phasing implementing a virtual delay
PCT/SE2001/000174 WO2001071920A1 (en) 2000-03-23 2001-01-31 Phase-locked loop based clock phasing implementing a virtual delay
EP01904686A EP1277285B1 (en) 2000-03-23 2001-01-31 Phase-locked loop based clock phasing implementing a virtual delay
US09/815,984 US6366146B2 (en) 2000-03-23 2001-03-23 Phase-locked loop based clock phasing implementing a virtual delay

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE0001029A SE517967C2 (sv) 2000-03-23 2000-03-23 System och förfarande för klocksignalgenerering

Publications (3)

Publication Number Publication Date
SE0001029D0 true SE0001029D0 (sv) 2000-03-23
SE0001029L SE0001029L (sv) 2001-09-24
SE517967C2 SE517967C2 (sv) 2002-08-06

Family

ID=20278984

Family Applications (1)

Application Number Title Priority Date Filing Date
SE0001029A SE517967C2 (sv) 2000-03-23 2000-03-23 System och förfarande för klocksignalgenerering

Country Status (7)

Country Link
US (1) US6366146B2 (sv)
EP (1) EP1277285B1 (sv)
AT (1) ATE292859T1 (sv)
AU (1) AU2001232515A1 (sv)
DE (1) DE60109912T2 (sv)
SE (1) SE517967C2 (sv)
WO (1) WO2001071920A1 (sv)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8385476B2 (en) * 2001-04-25 2013-02-26 Texas Instruments Incorporated Digital phase locked loop
DE60238353D1 (de) * 2002-02-14 2010-12-30 Ericsson Telefon Ab L M Nahtloser takt
US6741109B1 (en) * 2002-02-28 2004-05-25 Silicon Laboratories, Inc. Method and apparatus for switching between input clocks in a phase-locked loop
US6920622B1 (en) 2002-02-28 2005-07-19 Silicon Laboratories Inc. Method and apparatus for adjusting the phase of an output of a phase-locked loop
CN100373776C (zh) * 2002-06-28 2008-03-05 先进微装置公司 具有自动频率调整的锁相回路
KR100976375B1 (ko) * 2002-09-06 2010-08-18 텔레포나크티에볼라게트 엘엠 에릭슨(피유비엘) 2점 위상변조기의 트리밍
US6806751B2 (en) 2002-09-12 2004-10-19 Foundry Networks, Inc. Loop filter for a phase-locked loop and method for switching
US6803797B2 (en) * 2003-01-31 2004-10-12 Intel Corporation System and method for extending delay-locked loop frequency application range
US7330508B2 (en) * 2003-12-19 2008-02-12 Broadcom Corporation Using clock and data recovery phase adjust to set loop delay of a decision feedback equalizer
US7822113B2 (en) * 2003-12-19 2010-10-26 Broadcom Corporation Integrated decision feedback equalizer and clock and data recovery
US20060256821A1 (en) * 2005-05-13 2006-11-16 Peter Richards Signal synchronization in display systems
GB2430090B (en) * 2005-09-08 2007-10-17 Motorola Inc RF synthesizer and RF transmitter or receiver incorporating the synthesizer
DE102006024469B3 (de) * 2006-05-24 2007-07-12 Xignal Technologies Ag Phasenregelkreis zur Erzeugung mehrerer Ausgangssignale
DE102006024471A1 (de) * 2006-05-24 2007-12-06 Xignal Technologies Ag Umschaltbarer Phasenregelkreis sowie Verfahren zum Betrieb eines umschaltbaren Phasenregelkreises
EP2027653A1 (en) * 2006-06-14 2009-02-25 Telefonaktiebolaget Lm Ericsson Frequency synthesizer
US7405628B2 (en) * 2006-09-29 2008-07-29 Silicon Laboratories Inc. Technique for switching between input clocks in a phase-locked loop
US7443250B2 (en) * 2006-09-29 2008-10-28 Silicon Laboratories Inc. Programmable phase-locked loop responsive to a selected bandwidth and a selected reference clock signal frequency to adjust circuit characteristics
US20090302904A1 (en) * 2008-06-10 2009-12-10 International Business Machines Corporation Phase Frequency Detector Circuit for Implementing Low PLL Phase Noise and Low Phase Error
US7885030B2 (en) * 2008-07-07 2011-02-08 International Business Machines Corporation Methods and systems for delay compensation in global PLL-based timing recovery loops
CN103001720B (zh) * 2012-11-12 2017-05-10 中兴通讯股份有限公司 时间同步方法和装置
JP5880603B2 (ja) * 2014-03-19 2016-03-09 日本電気株式会社 クロック発生装置、サーバシステムおよびクロック制御方法
DE102014210521A1 (de) * 2014-06-03 2015-12-03 Continental Teves Ag & Co. Ohg Jitterkompensation im Taktgenerator eines Drehratensensors
US10514720B1 (en) 2018-06-19 2019-12-24 Aura Semiconductor Pvt. Ltd Hitless switching when generating an output clock derived from multiple redundant input clocks
US11588489B1 (en) 2021-10-06 2023-02-21 Shaoxing Yuanfang Semiconductor Co., Ltd. Obtaining lock in a phase-locked loop (PLL) upon being out of phase-lock
US11923864B2 (en) 2021-10-18 2024-03-05 Shaoxing Yuanfang Semiconductor Co., Ltd. Fast switching of output frequency of a phase locked loop (PLL)
US11967965B2 (en) 2021-11-03 2024-04-23 Shaoxing Yuanfang Semiconductor Co., Ltd. Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0364679B1 (de) * 1988-10-18 1994-11-02 Siemens-Albis Aktiengesellschaft Frequenzsynthesegerät
US5339278A (en) * 1993-04-12 1994-08-16 Motorola, Inc. Method and apparatus for standby recovery in a phase locked loop
US5638410A (en) 1993-10-14 1997-06-10 Alcatel Network Systems, Inc. Method and system for aligning the phase of high speed clocks in telecommunications systems
CA2130871C (en) * 1993-11-05 1999-09-28 John M. Alder Method and apparatus for a phase-locked loop circuit with holdover mode
JP2788855B2 (ja) * 1994-06-22 1998-08-20 日本電気株式会社 Ｐｌｌ回路装置
GB2293062B (en) 1994-09-09 1996-12-04 Toshiba Kk Master-slave multiplex communication system and PLL circuit applied to the system
DE4442306C2 (de) * 1994-11-28 1997-12-18 Siemens Ag Verfahren und Anordnung zur Ermittlung von Phasenänderungen eines Referenz-Eingangssignals eines Phasenregelkreises
JPH118813A (ja) 1997-06-18 1999-01-12 Sony Corp 位相同期ループ回路

Also Published As

Publication number Publication date
EP1277285B1 (en) 2005-04-06
EP1277285A1 (en) 2003-01-22
DE60109912T2 (de) 2006-04-27
US6366146B2 (en) 2002-04-02
AU2001232515A1 (en) 2001-10-03
SE0001029L (sv) 2001-09-24
US20010030559A1 (en) 2001-10-18
ATE292859T1 (de) 2005-04-15
SE517967C2 (sv) 2002-08-06
DE60109912D1 (de) 2005-05-12
WO2001071920A1 (en) 2001-09-27

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