AU2001232515A1 - Phase-locked loop based clock phasing implementing a virtual delay - Google Patents

Phase-locked loop based clock phasing implementing a virtual delay

Info

Publication number
AU2001232515A1
AU2001232515A1 AU2001232515A AU3251501A AU2001232515A1 AU 2001232515 A1 AU2001232515 A1 AU 2001232515A1 AU 2001232515 A AU2001232515 A AU 2001232515A AU 3251501 A AU3251501 A AU 3251501A AU 2001232515 A1 AU2001232515 A1 AU 2001232515A1
Authority
AU
Australia
Prior art keywords
delay
pll
control loop
signal
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001232515A
Inventor
Jesper Fredriksson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of AU2001232515A1 publication Critical patent/AU2001232515A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/143—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Networks Using Active Elements (AREA)

Abstract

The invention relates to reference handover in clock signal generation systems and similar applications. The idea according to the invention is to introduce a so-called "virtual" delay in the control loop of a PLL (10) for the purpose of forcing the control loop to shift the phase of the PLL output clock signal (VCOout), while still maintaining the mandatory phase lock condition of the PLL relative to a primary reference signal (MREF), towards a predetermined target phase relation with the primary reference signal. By utilizing a virtual delay ("DELTAT"), the problems associated with explicit delay elements such as passive or active delay lines are avoided, and a more robust and accurate clock phasing mechanism is obtained. Preferably, the virtual delay is introduced by superimposing an external phasing control signal in the control loop of the PLL (10) on the output signal/input signal of a control loop element.
AU2001232515A 2000-03-23 2001-01-31 Phase-locked loop based clock phasing implementing a virtual delay Abandoned AU2001232515A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE0001029 2000-03-23
SE0001029A SE517967C2 (en) 2000-03-23 2000-03-23 Clock signal generation system and method
PCT/SE2001/000174 WO2001071920A1 (en) 2000-03-23 2001-01-31 Phase-locked loop based clock phasing implementing a virtual delay

Publications (1)

Publication Number Publication Date
AU2001232515A1 true AU2001232515A1 (en) 2001-10-03

Family

ID=20278984

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001232515A Abandoned AU2001232515A1 (en) 2000-03-23 2001-01-31 Phase-locked loop based clock phasing implementing a virtual delay

Country Status (7)

Country Link
US (1) US6366146B2 (en)
EP (1) EP1277285B1 (en)
AT (1) ATE292859T1 (en)
AU (1) AU2001232515A1 (en)
DE (1) DE60109912T2 (en)
SE (1) SE517967C2 (en)
WO (1) WO2001071920A1 (en)

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US8385476B2 (en) * 2001-04-25 2013-02-26 Texas Instruments Incorporated Digital phase locked loop
US7386079B2 (en) 2002-02-14 2008-06-10 Telefonaktiebolaget Lm Ericsson (Publ) Seamless clock
US6741109B1 (en) * 2002-02-28 2004-05-25 Silicon Laboratories, Inc. Method and apparatus for switching between input clocks in a phase-locked loop
US6920622B1 (en) 2002-02-28 2005-07-19 Silicon Laboratories Inc. Method and apparatus for adjusting the phase of an output of a phase-locked loop
JP2005532016A (en) * 2002-06-28 2005-10-20 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Automatic frequency tuning phase lock loop
WO2004034564A2 (en) * 2002-09-06 2004-04-22 Telefonaktiebolaget Lm Ericsson (Publ) Trimming of a two point phase modulator
US6806751B2 (en) 2002-09-12 2004-10-19 Foundry Networks, Inc. Loop filter for a phase-locked loop and method for switching
US6803797B2 (en) * 2003-01-31 2004-10-12 Intel Corporation System and method for extending delay-locked loop frequency application range
US7822113B2 (en) * 2003-12-19 2010-10-26 Broadcom Corporation Integrated decision feedback equalizer and clock and data recovery
US7330508B2 (en) * 2003-12-19 2008-02-12 Broadcom Corporation Using clock and data recovery phase adjust to set loop delay of a decision feedback equalizer
US20060256821A1 (en) * 2005-05-13 2006-11-16 Peter Richards Signal synchronization in display systems
GB2430090B (en) * 2005-09-08 2007-10-17 Motorola Inc RF synthesizer and RF transmitter or receiver incorporating the synthesizer
DE102006024471A1 (en) * 2006-05-24 2007-12-06 Xignal Technologies Ag Switchable phase-locked loop and method for operating a switchable phase-locked loop
DE102006024469B3 (en) * 2006-05-24 2007-07-12 Xignal Technologies Ag Phase locked loop for communication system, has phase detector with phase interpolator and sampler to generate preset version of loop`s output signal and to determine phase difference between clock signal and version, respectively
EP2027653A1 (en) * 2006-06-14 2009-02-25 Telefonaktiebolaget Lm Ericsson Frequency synthesizer
US7443250B2 (en) * 2006-09-29 2008-10-28 Silicon Laboratories Inc. Programmable phase-locked loop responsive to a selected bandwidth and a selected reference clock signal frequency to adjust circuit characteristics
US7405628B2 (en) * 2006-09-29 2008-07-29 Silicon Laboratories Inc. Technique for switching between input clocks in a phase-locked loop
US20090302904A1 (en) * 2008-06-10 2009-12-10 International Business Machines Corporation Phase Frequency Detector Circuit for Implementing Low PLL Phase Noise and Low Phase Error
US7885030B2 (en) * 2008-07-07 2011-02-08 International Business Machines Corporation Methods and systems for delay compensation in global PLL-based timing recovery loops
CN103001720B (en) * 2012-11-12 2017-05-10 中兴通讯股份有限公司 Time synchronization method and device
JP5880603B2 (en) * 2014-03-19 2016-03-09 日本電気株式会社 Clock generator, server system, and clock control method
DE102014210521A1 (en) * 2014-06-03 2015-12-03 Continental Teves Ag & Co. Ohg Jitter compensation in the clock generator of a rotation rate sensor
US10514720B1 (en) 2018-06-19 2019-12-24 Aura Semiconductor Pvt. Ltd Hitless switching when generating an output clock derived from multiple redundant input clocks
US11588489B1 (en) 2021-10-06 2023-02-21 Shaoxing Yuanfang Semiconductor Co., Ltd. Obtaining lock in a phase-locked loop (PLL) upon being out of phase-lock
US11923864B2 (en) 2021-10-18 2024-03-05 Shaoxing Yuanfang Semiconductor Co., Ltd. Fast switching of output frequency of a phase locked loop (PLL)
US11967965B2 (en) 2021-11-03 2024-04-23 Shaoxing Yuanfang Semiconductor Co., Ltd. Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0364679B1 (en) * 1988-10-18 1994-11-02 Siemens-Albis Aktiengesellschaft Frequency synthesizer apparatus
US5339278A (en) * 1993-04-12 1994-08-16 Motorola, Inc. Method and apparatus for standby recovery in a phase locked loop
US5638410A (en) 1993-10-14 1997-06-10 Alcatel Network Systems, Inc. Method and system for aligning the phase of high speed clocks in telecommunications systems
CA2130871C (en) * 1993-11-05 1999-09-28 John M. Alder Method and apparatus for a phase-locked loop circuit with holdover mode
JP2788855B2 (en) * 1994-06-22 1998-08-20 日本電気株式会社 PLL circuit device
GB2293062B (en) 1994-09-09 1996-12-04 Toshiba Kk Master-slave multiplex communication system and PLL circuit applied to the system
DE4442306C2 (en) * 1994-11-28 1997-12-18 Siemens Ag Method and arrangement for determining phase changes in a reference input signal of a phase locked loop
JPH118813A (en) 1997-06-18 1999-01-12 Sony Corp Phase locked loop circuit

Also Published As

Publication number Publication date
EP1277285A1 (en) 2003-01-22
DE60109912T2 (en) 2006-04-27
ATE292859T1 (en) 2005-04-15
DE60109912D1 (en) 2005-05-12
WO2001071920A1 (en) 2001-09-27
SE0001029L (en) 2001-09-24
US20010030559A1 (en) 2001-10-18
SE0001029D0 (en) 2000-03-23
SE517967C2 (en) 2002-08-06
EP1277285B1 (en) 2005-04-06
US6366146B2 (en) 2002-04-02

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