RU94013073A - Device for control of regeneration in semiconductor dynamic memory unit - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has first and second clock pulse oscillators 1 and 2, first and second flip-flops 3 and 4, first and second bus generators 6 and 5 local control unit 7, counters 8, decoder 9, encoder 10, register 11, AND gate 12, OR gate 13. Central processing unit 14 and memory unit 15 of computer are connected to device. In addition device has terminal 16 for request of direct memory access, terminal 17 for permission of direct memory access, terminal 18 for acknowledge of channel access, address line 19, memory control line 20, outputs group 21 and inputs group 22 of local control unit 7, synchronization signal output 24, writing permission signal output 25, strobe signal output 26, reset signal output 27, synchronization input 28 of local control unit 7. In addition device has delay gate 29, group of flip-flops 30.1, ..., 30.i, ..., 30.n, group of AND gates 31.1, ..., 31.i, ...., 31.n, unit 32 which generates code for control of regeneration frequency, group 33 of detectors which measure intensity of external physical fields, writing strobe input 34. Device may be used in special computers that are exposed to heavy physical fields with variable intensity. EFFECT: increased reliability. 1 dwg

Claims (1)

The invention relates to computer technology and can be used to restore information in semiconductor dynamic storage devices that are part of specialized computers that are exposed during operation to physical fields of high intensity. The device contains first 1 and second 2 clock generators, first 3 and second 4 triggers, second 5 and first 6 bus drivers, local control unit 7, counters 8, decoder 9, encoder 10, register 11, AND element 12, OR element 13 The computer elements interacting with the device, the Central processor 14 and RAM 15, which is used as a semiconductor DZU. In addition, the device contains an output 16 of the direct memory access (DAP) requirement, an RAP submission input 17, a channel acquisition acknowledgment (PZ) output 18, an address bus 19, a memory management bus 20, an output group 21 and an input group 22 of the local control unit 7 , input 23 of the operating mode of the local control unit 7, output 24 of the synchronization signal, output 25 of the write enable signal, output 26 of the strobe signal, output 27 of the reset signal, sync input 28 of the local control unit 7. In addition, the device contains a delay element 29, a group of triggers 30.1 ,. . ..30.i, ..., 30.n, a group of elements And 31.1, ..., 31.i ....., 31.n, a block 32 for generating a regeneration frequency control code, a group 33 of measuring sensors of external parameters physical fields and input 34 gating records. 1 ill.